1 /** 2 * @file rtc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup rtc_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_RTC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_RTC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup rtc 67 * @defgroup rtc_registers RTC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. 69 * @details Real Time Clock and Alarm. 70 */ 71 72 /** 73 * @ingroup rtc_registers 74 * Structure type to access the RTC Registers. 75 */ 76 typedef struct { 77 __IO uint32_t sec; /**< <tt>\b 0x00:</tt> RTC SEC Register */ 78 __IO uint32_t ssec; /**< <tt>\b 0x04:</tt> RTC SSEC Register */ 79 __IO uint32_t ras; /**< <tt>\b 0x08:</tt> RTC RAS Register */ 80 __IO uint32_t rssa; /**< <tt>\b 0x0C:</tt> RTC RSSA Register */ 81 __IO uint32_t ctrl; /**< <tt>\b 0x10:</tt> RTC CTRL Register */ 82 __IO uint32_t trim; /**< <tt>\b 0x14:</tt> RTC TRIM Register */ 83 __IO uint32_t oscctrl; /**< <tt>\b 0x18:</tt> RTC OSCCTRL Register */ 84 } mxc_rtc_regs_t; 85 86 /* Register offsets for module RTC */ 87 /** 88 * @ingroup rtc_registers 89 * @defgroup RTC_Register_Offsets Register Offsets 90 * @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address. 91 * @{ 92 */ 93 #define MXC_R_RTC_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: <tt> 0x0000</tt> */ 94 #define MXC_R_RTC_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: <tt> 0x0004</tt> */ 95 #define MXC_R_RTC_RAS ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: <tt> 0x0008</tt> */ 96 #define MXC_R_RTC_RSSA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: <tt> 0x000C</tt> */ 97 #define MXC_R_RTC_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: <tt> 0x0010</tt> */ 98 #define MXC_R_RTC_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: <tt> 0x0014</tt> */ 99 #define MXC_R_RTC_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: <tt> 0x0018</tt> */ 100 /**@} end of group rtc_registers */ 101 102 /** 103 * @ingroup rtc_registers 104 * @defgroup RTC_SEC RTC_SEC 105 * @brief RTC Second Counter. This register contains the 32-bit second counter. 106 * @{ 107 */ 108 #define MXC_F_RTC_SEC_SEC_POS 0 /**< SEC_SEC Position */ 109 #define MXC_F_RTC_SEC_SEC ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_SEC_SEC_POS)) /**< SEC_SEC Mask */ 110 111 /**@} end of group RTC_SEC_Register */ 112 113 /** 114 * @ingroup rtc_registers 115 * @defgroup RTC_SSEC RTC_SSEC 116 * @brief RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented 117 * when this register rolls over from 0xFF to 0x00. 118 * @{ 119 */ 120 #define MXC_F_RTC_SSEC_RTSS_POS 0 /**< SSEC_RTSS Position */ 121 #define MXC_F_RTC_SSEC_RTSS ((uint32_t)(0xFFUL << MXC_F_RTC_SSEC_RTSS_POS)) /**< SSEC_RTSS Mask */ 122 123 /**@} end of group RTC_SSEC_Register */ 124 125 /** 126 * @ingroup rtc_registers 127 * @defgroup RTC_RAS RTC_RAS 128 * @brief Time-of-day Alarm. 129 * @{ 130 */ 131 #define MXC_F_RTC_RAS_RAS_POS 0 /**< RAS_RAS Position */ 132 #define MXC_F_RTC_RAS_RAS ((uint32_t)(0xFFFFFUL << MXC_F_RTC_RAS_RAS_POS)) /**< RAS_RAS Mask */ 133 134 /**@} end of group RTC_RAS_Register */ 135 136 /** 137 * @ingroup rtc_registers 138 * @defgroup RTC_RSSA RTC_RSSA 139 * @brief RTC sub-second alarm. This register contains the reload value for the sub- 140 * second alarm. 141 * @{ 142 */ 143 #define MXC_F_RTC_RSSA_RSSA_POS 0 /**< RSSA_RSSA Position */ 144 #define MXC_F_RTC_RSSA_RSSA ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_RSSA_RSSA_POS)) /**< RSSA_RSSA Mask */ 145 146 /**@} end of group RTC_RSSA_Register */ 147 148 /** 149 * @ingroup rtc_registers 150 * @defgroup RTC_CTRL RTC_CTRL 151 * @brief RTC Control Register. 152 * @{ 153 */ 154 #define MXC_F_RTC_CTRL_RTCE_POS 0 /**< CTRL_RTCE Position */ 155 #define MXC_F_RTC_CTRL_RTCE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RTCE_POS)) /**< CTRL_RTCE Mask */ 156 157 #define MXC_F_RTC_CTRL_ADE_POS 1 /**< CTRL_ADE Position */ 158 #define MXC_F_RTC_CTRL_ADE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ADE_POS)) /**< CTRL_ADE Mask */ 159 160 #define MXC_F_RTC_CTRL_ASE_POS 2 /**< CTRL_ASE Position */ 161 #define MXC_F_RTC_CTRL_ASE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ASE_POS)) /**< CTRL_ASE Mask */ 162 163 #define MXC_F_RTC_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */ 164 #define MXC_F_RTC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ 165 166 #define MXC_F_RTC_CTRL_RDY_POS 4 /**< CTRL_RDY Position */ 167 #define MXC_F_RTC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ 168 169 #define MXC_F_RTC_CTRL_RDYE_POS 5 /**< CTRL_RDYE Position */ 170 #define MXC_F_RTC_CTRL_RDYE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDYE_POS)) /**< CTRL_RDYE Mask */ 171 172 #define MXC_F_RTC_CTRL_ALDF_POS 6 /**< CTRL_ALDF Position */ 173 #define MXC_F_RTC_CTRL_ALDF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALDF_POS)) /**< CTRL_ALDF Mask */ 174 175 #define MXC_F_RTC_CTRL_ALSF_POS 7 /**< CTRL_ALSF Position */ 176 #define MXC_F_RTC_CTRL_ALSF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALSF_POS)) /**< CTRL_ALSF Mask */ 177 178 #define MXC_F_RTC_CTRL_SQE_POS 8 /**< CTRL_SQE Position */ 179 #define MXC_F_RTC_CTRL_SQE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQE_POS)) /**< CTRL_SQE Mask */ 180 181 #define MXC_F_RTC_CTRL_FT_POS 9 /**< CTRL_FT Position */ 182 #define MXC_F_RTC_CTRL_FT ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_FT_POS)) /**< CTRL_FT Mask */ 183 #define MXC_V_RTC_CTRL_FT_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_FT_FREQ1HZ Value */ 184 #define MXC_S_RTC_CTRL_FT_FREQ1HZ (MXC_V_RTC_CTRL_FT_FREQ1HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ1HZ Setting */ 185 #define MXC_V_RTC_CTRL_FT_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_FT_FREQ512HZ Value */ 186 #define MXC_S_RTC_CTRL_FT_FREQ512HZ (MXC_V_RTC_CTRL_FT_FREQ512HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ512HZ Setting */ 187 #define MXC_V_RTC_CTRL_FT_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_FT_FREQ4KHZ Value */ 188 #define MXC_S_RTC_CTRL_FT_FREQ4KHZ (MXC_V_RTC_CTRL_FT_FREQ4KHZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ4KHZ Setting */ 189 #define MXC_V_RTC_CTRL_FT_CLKDIV8 ((uint32_t)0x3UL) /**< CTRL_FT_CLKDIV8 Value */ 190 #define MXC_S_RTC_CTRL_FT_CLKDIV8 (MXC_V_RTC_CTRL_FT_CLKDIV8 << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_CLKDIV8 Setting */ 191 192 #define MXC_F_RTC_CTRL_X32KMD_POS 11 /**< CTRL_X32KMD Position */ 193 #define MXC_F_RTC_CTRL_X32KMD ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_X32KMD_POS)) /**< CTRL_X32KMD Mask */ 194 #define MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE ((uint32_t)0x0UL) /**< CTRL_X32KMD_NOISEIMMUNEMODE Value */ 195 #define MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE (MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_NOISEIMMUNEMODE Setting */ 196 #define MXC_V_RTC_CTRL_X32KMD_QUIETMODE ((uint32_t)0x1UL) /**< CTRL_X32KMD_QUIETMODE Value */ 197 #define MXC_S_RTC_CTRL_X32KMD_QUIETMODE (MXC_V_RTC_CTRL_X32KMD_QUIETMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETMODE Setting */ 198 #define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP ((uint32_t)0x2UL) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Value */ 199 #define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Setting */ 200 #define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP ((uint32_t)0x3UL) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Value */ 201 #define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Setting */ 202 203 #define MXC_F_RTC_CTRL_WE_POS 15 /**< CTRL_WE Position */ 204 #define MXC_F_RTC_CTRL_WE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WE_POS)) /**< CTRL_WE Mask */ 205 206 /**@} end of group RTC_CTRL_Register */ 207 208 /** 209 * @ingroup rtc_registers 210 * @defgroup RTC_TRIM RTC_TRIM 211 * @brief RTC Trim Register. 212 * @{ 213 */ 214 #define MXC_F_RTC_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */ 215 #define MXC_F_RTC_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */ 216 217 #define MXC_F_RTC_TRIM_VBATTMR_POS 8 /**< TRIM_VBATTMR Position */ 218 #define MXC_F_RTC_TRIM_VBATTMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VBATTMR_POS)) /**< TRIM_VBATTMR Mask */ 219 220 /**@} end of group RTC_TRIM_Register */ 221 222 /** 223 * @ingroup rtc_registers 224 * @defgroup RTC_OSCCTRL RTC_OSCCTRL 225 * @brief RTC Oscillator Control Register. 226 * @{ 227 */ 228 #define MXC_F_RTC_OSCCTRL_FLITER_EN_POS 0 /**< OSCCTRL_FLITER_EN Position */ 229 #define MXC_F_RTC_OSCCTRL_FLITER_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_FLITER_EN_POS)) /**< OSCCTRL_FLITER_EN Mask */ 230 231 #define MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS 1 /**< OSCCTRL_IBIAS_SEL Position */ 232 #define MXC_F_RTC_OSCCTRL_IBIAS_SEL ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS)) /**< OSCCTRL_IBIAS_SEL Mask */ 233 234 #define MXC_F_RTC_OSCCTRL_HYST_EN_POS 2 /**< OSCCTRL_HYST_EN Position */ 235 #define MXC_F_RTC_OSCCTRL_HYST_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_HYST_EN_POS)) /**< OSCCTRL_HYST_EN Mask */ 236 237 #define MXC_F_RTC_OSCCTRL_IBIAS_EN_POS 3 /**< OSCCTRL_IBIAS_EN Position */ 238 #define MXC_F_RTC_OSCCTRL_IBIAS_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_EN_POS)) /**< OSCCTRL_IBIAS_EN Mask */ 239 240 #define MXC_F_RTC_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */ 241 #define MXC_F_RTC_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */ 242 243 #define MXC_F_RTC_OSCCTRL_OUT32K_POS 5 /**< OSCCTRL_OUT32K Position */ 244 #define MXC_F_RTC_OSCCTRL_OUT32K ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_OUT32K_POS)) /**< OSCCTRL_OUT32K Mask */ 245 246 /**@} end of group RTC_OSCCTRL_Register */ 247 248 #ifdef __cplusplus 249 } 250 #endif 251 252 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_RTC_REGS_H_ 253
