1 /** 2 * @file max32660.h 3 * @brief Device-specific perhiperal header file 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_MAX32660_H_ 27 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_MAX32660_H_ 28 29 #ifndef TARGET_NUM 30 #define TARGET_NUM 32660 31 #endif 32 33 #include <stdint.h> 34 35 #ifndef FALSE 36 #define FALSE (0) 37 #endif 38 39 #ifndef TRUE 40 #define TRUE (1) 41 #endif 42 43 #if !defined(__GNUC__) 44 #define CMSIS_VECTAB_VIRTUAL 45 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "nvic_table.h" 46 #endif /* !__GNUC__ */ 47 48 /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ 49 #if defined(__GNUC__) /* GCC */ 50 #ifndef __weak 51 #define __weak __attribute__((weak)) 52 #endif 53 54 #elif defined(__CC_ARM) /* Keil */ 55 56 #define inline __inline 57 #pragma anon_unions 58 59 #endif 60 61 typedef enum { 62 NonMaskableInt_IRQn = -14, 63 HardFault_IRQn = -13, 64 MemoryManagement_IRQn = -12, 65 BusFault_IRQn = -11, 66 UsageFault_IRQn = -10, 67 SVCall_IRQn = -5, 68 DebugMonitor_IRQn = -4, 69 PendSV_IRQn = -2, 70 SysTick_IRQn = -1, 71 72 /* Device-specific interrupt sources (external to ARM core) */ 73 /* table entry number */ 74 /* |||| */ 75 /* |||| table offset address */ 76 /* vvvv vvvvvv */ 77 78 PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */ 79 WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */ 80 RSV00_IRQn, /* 0x12 0x0048 18: RSV00 */ 81 RTC_IRQn, /* 0x13 0x004C 19: RTC */ 82 RSV1_IRQn, /* 0x14 0x0050 20: RSV1 */ 83 TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */ 84 TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */ 85 TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */ 86 RSV02_IRQn, /* 0x18 0x0060 24: RSV02 */ 87 RSV03_IRQn, /* 0x19 0x0064 25: RSV03 */ 88 RSV04_IRQn, /* 0x1A 0x0068 26: RSV04 */ 89 RSV05_IRQn, /* 0x1B 0x006C 27: RSV05 */ 90 RSV06_IRQn, /* 0x1C 0x0070 28: RSV06 */ 91 I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */ 92 UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */ 93 UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */ 94 SPI0_IRQn, /* 0x20 0x0080 32: SPI17Y */ 95 SPIMSS_IRQn, /* 0x21 0x0084 33: SPIMSS */ 96 RSV07_IRQn, /* 0x22 0x0088 34: RSV07 */ 97 RSV08_IRQn, /* 0x23 0x008C 35: RSV08 */ 98 RSV09_IRQn, /* 0x24 0x0090 36: RSV09 */ 99 RSV10_IRQn, /* 0x25 0x0094 37: RSV10 */ 100 RSV11_IRQn, /* 0x26 0x0098 38: RSV11 */ 101 FLC_IRQn, /* 0x27 0x009C 39: FLC */ 102 GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */ 103 RSV12_IRQn, /* 0x29 0x00A4 41: RSV12 */ 104 RSV13_IRQn, /* 0x2A 0x00A8 42: RSV13 */ 105 RSV14_IRQn, /* 0x2B 0x00AC 43: RSV14 */ 106 DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */ 107 DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */ 108 DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */ 109 DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */ 110 RSV15_IRQn, /* 0x30 0x00C0 48: RSV15 */ 111 RSV16_IRQn, /* 0x31 0x00C4 49: RSV16 */ 112 RSV17_IRQn, /* 0x32 0x00C8 50: RSV17 */ 113 RSV18_IRQn, /* 0x33 0x00CC 51: RSV18 */ 114 I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */ 115 RSV19_IRQn, /* 0x35 0x00D4 53: RSV19 */ 116 RSV20_IRQn, /* 0x36 0x00D8 54: RSV20 */ 117 RSV21_IRQn, /* 0x37 0x00DC 55: RSV21 */ 118 RSV22_IRQn, /* 0x38 0x00E0 56: RSV22 */ 119 RSV23_IRQn, /* 0x39 0x00E4 57: RSV23 */ 120 RSV24_IRQn, /* 0x3A 0x00E8 58: RSV24 */ 121 RSV25_IRQn, /* 0x3B 0x00EC 59: RSV25 */ 122 RSV26_IRQn, /* 0x3C 0x00F0 60: RSV26 */ 123 RSV27_IRQn, /* 0x3D 0x00F4 61: RSV27 */ 124 RSV28_IRQn, /* 0x3E 0x00F8 62: RSV28 */ 125 RSV29_IRQn, /* 0x3F 0x00FC 63: RSV29 */ 126 RSV30_IRQn, /* 0x40 0x0100 64: RSV30 */ 127 RSV31_IRQn, /* 0x41 0x0104 65: RSV31 */ 128 RSV32_IRQn, /* 0x42 0x0108 66: RSV32 */ 129 RSV33_IRQn, /* 0x43 0x010C 67: RSV33 */ 130 RSV34_IRQn, /* 0x44 0x0110 68: RSV34 */ 131 RSV35_IRQn, /* 0x45 0x0114 69: RSV35 */ 132 GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */ 133 MXC_IRQ_EXT_COUNT, 134 } IRQn_Type; 135 136 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) 137 138 /* ================================================================================ */ 139 /* ================ Processor and Core Peripheral Section ================ */ 140 /* ================================================================================ */ 141 142 /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */ 143 #define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ 144 #define __MPU_PRESENT 1 /*!< MPU present or not */ 145 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 146 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 147 #define __FPU_PRESENT 1 /*!< FPU present or not */ 148 149 #include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */ 150 #include "system_max32660.h" /*!< System Header */ 151 152 /* ================================================================================ */ 153 /* ================== Device Specific Memory Section ================== */ 154 /* ================================================================================ */ 155 156 #define MXC_FLASH_MEM_BASE 0x00000000UL 157 #define MXC_FLASH_PAGE_SIZE 0x00002000UL 158 #define MXC_FLASH_MEM_SIZE 0x00040000UL 159 #define MXC_INFO_MEM_BASE 0x00040000UL 160 #define MXC_INFO_MEM_SIZE 0x00001000UL 161 #define MXC_SRAM_MEM_BASE 0x20000000UL 162 #define MXC_SRAM_MEM_SIZE 0x00018000UL 163 164 /* ================================================================================ */ 165 /* ================ Device Specific Peripheral Section ================ */ 166 /* ================================================================================ */ 167 168 /* 169 Base addresses and configuration settings for all MAX32660 peripheral modules. 170 */ 171 172 /******************************************************************************/ 173 /* Global control */ 174 #define MXC_BASE_GCR ((uint32_t)0x40000000UL) 175 #define MXC_GCR ((mxc_gcr_regs_t *)MXC_BASE_GCR) 176 177 /******************************************************************************/ 178 /* Non-battery backed SI Registers */ 179 #define MXC_BASE_SIR ((uint32_t)0x40000400UL) 180 #define MXC_SIR ((mxc_sir_regs_t *)MXC_BASE_SIR) 181 182 /******************************************************************************/ 183 /* Watchdog */ 184 #define MXC_BASE_WDT0 ((uint32_t)0x40003000UL) 185 #define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0) 186 187 /******************************************************************************/ 188 /* Real Time Clock */ 189 #define MXC_BASE_RTC ((uint32_t)0x40006000UL) 190 #define MXC_RTC ((mxc_rtc_regs_t *)MXC_BASE_RTC) 191 192 /******************************************************************************/ 193 /* Power Sequencer */ 194 #define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL) 195 #define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ) 196 197 /******************************************************************************/ 198 /* GPIO */ 199 #define MXC_CFG_GPIO_INSTANCES (1) 200 #define MXC_CFG_GPIO_PINS_PORT (14) 201 202 #define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL) 203 #define MXC_GPIO0 ((mxc_gpio_regs_t *)MXC_BASE_GPIO0) 204 205 #define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : -1) 206 207 #define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : 0) 208 209 #define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : 0) 210 211 /******************************************************************************/ 212 /* Timer */ 213 #define SEC(s) (((uint32_t)s) * 1000000UL) 214 #define MSEC(ms) (ms * 1000UL) 215 #define USEC(us) (us) 216 217 #define MXC_CFG_TMR_INSTANCES (3) 218 219 #define MXC_BASE_TMR0 ((uint32_t)0x40010000UL) 220 #define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0) 221 #define MXC_BASE_TMR1 ((uint32_t)0x40011000UL) 222 #define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1) 223 #define MXC_BASE_TMR2 ((uint32_t)0x40012000UL) 224 #define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2) 225 226 #define MXC_TMR_GET_IRQ(i) \ 227 (IRQn_Type)((i) == 0 ? TMR0_IRQn : (i) == 1 ? TMR1_IRQn : (i) == 2 ? TMR2_IRQn : 0) 228 229 #define MXC_TMR_GET_BASE(i) \ 230 ((i) == 0 ? MXC_BASE_TMR0 : (i) == 1 ? MXC_BASE_TMR1 : (i) == 2 ? MXC_BASE_TMR2 : 0) 231 232 #define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : (i) == 1 ? MXC_TMR1 : (i) == 2 ? MXC_TMR2 : 0) 233 234 #define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : (p) == MXC_TMR1 ? 1 : (p) == MXC_TMR2 ? 2 : -1) 235 236 /******************************************************************************/ 237 /* SPIMSS */ 238 #define MXC_SPIMSS_INSTANCES (1) 239 #define MXC_SPIMSS_FIFO_DEPTH (8) 240 241 #define MXC_BASE_SPIMSS ((uint32_t)0x40019000UL) 242 #define MXC_SPIMSS ((mxc_spimss_regs_t *)MXC_BASE_SPIMSS) 243 244 #define MXC_SPIMSS_GET_IDX(p) ((p) == MXC_SPIMSS ? 0 : -1) 245 #define MXC_SPIMSS_GET_SPI(i) ((i) == 0 ? MXC_SPIMSS : 0) 246 247 /******************************************************************************/ 248 /* I2C */ 249 #define MXC_I2C_INSTANCES (2) 250 #define MXC_I2C_FIFO_DEPTH (8) 251 #define MXC_I2C_NUM_TARGET_ADDR (4) 252 253 #define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL) 254 #define MXC_I2C0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0) 255 #define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL) 256 #define MXC_I2C1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1) 257 258 #define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : 0) 259 260 #define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : 0) 261 262 #define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : (i) == 1 ? MXC_I2C1 : 0) 263 264 #define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : (p) == MXC_I2C1 ? 1 : -1) 265 266 /******************************************************************************/ 267 /* DMA */ 268 #define MXC_DMA_CHANNELS (4) 269 #define MXC_DMA_INSTANCES (1) 270 271 #define MXC_BASE_DMA ((uint32_t)0x40028000UL) 272 #define MXC_DMA ((mxc_dma_regs_t *)MXC_BASE_DMA) 273 274 #define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1) 275 276 #define MXC_DMA_CH_GET_IRQ(i) \ 277 ((IRQn_Type)(((i) == 0) ? DMA0_IRQn : \ 278 ((i) == 1) ? DMA1_IRQn : \ 279 ((i) == 2) ? DMA2_IRQn : \ 280 ((i) == 3) ? DMA3_IRQn : \ 281 0)) 282 283 /******************************************************************************/ 284 /* FLC */ 285 #define MXC_FLC_INSTANCES (1) 286 287 #define MXC_BASE_FLC ((uint32_t)0x40029000UL) 288 #define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC) 289 #define MXC_FLC0 MXC_FLC 290 291 #define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC : 0) 292 293 /******************************************************************************/ 294 /* Instruction Cache */ 295 #define MXC_BASE_ICC ((uint32_t)0x4002A000UL) 296 #define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC) 297 298 /******************************************************************************/ 299 /* UART / Serial Port Interface */ 300 #define MXC_UART_INSTANCES (2) 301 #define MXC_UART_FIFO_DEPTH (8) 302 303 #define MXC_BASE_UART0 ((uint32_t)0x40042000UL) 304 #define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0) 305 #define MXC_BASE_UART1 ((uint32_t)0x40043000UL) 306 #define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1) 307 308 #define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : (i) == 1 ? UART1_IRQn : 0) 309 310 #define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : (i) == 1 ? MXC_BASE_UART1 : 0) 311 312 #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : 0) 313 314 #define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : (p) == MXC_UART1 ? 1 : -1) 315 316 /******************************************************************************/ 317 /* SPI */ 318 #define MXC_SPI_INSTANCES (1) 319 #define MXC_SPI_SS_INSTANCES (1) 320 #define MXC_SPI_FIFO_DEPTH (32) 321 322 #define MXC_BASE_SPI ((uint32_t)0x40046000UL) 323 #define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI) 324 325 #define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : -1) 326 327 #define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI : 0) 328 329 #define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : 0) 330 331 /******************************************************************************/ 332 /* Bit Shifting */ 333 #define MXC_F_BIT_0 (1 << 0) 334 #define MXC_F_BIT_1 (1 << 1) 335 #define MXC_F_BIT_2 (1 << 2) 336 #define MXC_F_BIT_3 (1 << 3) 337 #define MXC_F_BIT_4 (1 << 4) 338 #define MXC_F_BIT_5 (1 << 5) 339 #define MXC_F_BIT_6 (1 << 6) 340 #define MXC_F_BIT_7 (1 << 7) 341 #define MXC_F_BIT_8 (1 << 8) 342 #define MXC_F_BIT_9 (1 << 9) 343 #define MXC_F_BIT_10 (1 << 10) 344 #define MXC_F_BIT_11 (1 << 11) 345 #define MXC_F_BIT_12 (1 << 12) 346 #define MXC_F_BIT_13 (1 << 13) 347 #define MXC_F_BIT_14 (1 << 14) 348 #define MXC_F_BIT_15 (1 << 15) 349 #define MXC_F_BIT_16 (1 << 16) 350 #define MXC_F_BIT_17 (1 << 17) 351 #define MXC_F_BIT_18 (1 << 18) 352 #define MXC_F_BIT_19 (1 << 19) 353 #define MXC_F_BIT_20 (1 << 20) 354 #define MXC_F_BIT_21 (1 << 21) 355 #define MXC_F_BIT_22 (1 << 22) 356 #define MXC_F_BIT_23 (1 << 23) 357 #define MXC_F_BIT_24 (1 << 24) 358 #define MXC_F_BIT_25 (1 << 25) 359 #define MXC_F_BIT_26 (1 << 26) 360 #define MXC_F_BIT_27 (1 << 27) 361 #define MXC_F_BIT_28 (1 << 28) 362 #define MXC_F_BIT_29 (1 << 29) 363 #define MXC_F_BIT_30 (1 << 30) 364 #define MXC_F_BIT_31 (1 << 31) 365 366 /******************************************************************************/ 367 /* Bit Banding */ 368 #define BITBAND(reg, bit) \ 369 ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \ 370 ((bit) << 2)) 371 372 #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) 373 #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) 374 #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) 375 376 #define MXC_SETFIELD(reg, mask, value) ((reg) = ((reg) & ~(mask)) | ((value) & (mask))) 377 378 /******************************************************************************/ 379 /* SCB CPACR */ 380 381 /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */ 382 #define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ 383 #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ 384 #define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ 385 #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ 386 387 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_MAX32660_H_ 388
