1 /** 2 * @file trimsir_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the TRIMSIR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup trimsir_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_TRIMSIR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_TRIMSIR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup trimsir 67 * @defgroup trimsir_registers TRIMSIR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the TRIMSIR Peripheral Module. 69 * @details Trim System Initilazation Registers 70 */ 71 72 /** 73 * @ingroup trimsir_registers 74 * Structure type to access the TRIMSIR Registers. 75 */ 76 typedef struct { 77 __R uint32_t rsv_0x0_0x7[2]; 78 __IO uint32_t rtc; /**< <tt>\b 0x08:</tt> TRIMSIR RTC Register */ 79 __R uint32_t rsv_0xc_0x33[10]; 80 __I uint32_t simo; /**< <tt>\b 0x34:</tt> TRIMSIR SIMO Register */ 81 __R uint32_t rsv_0x38; 82 __I uint32_t ipolo; /**< <tt>\b 0x3C:</tt> TRIMSIR IPOLO Register */ 83 __IO uint32_t ctrl; /**< <tt>\b 0x40:</tt> TRIMSIR CTRL Register */ 84 __IO uint32_t inro; /**< <tt>\b 0x44:</tt> TRIMSIR INRO Register */ 85 } mxc_trimsir_regs_t; 86 87 /* Register offsets for module TRIMSIR */ 88 /** 89 * @ingroup trimsir_registers 90 * @defgroup TRIMSIR_Register_Offsets Register Offsets 91 * @brief TRIMSIR Peripheral Register Offsets from the TRIMSIR Base Peripheral Address. 92 * @{ 93 */ 94 #define MXC_R_TRIMSIR_RTC ((uint32_t)0x00000008UL) /**< Offset from TRIMSIR Base Address: <tt> 0x0008</tt> */ 95 #define MXC_R_TRIMSIR_SIMO ((uint32_t)0x00000034UL) /**< Offset from TRIMSIR Base Address: <tt> 0x0034</tt> */ 96 #define MXC_R_TRIMSIR_IPOLO ((uint32_t)0x0000003CUL) /**< Offset from TRIMSIR Base Address: <tt> 0x003C</tt> */ 97 #define MXC_R_TRIMSIR_CTRL ((uint32_t)0x00000040UL) /**< Offset from TRIMSIR Base Address: <tt> 0x0040</tt> */ 98 #define MXC_R_TRIMSIR_INRO ((uint32_t)0x00000044UL) /**< Offset from TRIMSIR Base Address: <tt> 0x0044</tt> */ 99 /**@} end of group trimsir_registers */ 100 101 /** 102 * @ingroup trimsir_registers 103 * @defgroup TRIMSIR_RTC TRIMSIR_RTC 104 * @brief RTC Trim System Initialization Register. 105 * @{ 106 */ 107 #define MXC_F_TRIMSIR_RTC_X1TRIM_POS 16 /**< RTC_X1TRIM Position */ 108 #define MXC_F_TRIMSIR_RTC_X1TRIM ((uint32_t)(0x1FUL << MXC_F_TRIMSIR_RTC_X1TRIM_POS)) /**< RTC_X1TRIM Mask */ 109 110 #define MXC_F_TRIMSIR_RTC_X2TRIM_POS 21 /**< RTC_X2TRIM Position */ 111 #define MXC_F_TRIMSIR_RTC_X2TRIM ((uint32_t)(0x1FUL << MXC_F_TRIMSIR_RTC_X2TRIM_POS)) /**< RTC_X2TRIM Mask */ 112 113 #define MXC_F_TRIMSIR_RTC_LOCK_POS 31 /**< RTC_LOCK Position */ 114 #define MXC_F_TRIMSIR_RTC_LOCK ((uint32_t)(0x1UL << MXC_F_TRIMSIR_RTC_LOCK_POS)) /**< RTC_LOCK Mask */ 115 116 /**@} end of group TRIMSIR_RTC_Register */ 117 118 /** 119 * @ingroup trimsir_registers 120 * @defgroup TRIMSIR_SIMO TRIMSIR_SIMO 121 * @brief SIMO Trim System Initialization Register. 122 * @{ 123 */ 124 #define MXC_F_TRIMSIR_SIMO_CLKDIV_POS 0 /**< SIMO_CLKDIV Position */ 125 #define MXC_F_TRIMSIR_SIMO_CLKDIV ((uint32_t)(0x7UL << MXC_F_TRIMSIR_SIMO_CLKDIV_POS)) /**< SIMO_CLKDIV Mask */ 126 #define MXC_V_TRIMSIR_SIMO_CLKDIV_DIV1 ((uint32_t)0x0UL) /**< SIMO_CLKDIV_DIV1 Value */ 127 #define MXC_S_TRIMSIR_SIMO_CLKDIV_DIV1 (MXC_V_TRIMSIR_SIMO_CLKDIV_DIV1 << MXC_F_TRIMSIR_SIMO_CLKDIV_POS) /**< SIMO_CLKDIV_DIV1 Setting */ 128 #define MXC_V_TRIMSIR_SIMO_CLKDIV_DIV16 ((uint32_t)0x1UL) /**< SIMO_CLKDIV_DIV16 Value */ 129 #define MXC_S_TRIMSIR_SIMO_CLKDIV_DIV16 (MXC_V_TRIMSIR_SIMO_CLKDIV_DIV16 << MXC_F_TRIMSIR_SIMO_CLKDIV_POS) /**< SIMO_CLKDIV_DIV16 Setting */ 130 #define MXC_V_TRIMSIR_SIMO_CLKDIV_DIV32 ((uint32_t)0x3UL) /**< SIMO_CLKDIV_DIV32 Value */ 131 #define MXC_S_TRIMSIR_SIMO_CLKDIV_DIV32 (MXC_V_TRIMSIR_SIMO_CLKDIV_DIV32 << MXC_F_TRIMSIR_SIMO_CLKDIV_POS) /**< SIMO_CLKDIV_DIV32 Setting */ 132 #define MXC_V_TRIMSIR_SIMO_CLKDIV_DIV64 ((uint32_t)0x5UL) /**< SIMO_CLKDIV_DIV64 Value */ 133 #define MXC_S_TRIMSIR_SIMO_CLKDIV_DIV64 (MXC_V_TRIMSIR_SIMO_CLKDIV_DIV64 << MXC_F_TRIMSIR_SIMO_CLKDIV_POS) /**< SIMO_CLKDIV_DIV64 Setting */ 134 #define MXC_V_TRIMSIR_SIMO_CLKDIV_DIV128 ((uint32_t)0x7UL) /**< SIMO_CLKDIV_DIV128 Value */ 135 #define MXC_S_TRIMSIR_SIMO_CLKDIV_DIV128 (MXC_V_TRIMSIR_SIMO_CLKDIV_DIV128 << MXC_F_TRIMSIR_SIMO_CLKDIV_POS) /**< SIMO_CLKDIV_DIV128 Setting */ 136 137 /**@} end of group TRIMSIR_SIMO_Register */ 138 139 /** 140 * @ingroup trimsir_registers 141 * @defgroup TRIMSIR_IPOLO TRIMSIR_IPOLO 142 * @brief IPO Low Trim System Initialization Register. 143 * @{ 144 */ 145 #define MXC_F_TRIMSIR_IPOLO_IPO_LIMITLO_POS 0 /**< IPOLO_IPO_LIMITLO Position */ 146 #define MXC_F_TRIMSIR_IPOLO_IPO_LIMITLO ((uint32_t)(0xFFUL << MXC_F_TRIMSIR_IPOLO_IPO_LIMITLO_POS)) /**< IPOLO_IPO_LIMITLO Mask */ 147 148 /**@} end of group TRIMSIR_IPOLO_Register */ 149 150 /** 151 * @ingroup trimsir_registers 152 * @defgroup TRIMSIR_CTRL TRIMSIR_CTRL 153 * @brief Control Trim System Initialization Register. 154 * @{ 155 */ 156 #define MXC_F_TRIMSIR_CTRL_VDDA_LIMITLO_POS 0 /**< CTRL_VDDA_LIMITLO Position */ 157 #define MXC_F_TRIMSIR_CTRL_VDDA_LIMITLO ((uint32_t)(0x7FUL << MXC_F_TRIMSIR_CTRL_VDDA_LIMITLO_POS)) /**< CTRL_VDDA_LIMITLO Mask */ 158 159 #define MXC_F_TRIMSIR_CTRL_VDDA_LIMITHI_POS 8 /**< CTRL_VDDA_LIMITHI Position */ 160 #define MXC_F_TRIMSIR_CTRL_VDDA_LIMITHI ((uint32_t)(0x7FUL << MXC_F_TRIMSIR_CTRL_VDDA_LIMITHI_POS)) /**< CTRL_VDDA_LIMITHI Mask */ 161 162 #define MXC_F_TRIMSIR_CTRL_IPO_LIMITHI_POS 15 /**< CTRL_IPO_LIMITHI Position */ 163 #define MXC_F_TRIMSIR_CTRL_IPO_LIMITHI ((uint32_t)(0x1FFUL << MXC_F_TRIMSIR_CTRL_IPO_LIMITHI_POS)) /**< CTRL_IPO_LIMITHI Mask */ 164 165 #define MXC_F_TRIMSIR_CTRL_INRO_SEL_POS 24 /**< CTRL_INRO_SEL Position */ 166 #define MXC_F_TRIMSIR_CTRL_INRO_SEL ((uint32_t)(0x3UL << MXC_F_TRIMSIR_CTRL_INRO_SEL_POS)) /**< CTRL_INRO_SEL Mask */ 167 #define MXC_V_TRIMSIR_CTRL_INRO_SEL_8KHZ ((uint32_t)0x0UL) /**< CTRL_INRO_SEL_8KHZ Value */ 168 #define MXC_S_TRIMSIR_CTRL_INRO_SEL_8KHZ (MXC_V_TRIMSIR_CTRL_INRO_SEL_8KHZ << MXC_F_TRIMSIR_CTRL_INRO_SEL_POS) /**< CTRL_INRO_SEL_8KHZ Setting */ 169 #define MXC_V_TRIMSIR_CTRL_INRO_SEL_16KHZ ((uint32_t)0x1UL) /**< CTRL_INRO_SEL_16KHZ Value */ 170 #define MXC_S_TRIMSIR_CTRL_INRO_SEL_16KHZ (MXC_V_TRIMSIR_CTRL_INRO_SEL_16KHZ << MXC_F_TRIMSIR_CTRL_INRO_SEL_POS) /**< CTRL_INRO_SEL_16KHZ Setting */ 171 #define MXC_V_TRIMSIR_CTRL_INRO_SEL_30KHZ ((uint32_t)0x2UL) /**< CTRL_INRO_SEL_30KHZ Value */ 172 #define MXC_S_TRIMSIR_CTRL_INRO_SEL_30KHZ (MXC_V_TRIMSIR_CTRL_INRO_SEL_30KHZ << MXC_F_TRIMSIR_CTRL_INRO_SEL_POS) /**< CTRL_INRO_SEL_30KHZ Setting */ 173 174 #define MXC_F_TRIMSIR_CTRL_INRO_TRIM_POS 29 /**< CTRL_INRO_TRIM Position */ 175 #define MXC_F_TRIMSIR_CTRL_INRO_TRIM ((uint32_t)(0x7UL << MXC_F_TRIMSIR_CTRL_INRO_TRIM_POS)) /**< CTRL_INRO_TRIM Mask */ 176 177 /**@} end of group TRIMSIR_CTRL_Register */ 178 179 /** 180 * @ingroup trimsir_registers 181 * @defgroup TRIMSIR_INRO TRIMSIR_INRO 182 * @brief RTC Trim System Initialization Register. 183 * @{ 184 */ 185 #define MXC_F_TRIMSIR_INRO_TRIM16K_POS 0 /**< INRO_TRIM16K Position */ 186 #define MXC_F_TRIMSIR_INRO_TRIM16K ((uint32_t)(0x7UL << MXC_F_TRIMSIR_INRO_TRIM16K_POS)) /**< INRO_TRIM16K Mask */ 187 188 #define MXC_F_TRIMSIR_INRO_TRIM30K_POS 3 /**< INRO_TRIM30K Position */ 189 #define MXC_F_TRIMSIR_INRO_TRIM30K ((uint32_t)(0x7UL << MXC_F_TRIMSIR_INRO_TRIM30K_POS)) /**< INRO_TRIM30K Mask */ 190 191 #define MXC_F_TRIMSIR_INRO_LPCLKSEL_POS 6 /**< INRO_LPCLKSEL Position */ 192 #define MXC_F_TRIMSIR_INRO_LPCLKSEL ((uint32_t)(0x3UL << MXC_F_TRIMSIR_INRO_LPCLKSEL_POS)) /**< INRO_LPCLKSEL Mask */ 193 #define MXC_V_TRIMSIR_INRO_LPCLKSEL_8KHZ ((uint32_t)0x0UL) /**< INRO_LPCLKSEL_8KHZ Value */ 194 #define MXC_S_TRIMSIR_INRO_LPCLKSEL_8KHZ (MXC_V_TRIMSIR_INRO_LPCLKSEL_8KHZ << MXC_F_TRIMSIR_INRO_LPCLKSEL_POS) /**< INRO_LPCLKSEL_8KHZ Setting */ 195 #define MXC_V_TRIMSIR_INRO_LPCLKSEL_16KHZ ((uint32_t)0x1UL) /**< INRO_LPCLKSEL_16KHZ Value */ 196 #define MXC_S_TRIMSIR_INRO_LPCLKSEL_16KHZ (MXC_V_TRIMSIR_INRO_LPCLKSEL_16KHZ << MXC_F_TRIMSIR_INRO_LPCLKSEL_POS) /**< INRO_LPCLKSEL_16KHZ Setting */ 197 #define MXC_V_TRIMSIR_INRO_LPCLKSEL_30KHZ ((uint32_t)0x2UL) /**< INRO_LPCLKSEL_30KHZ Value */ 198 #define MXC_S_TRIMSIR_INRO_LPCLKSEL_30KHZ (MXC_V_TRIMSIR_INRO_LPCLKSEL_30KHZ << MXC_F_TRIMSIR_INRO_LPCLKSEL_POS) /**< INRO_LPCLKSEL_30KHZ Setting */ 199 200 /**@} end of group TRIMSIR_INRO_Register */ 201 202 #ifdef __cplusplus 203 } 204 #endif 205 206 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_TRIMSIR_REGS_H_ 207
