1 /** 2 * @file spi_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup spi_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_SPI_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_SPI_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup spi 67 * @defgroup spi_registers SPI_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. 69 * @details SPI peripheral. 70 */ 71 72 /** 73 * @ingroup spi_registers 74 * Structure type to access the SPI Registers. 75 */ 76 typedef struct { 77 union { 78 __IO uint32_t fifo32; /**< <tt>\b 0x00:</tt> SPI FIFO32 Register */ 79 __IO uint16_t fifo16[2]; /**< <tt>\b 0x00:</tt> SPI FIFO16 Register */ 80 __IO uint8_t fifo8[4]; /**< <tt>\b 0x00:</tt> SPI FIFO8 Register */ 81 }; 82 __IO uint32_t ctrl0; /**< <tt>\b 0x04:</tt> SPI CTRL0 Register */ 83 __IO uint32_t ctrl1; /**< <tt>\b 0x08:</tt> SPI CTRL1 Register */ 84 __IO uint32_t ctrl2; /**< <tt>\b 0x0C:</tt> SPI CTRL2 Register */ 85 __IO uint32_t sstime; /**< <tt>\b 0x10:</tt> SPI SSTIME Register */ 86 __IO uint32_t clkctrl; /**< <tt>\b 0x14:</tt> SPI CLKCTRL Register */ 87 __R uint32_t rsv_0x18; 88 __IO uint32_t dma; /**< <tt>\b 0x1C:</tt> SPI DMA Register */ 89 __IO uint32_t intfl; /**< <tt>\b 0x20:</tt> SPI INTFL Register */ 90 __IO uint32_t inten; /**< <tt>\b 0x24:</tt> SPI INTEN Register */ 91 __IO uint32_t wkfl; /**< <tt>\b 0x28:</tt> SPI WKFL Register */ 92 __IO uint32_t wken; /**< <tt>\b 0x2C:</tt> SPI WKEN Register */ 93 __I uint32_t stat; /**< <tt>\b 0x30:</tt> SPI STAT Register */ 94 } mxc_spi_regs_t; 95 96 /* Register offsets for module SPI */ 97 /** 98 * @ingroup spi_registers 99 * @defgroup SPI_Register_Offsets Register Offsets 100 * @brief SPI Peripheral Register Offsets from the SPI Base Peripheral Address. 101 * @{ 102 */ 103 #define MXC_R_SPI_FIFO32 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */ 104 #define MXC_R_SPI_FIFO16 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */ 105 #define MXC_R_SPI_FIFO8 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */ 106 #define MXC_R_SPI_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI Base Address: <tt> 0x0004</tt> */ 107 #define MXC_R_SPI_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI Base Address: <tt> 0x0008</tt> */ 108 #define MXC_R_SPI_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI Base Address: <tt> 0x000C</tt> */ 109 #define MXC_R_SPI_SSTIME ((uint32_t)0x00000010UL) /**< Offset from SPI Base Address: <tt> 0x0010</tt> */ 110 #define MXC_R_SPI_CLKCTRL ((uint32_t)0x00000014UL) /**< Offset from SPI Base Address: <tt> 0x0014</tt> */ 111 #define MXC_R_SPI_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI Base Address: <tt> 0x001C</tt> */ 112 #define MXC_R_SPI_INTFL ((uint32_t)0x00000020UL) /**< Offset from SPI Base Address: <tt> 0x0020</tt> */ 113 #define MXC_R_SPI_INTEN ((uint32_t)0x00000024UL) /**< Offset from SPI Base Address: <tt> 0x0024</tt> */ 114 #define MXC_R_SPI_WKFL ((uint32_t)0x00000028UL) /**< Offset from SPI Base Address: <tt> 0x0028</tt> */ 115 #define MXC_R_SPI_WKEN ((uint32_t)0x0000002CUL) /**< Offset from SPI Base Address: <tt> 0x002C</tt> */ 116 #define MXC_R_SPI_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI Base Address: <tt> 0x0030</tt> */ 117 /**@} end of group spi_registers */ 118 119 /** 120 * @ingroup spi_registers 121 * @defgroup SPI_FIFO32 SPI_FIFO32 122 * @brief Register for reading and writing the FIFO. 123 * @{ 124 */ 125 #define MXC_F_SPI_FIFO32_DATA_POS 0 /**< FIFO32_DATA Position */ 126 #define MXC_F_SPI_FIFO32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI_FIFO32_DATA_POS)) /**< FIFO32_DATA Mask */ 127 128 /**@} end of group SPI_FIFO32_Register */ 129 130 /** 131 * @ingroup spi_registers 132 * @defgroup SPI_FIFO16 SPI_FIFO16 133 * @brief Register for reading and writing the FIFO. 134 * @{ 135 */ 136 #define MXC_F_SPI_FIFO16_DATA_POS 0 /**< FIFO16_DATA Position */ 137 #define MXC_F_SPI_FIFO16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPI_FIFO16_DATA_POS)) /**< FIFO16_DATA Mask */ 138 139 /**@} end of group SPI_FIFO16_Register */ 140 141 /** 142 * @ingroup spi_registers 143 * @defgroup SPI_FIFO8 SPI_FIFO8 144 * @brief Register for reading and writing the FIFO. 145 * @{ 146 */ 147 #define MXC_F_SPI_FIFO8_DATA_POS 0 /**< FIFO8_DATA Position */ 148 #define MXC_F_SPI_FIFO8_DATA ((uint8_t)(0xFFUL << MXC_F_SPI_FIFO8_DATA_POS)) /**< FIFO8_DATA Mask */ 149 150 /**@} end of group SPI_FIFO8_Register */ 151 152 /** 153 * @ingroup spi_registers 154 * @defgroup SPI_CTRL0 SPI_CTRL0 155 * @brief Register for controlling SPI peripheral. 156 * @{ 157 */ 158 #define MXC_F_SPI_CTRL0_EN_POS 0 /**< CTRL0_EN Position */ 159 #define MXC_F_SPI_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_EN_POS)) /**< CTRL0_EN Mask */ 160 161 #define MXC_F_SPI_CTRL0_MST_MODE_POS 1 /**< CTRL0_MST_MODE Position */ 162 #define MXC_F_SPI_CTRL0_MST_MODE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MST_MODE_POS)) /**< CTRL0_MST_MODE Mask */ 163 164 #define MXC_F_SPI_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */ 165 #define MXC_F_SPI_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */ 166 167 #define MXC_F_SPI_CTRL0_START_POS 5 /**< CTRL0_START Position */ 168 #define MXC_F_SPI_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS)) /**< CTRL0_START Mask */ 169 170 #define MXC_F_SPI_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */ 171 #define MXC_F_SPI_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */ 172 173 #define MXC_F_SPI_CTRL0_SS_ACTIVE_POS 16 /**< CTRL0_SS_ACTIVE Position */ 174 #define MXC_F_SPI_CTRL0_SS_ACTIVE ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_SS_ACTIVE_POS)) /**< CTRL0_SS_ACTIVE Mask */ 175 #define MXC_V_SPI_CTRL0_SS_ACTIVE_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_ACTIVE_SS0 Value */ 176 #define MXC_S_SPI_CTRL0_SS_ACTIVE_SS0 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS0 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS0 Setting */ 177 #define MXC_V_SPI_CTRL0_SS_ACTIVE_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_ACTIVE_SS1 Value */ 178 #define MXC_S_SPI_CTRL0_SS_ACTIVE_SS1 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS1 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS1 Setting */ 179 #define MXC_V_SPI_CTRL0_SS_ACTIVE_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_ACTIVE_SS2 Value */ 180 #define MXC_S_SPI_CTRL0_SS_ACTIVE_SS2 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS2 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS2 Setting */ 181 #define MXC_V_SPI_CTRL0_SS_ACTIVE_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_ACTIVE_SS3 Value */ 182 #define MXC_S_SPI_CTRL0_SS_ACTIVE_SS3 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS3 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS3 Setting */ 183 184 /**@} end of group SPI_CTRL0_Register */ 185 186 /** 187 * @ingroup spi_registers 188 * @defgroup SPI_CTRL1 SPI_CTRL1 189 * @brief Register for controlling SPI peripheral. 190 * @{ 191 */ 192 #define MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */ 193 #define MXC_F_SPI_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */ 194 195 #define MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */ 196 #define MXC_F_SPI_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */ 197 198 /**@} end of group SPI_CTRL1_Register */ 199 200 /** 201 * @ingroup spi_registers 202 * @defgroup SPI_CTRL2 SPI_CTRL2 203 * @brief Register for controlling SPI peripheral. 204 * @{ 205 */ 206 #define MXC_F_SPI_CTRL2_CLKPHA_POS 0 /**< CTRL2_CLKPHA Position */ 207 #define MXC_F_SPI_CTRL2_CLKPHA ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLKPHA_POS)) /**< CTRL2_CLKPHA Mask */ 208 209 #define MXC_F_SPI_CTRL2_CLKPOL_POS 1 /**< CTRL2_CLKPOL Position */ 210 #define MXC_F_SPI_CTRL2_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLKPOL_POS)) /**< CTRL2_CLKPOL Mask */ 211 212 #define MXC_F_SPI_CTRL2_NUMBITS_POS 8 /**< CTRL2_NUMBITS Position */ 213 #define MXC_F_SPI_CTRL2_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUMBITS_POS)) /**< CTRL2_NUMBITS Mask */ 214 #define MXC_V_SPI_CTRL2_NUMBITS_16 ((uint32_t)0x0UL) /**< CTRL2_NUMBITS_16 Value */ 215 #define MXC_S_SPI_CTRL2_NUMBITS_16 (MXC_V_SPI_CTRL2_NUMBITS_16 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_16 Setting */ 216 #define MXC_V_SPI_CTRL2_NUMBITS_1 ((uint32_t)0x1UL) /**< CTRL2_NUMBITS_1 Value */ 217 #define MXC_S_SPI_CTRL2_NUMBITS_1 (MXC_V_SPI_CTRL2_NUMBITS_1 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_1 Setting */ 218 #define MXC_V_SPI_CTRL2_NUMBITS_2 ((uint32_t)0x2UL) /**< CTRL2_NUMBITS_2 Value */ 219 #define MXC_S_SPI_CTRL2_NUMBITS_2 (MXC_V_SPI_CTRL2_NUMBITS_2 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_2 Setting */ 220 #define MXC_V_SPI_CTRL2_NUMBITS_3 ((uint32_t)0x3UL) /**< CTRL2_NUMBITS_3 Value */ 221 #define MXC_S_SPI_CTRL2_NUMBITS_3 (MXC_V_SPI_CTRL2_NUMBITS_3 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_3 Setting */ 222 #define MXC_V_SPI_CTRL2_NUMBITS_4 ((uint32_t)0x4UL) /**< CTRL2_NUMBITS_4 Value */ 223 #define MXC_S_SPI_CTRL2_NUMBITS_4 (MXC_V_SPI_CTRL2_NUMBITS_4 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_4 Setting */ 224 #define MXC_V_SPI_CTRL2_NUMBITS_5 ((uint32_t)0x5UL) /**< CTRL2_NUMBITS_5 Value */ 225 #define MXC_S_SPI_CTRL2_NUMBITS_5 (MXC_V_SPI_CTRL2_NUMBITS_5 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_5 Setting */ 226 #define MXC_V_SPI_CTRL2_NUMBITS_6 ((uint32_t)0x6UL) /**< CTRL2_NUMBITS_6 Value */ 227 #define MXC_S_SPI_CTRL2_NUMBITS_6 (MXC_V_SPI_CTRL2_NUMBITS_6 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_6 Setting */ 228 #define MXC_V_SPI_CTRL2_NUMBITS_7 ((uint32_t)0x7UL) /**< CTRL2_NUMBITS_7 Value */ 229 #define MXC_S_SPI_CTRL2_NUMBITS_7 (MXC_V_SPI_CTRL2_NUMBITS_7 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_7 Setting */ 230 #define MXC_V_SPI_CTRL2_NUMBITS_8 ((uint32_t)0x8UL) /**< CTRL2_NUMBITS_8 Value */ 231 #define MXC_S_SPI_CTRL2_NUMBITS_8 (MXC_V_SPI_CTRL2_NUMBITS_8 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_8 Setting */ 232 #define MXC_V_SPI_CTRL2_NUMBITS_9 ((uint32_t)0x9UL) /**< CTRL2_NUMBITS_9 Value */ 233 #define MXC_S_SPI_CTRL2_NUMBITS_9 (MXC_V_SPI_CTRL2_NUMBITS_9 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_9 Setting */ 234 #define MXC_V_SPI_CTRL2_NUMBITS_10 ((uint32_t)0xAUL) /**< CTRL2_NUMBITS_10 Value */ 235 #define MXC_S_SPI_CTRL2_NUMBITS_10 (MXC_V_SPI_CTRL2_NUMBITS_10 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_10 Setting */ 236 #define MXC_V_SPI_CTRL2_NUMBITS_11 ((uint32_t)0xBUL) /**< CTRL2_NUMBITS_11 Value */ 237 #define MXC_S_SPI_CTRL2_NUMBITS_11 (MXC_V_SPI_CTRL2_NUMBITS_11 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_11 Setting */ 238 #define MXC_V_SPI_CTRL2_NUMBITS_12 ((uint32_t)0xCUL) /**< CTRL2_NUMBITS_12 Value */ 239 #define MXC_S_SPI_CTRL2_NUMBITS_12 (MXC_V_SPI_CTRL2_NUMBITS_12 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_12 Setting */ 240 #define MXC_V_SPI_CTRL2_NUMBITS_13 ((uint32_t)0xDUL) /**< CTRL2_NUMBITS_13 Value */ 241 #define MXC_S_SPI_CTRL2_NUMBITS_13 (MXC_V_SPI_CTRL2_NUMBITS_13 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_13 Setting */ 242 #define MXC_V_SPI_CTRL2_NUMBITS_14 ((uint32_t)0xEUL) /**< CTRL2_NUMBITS_14 Value */ 243 #define MXC_S_SPI_CTRL2_NUMBITS_14 (MXC_V_SPI_CTRL2_NUMBITS_14 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_14 Setting */ 244 #define MXC_V_SPI_CTRL2_NUMBITS_15 ((uint32_t)0xFUL) /**< CTRL2_NUMBITS_15 Value */ 245 #define MXC_S_SPI_CTRL2_NUMBITS_15 (MXC_V_SPI_CTRL2_NUMBITS_15 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_15 Setting */ 246 247 #define MXC_F_SPI_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */ 248 #define MXC_F_SPI_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */ 249 #define MXC_V_SPI_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */ 250 #define MXC_S_SPI_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */ 251 #define MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */ 252 #define MXC_S_SPI_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */ 253 #define MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */ 254 #define MXC_S_SPI_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */ 255 256 #define MXC_F_SPI_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */ 257 #define MXC_F_SPI_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */ 258 259 #define MXC_F_SPI_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */ 260 #define MXC_F_SPI_CTRL2_SS_POL ((uint32_t)(0xFFUL << MXC_F_SPI_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */ 261 #define MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SS_POL_SS0_HIGH Value */ 262 #define MXC_S_SPI_CTRL2_SS_POL_SS0_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS0_HIGH Setting */ 263 #define MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SS_POL_SS1_HIGH Value */ 264 #define MXC_S_SPI_CTRL2_SS_POL_SS1_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS1_HIGH Setting */ 265 #define MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SS_POL_SS2_HIGH Value */ 266 #define MXC_S_SPI_CTRL2_SS_POL_SS2_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS2_HIGH Setting */ 267 #define MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SS_POL_SS3_HIGH Value */ 268 #define MXC_S_SPI_CTRL2_SS_POL_SS3_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS3_HIGH Setting */ 269 270 /**@} end of group SPI_CTRL2_Register */ 271 272 /** 273 * @ingroup spi_registers 274 * @defgroup SPI_SSTIME SPI_SSTIME 275 * @brief Register for controlling SPI peripheral/Slave Select Timing. 276 * @{ 277 */ 278 #define MXC_F_SPI_SSTIME_PRE_POS 0 /**< SSTIME_PRE Position */ 279 #define MXC_F_SPI_SSTIME_PRE ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_PRE_POS)) /**< SSTIME_PRE Mask */ 280 #define MXC_V_SPI_SSTIME_PRE_256 ((uint32_t)0x0UL) /**< SSTIME_PRE_256 Value */ 281 #define MXC_S_SPI_SSTIME_PRE_256 (MXC_V_SPI_SSTIME_PRE_256 << MXC_F_SPI_SSTIME_PRE_POS) /**< SSTIME_PRE_256 Setting */ 282 283 #define MXC_F_SPI_SSTIME_POST_POS 8 /**< SSTIME_POST Position */ 284 #define MXC_F_SPI_SSTIME_POST ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_POST_POS)) /**< SSTIME_POST Mask */ 285 #define MXC_V_SPI_SSTIME_POST_256 ((uint32_t)0x0UL) /**< SSTIME_POST_256 Value */ 286 #define MXC_S_SPI_SSTIME_POST_256 (MXC_V_SPI_SSTIME_POST_256 << MXC_F_SPI_SSTIME_POST_POS) /**< SSTIME_POST_256 Setting */ 287 288 #define MXC_F_SPI_SSTIME_INACT_POS 16 /**< SSTIME_INACT Position */ 289 #define MXC_F_SPI_SSTIME_INACT ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_INACT_POS)) /**< SSTIME_INACT Mask */ 290 #define MXC_V_SPI_SSTIME_INACT_256 ((uint32_t)0x0UL) /**< SSTIME_INACT_256 Value */ 291 #define MXC_S_SPI_SSTIME_INACT_256 (MXC_V_SPI_SSTIME_INACT_256 << MXC_F_SPI_SSTIME_INACT_POS) /**< SSTIME_INACT_256 Setting */ 292 293 /**@} end of group SPI_SSTIME_Register */ 294 295 /** 296 * @ingroup spi_registers 297 * @defgroup SPI_CLKCTRL SPI_CLKCTRL 298 * @brief Register for controlling SPI clock rate. 299 * @{ 300 */ 301 #define MXC_F_SPI_CLKCTRL_LO_POS 0 /**< CLKCTRL_LO Position */ 302 #define MXC_F_SPI_CLKCTRL_LO ((uint32_t)(0xFFUL << MXC_F_SPI_CLKCTRL_LO_POS)) /**< CLKCTRL_LO Mask */ 303 #define MXC_V_SPI_CLKCTRL_LO_DIS ((uint32_t)0x0UL) /**< CLKCTRL_LO_DIS Value */ 304 #define MXC_S_SPI_CLKCTRL_LO_DIS (MXC_V_SPI_CLKCTRL_LO_DIS << MXC_F_SPI_CLKCTRL_LO_POS) /**< CLKCTRL_LO_DIS Setting */ 305 306 #define MXC_F_SPI_CLKCTRL_HI_POS 8 /**< CLKCTRL_HI Position */ 307 #define MXC_F_SPI_CLKCTRL_HI ((uint32_t)(0xFFUL << MXC_F_SPI_CLKCTRL_HI_POS)) /**< CLKCTRL_HI Mask */ 308 #define MXC_V_SPI_CLKCTRL_HI_DIS ((uint32_t)0x0UL) /**< CLKCTRL_HI_DIS Value */ 309 #define MXC_S_SPI_CLKCTRL_HI_DIS (MXC_V_SPI_CLKCTRL_HI_DIS << MXC_F_SPI_CLKCTRL_HI_POS) /**< CLKCTRL_HI_DIS Setting */ 310 311 #define MXC_F_SPI_CLKCTRL_CLKDIV_POS 16 /**< CLKCTRL_CLKDIV Position */ 312 #define MXC_F_SPI_CLKCTRL_CLKDIV ((uint32_t)(0xFUL << MXC_F_SPI_CLKCTRL_CLKDIV_POS)) /**< CLKCTRL_CLKDIV Mask */ 313 314 /**@} end of group SPI_CLKCTRL_Register */ 315 316 /** 317 * @ingroup spi_registers 318 * @defgroup SPI_DMA SPI_DMA 319 * @brief Register for controlling DMA. 320 * @{ 321 */ 322 #define MXC_F_SPI_DMA_TX_THD_VAL_POS 0 /**< DMA_TX_THD_VAL Position */ 323 #define MXC_F_SPI_DMA_TX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */ 324 325 #define MXC_F_SPI_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */ 326 #define MXC_F_SPI_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */ 327 328 #define MXC_F_SPI_DMA_TX_FLUSH_POS 7 /**< DMA_TX_FLUSH Position */ 329 #define MXC_F_SPI_DMA_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FLUSH_POS)) /**< DMA_TX_FLUSH Mask */ 330 331 #define MXC_F_SPI_DMA_TX_LVL_POS 8 /**< DMA_TX_LVL Position */ 332 #define MXC_F_SPI_DMA_TX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_LVL_POS)) /**< DMA_TX_LVL Mask */ 333 334 #define MXC_F_SPI_DMA_DMA_TX_EN_POS 15 /**< DMA_DMA_TX_EN Position */ 335 #define MXC_F_SPI_DMA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_DMA_TX_EN_POS)) /**< DMA_DMA_TX_EN Mask */ 336 337 #define MXC_F_SPI_DMA_RX_THD_VAL_POS 16 /**< DMA_RX_THD_VAL Position */ 338 #define MXC_F_SPI_DMA_RX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */ 339 340 #define MXC_F_SPI_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */ 341 #define MXC_F_SPI_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */ 342 343 #define MXC_F_SPI_DMA_RX_FLUSH_POS 23 /**< DMA_RX_FLUSH Position */ 344 #define MXC_F_SPI_DMA_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FLUSH_POS)) /**< DMA_RX_FLUSH Mask */ 345 346 #define MXC_F_SPI_DMA_RX_LVL_POS 24 /**< DMA_RX_LVL Position */ 347 #define MXC_F_SPI_DMA_RX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_LVL_POS)) /**< DMA_RX_LVL Mask */ 348 349 #define MXC_F_SPI_DMA_DMA_RX_EN_POS 31 /**< DMA_DMA_RX_EN Position */ 350 #define MXC_F_SPI_DMA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_DMA_RX_EN_POS)) /**< DMA_DMA_RX_EN Mask */ 351 352 /**@} end of group SPI_DMA_Register */ 353 354 /** 355 * @ingroup spi_registers 356 * @defgroup SPI_INTFL SPI_INTFL 357 * @brief Register for reading and clearing interrupt flags. All bits are write 1 to 358 * clear. 359 * @{ 360 */ 361 #define MXC_F_SPI_INTFL_TX_THD_POS 0 /**< INTFL_TX_THD Position */ 362 #define MXC_F_SPI_INTFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_THD_POS)) /**< INTFL_TX_THD Mask */ 363 364 #define MXC_F_SPI_INTFL_TX_EM_POS 1 /**< INTFL_TX_EM Position */ 365 #define MXC_F_SPI_INTFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_EM_POS)) /**< INTFL_TX_EM Mask */ 366 367 #define MXC_F_SPI_INTFL_RX_THD_POS 2 /**< INTFL_RX_THD Position */ 368 #define MXC_F_SPI_INTFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_THD_POS)) /**< INTFL_RX_THD Mask */ 369 370 #define MXC_F_SPI_INTFL_RX_FULL_POS 3 /**< INTFL_RX_FULL Position */ 371 #define MXC_F_SPI_INTFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_FULL_POS)) /**< INTFL_RX_FULL Mask */ 372 373 #define MXC_F_SPI_INTFL_SSA_POS 4 /**< INTFL_SSA Position */ 374 #define MXC_F_SPI_INTFL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSA_POS)) /**< INTFL_SSA Mask */ 375 376 #define MXC_F_SPI_INTFL_SSD_POS 5 /**< INTFL_SSD Position */ 377 #define MXC_F_SPI_INTFL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSD_POS)) /**< INTFL_SSD Mask */ 378 379 #define MXC_F_SPI_INTFL_FAULT_POS 8 /**< INTFL_FAULT Position */ 380 #define MXC_F_SPI_INTFL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_FAULT_POS)) /**< INTFL_FAULT Mask */ 381 382 #define MXC_F_SPI_INTFL_ABORT_POS 9 /**< INTFL_ABORT Position */ 383 #define MXC_F_SPI_INTFL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_ABORT_POS)) /**< INTFL_ABORT Mask */ 384 385 #define MXC_F_SPI_INTFL_MST_DONE_POS 11 /**< INTFL_MST_DONE Position */ 386 #define MXC_F_SPI_INTFL_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_MST_DONE_POS)) /**< INTFL_MST_DONE Mask */ 387 388 #define MXC_F_SPI_INTFL_TX_OV_POS 12 /**< INTFL_TX_OV Position */ 389 #define MXC_F_SPI_INTFL_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_OV_POS)) /**< INTFL_TX_OV Mask */ 390 391 #define MXC_F_SPI_INTFL_TX_UN_POS 13 /**< INTFL_TX_UN Position */ 392 #define MXC_F_SPI_INTFL_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_UN_POS)) /**< INTFL_TX_UN Mask */ 393 394 #define MXC_F_SPI_INTFL_RX_OV_POS 14 /**< INTFL_RX_OV Position */ 395 #define MXC_F_SPI_INTFL_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_OV_POS)) /**< INTFL_RX_OV Mask */ 396 397 #define MXC_F_SPI_INTFL_RX_UN_POS 15 /**< INTFL_RX_UN Position */ 398 #define MXC_F_SPI_INTFL_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_UN_POS)) /**< INTFL_RX_UN Mask */ 399 400 /**@} end of group SPI_INTFL_Register */ 401 402 /** 403 * @ingroup spi_registers 404 * @defgroup SPI_INTEN SPI_INTEN 405 * @brief Register for enabling interrupts. 406 * @{ 407 */ 408 #define MXC_F_SPI_INTEN_TX_THD_POS 0 /**< INTEN_TX_THD Position */ 409 #define MXC_F_SPI_INTEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_THD_POS)) /**< INTEN_TX_THD Mask */ 410 411 #define MXC_F_SPI_INTEN_TX_EM_POS 1 /**< INTEN_TX_EM Position */ 412 #define MXC_F_SPI_INTEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_EM_POS)) /**< INTEN_TX_EM Mask */ 413 414 #define MXC_F_SPI_INTEN_RX_THD_POS 2 /**< INTEN_RX_THD Position */ 415 #define MXC_F_SPI_INTEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_THD_POS)) /**< INTEN_RX_THD Mask */ 416 417 #define MXC_F_SPI_INTEN_RX_FULL_POS 3 /**< INTEN_RX_FULL Position */ 418 #define MXC_F_SPI_INTEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_FULL_POS)) /**< INTEN_RX_FULL Mask */ 419 420 #define MXC_F_SPI_INTEN_SSA_POS 4 /**< INTEN_SSA Position */ 421 #define MXC_F_SPI_INTEN_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSA_POS)) /**< INTEN_SSA Mask */ 422 423 #define MXC_F_SPI_INTEN_SSD_POS 5 /**< INTEN_SSD Position */ 424 #define MXC_F_SPI_INTEN_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSD_POS)) /**< INTEN_SSD Mask */ 425 426 #define MXC_F_SPI_INTEN_FAULT_POS 8 /**< INTEN_FAULT Position */ 427 #define MXC_F_SPI_INTEN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_FAULT_POS)) /**< INTEN_FAULT Mask */ 428 429 #define MXC_F_SPI_INTEN_ABORT_POS 9 /**< INTEN_ABORT Position */ 430 #define MXC_F_SPI_INTEN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_ABORT_POS)) /**< INTEN_ABORT Mask */ 431 432 #define MXC_F_SPI_INTEN_MST_DONE_POS 11 /**< INTEN_MST_DONE Position */ 433 #define MXC_F_SPI_INTEN_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_MST_DONE_POS)) /**< INTEN_MST_DONE Mask */ 434 435 #define MXC_F_SPI_INTEN_TX_OV_POS 12 /**< INTEN_TX_OV Position */ 436 #define MXC_F_SPI_INTEN_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_OV_POS)) /**< INTEN_TX_OV Mask */ 437 438 #define MXC_F_SPI_INTEN_TX_UN_POS 13 /**< INTEN_TX_UN Position */ 439 #define MXC_F_SPI_INTEN_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_UN_POS)) /**< INTEN_TX_UN Mask */ 440 441 #define MXC_F_SPI_INTEN_RX_OV_POS 14 /**< INTEN_RX_OV Position */ 442 #define MXC_F_SPI_INTEN_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_OV_POS)) /**< INTEN_RX_OV Mask */ 443 444 #define MXC_F_SPI_INTEN_RX_UN_POS 15 /**< INTEN_RX_UN Position */ 445 #define MXC_F_SPI_INTEN_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_UN_POS)) /**< INTEN_RX_UN Mask */ 446 447 /**@} end of group SPI_INTEN_Register */ 448 449 /** 450 * @ingroup spi_registers 451 * @defgroup SPI_WKFL SPI_WKFL 452 * @brief Register for wake up flags. All bits in this register are write 1 to clear. 453 * @{ 454 */ 455 #define MXC_F_SPI_WKFL_TX_THD_POS 0 /**< WKFL_TX_THD Position */ 456 #define MXC_F_SPI_WKFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_TX_THD_POS)) /**< WKFL_TX_THD Mask */ 457 458 #define MXC_F_SPI_WKFL_TX_EM_POS 1 /**< WKFL_TX_EM Position */ 459 #define MXC_F_SPI_WKFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_TX_EM_POS)) /**< WKFL_TX_EM Mask */ 460 461 #define MXC_F_SPI_WKFL_RX_THD_POS 2 /**< WKFL_RX_THD Position */ 462 #define MXC_F_SPI_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */ 463 464 #define MXC_F_SPI_WKFL_RX_FULL_POS 3 /**< WKFL_RX_FULL Position */ 465 #define MXC_F_SPI_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */ 466 467 /**@} end of group SPI_WKFL_Register */ 468 469 /** 470 * @ingroup spi_registers 471 * @defgroup SPI_WKEN SPI_WKEN 472 * @brief Register for wake up enable. 473 * @{ 474 */ 475 #define MXC_F_SPI_WKEN_TX_THD_POS 0 /**< WKEN_TX_THD Position */ 476 #define MXC_F_SPI_WKEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_TX_THD_POS)) /**< WKEN_TX_THD Mask */ 477 478 #define MXC_F_SPI_WKEN_TX_EM_POS 1 /**< WKEN_TX_EM Position */ 479 #define MXC_F_SPI_WKEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_TX_EM_POS)) /**< WKEN_TX_EM Mask */ 480 481 #define MXC_F_SPI_WKEN_RX_THD_POS 2 /**< WKEN_RX_THD Position */ 482 #define MXC_F_SPI_WKEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */ 483 484 #define MXC_F_SPI_WKEN_RX_FULL_POS 3 /**< WKEN_RX_FULL Position */ 485 #define MXC_F_SPI_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */ 486 487 /**@} end of group SPI_WKEN_Register */ 488 489 /** 490 * @ingroup spi_registers 491 * @defgroup SPI_STAT SPI_STAT 492 * @brief SPI Status register. 493 * @{ 494 */ 495 #define MXC_F_SPI_STAT_BUSY_POS 0 /**< STAT_BUSY Position */ 496 #define MXC_F_SPI_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_STAT_BUSY_POS)) /**< STAT_BUSY Mask */ 497 498 /**@} end of group SPI_STAT_Register */ 499 500 #ifdef __cplusplus 501 } 502 #endif 503 504 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_SPI_REGS_H_ 505
