1 /** 2 * @file simo_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SIMO Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup simo_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_SIMO_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_SIMO_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup simo 67 * @defgroup simo_registers SIMO_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SIMO Peripheral Module. 69 * @details Single Inductor Multiple Output Switching Converter 70 */ 71 72 /** 73 * @ingroup simo_registers 74 * Structure type to access the SIMO Registers. 75 */ 76 typedef struct { 77 __R uint32_t rsv_0x0; 78 __IO uint32_t vrego_a; /**< <tt>\b 0x0004:</tt> SIMO VREGO_A Register */ 79 __IO uint32_t vrego_b; /**< <tt>\b 0x0008:</tt> SIMO VREGO_B Register */ 80 __IO uint32_t vrego_c; /**< <tt>\b 0x000C:</tt> SIMO VREGO_C Register */ 81 __IO uint32_t vrego_d; /**< <tt>\b 0x0010:</tt> SIMO VREGO_D Register */ 82 __IO uint32_t ipka; /**< <tt>\b 0x0014:</tt> SIMO IPKA Register */ 83 __IO uint32_t ipkb; /**< <tt>\b 0x0018:</tt> SIMO IPKB Register */ 84 __IO uint32_t maxton; /**< <tt>\b 0x001C:</tt> SIMO MAXTON Register */ 85 __I uint32_t iload_a; /**< <tt>\b 0x0020:</tt> SIMO ILOAD_A Register */ 86 __I uint32_t iload_b; /**< <tt>\b 0x0024:</tt> SIMO ILOAD_B Register */ 87 __I uint32_t iload_c; /**< <tt>\b 0x0028:</tt> SIMO ILOAD_C Register */ 88 __I uint32_t iload_d; /**< <tt>\b 0x002C:</tt> SIMO ILOAD_D Register */ 89 __IO uint32_t buck_alert_thr_a; /**< <tt>\b 0x0030:</tt> SIMO BUCK_ALERT_THR_A Register */ 90 __IO uint32_t buck_alert_thr_b; /**< <tt>\b 0x0034:</tt> SIMO BUCK_ALERT_THR_B Register */ 91 __IO uint32_t buck_alert_thr_c; /**< <tt>\b 0x0038:</tt> SIMO BUCK_ALERT_THR_C Register */ 92 __IO uint32_t buck_alert_thr_d; /**< <tt>\b 0x003C:</tt> SIMO BUCK_ALERT_THR_D Register */ 93 __I uint32_t buck_out_ready; /**< <tt>\b 0x0040:</tt> SIMO BUCK_OUT_READY Register */ 94 __I uint32_t zero_cross_cal_a; /**< <tt>\b 0x0044:</tt> SIMO ZERO_CROSS_CAL_A Register */ 95 __I uint32_t zero_cross_cal_b; /**< <tt>\b 0x0048:</tt> SIMO ZERO_CROSS_CAL_B Register */ 96 __I uint32_t zero_cross_cal_c; /**< <tt>\b 0x004C:</tt> SIMO ZERO_CROSS_CAL_C Register */ 97 __I uint32_t zero_cross_cal_d; /**< <tt>\b 0x0050:</tt> SIMO ZERO_CROSS_CAL_D Register */ 98 } mxc_simo_regs_t; 99 100 /* Register offsets for module SIMO */ 101 /** 102 * @ingroup simo_registers 103 * @defgroup SIMO_Register_Offsets Register Offsets 104 * @brief SIMO Peripheral Register Offsets from the SIMO Base Peripheral Address. 105 * @{ 106 */ 107 #define MXC_R_SIMO_VREGO_A ((uint32_t)0x00000004UL) /**< Offset from SIMO Base Address: <tt> 0x0004</tt> */ 108 #define MXC_R_SIMO_VREGO_B ((uint32_t)0x00000008UL) /**< Offset from SIMO Base Address: <tt> 0x0008</tt> */ 109 #define MXC_R_SIMO_VREGO_C ((uint32_t)0x0000000CUL) /**< Offset from SIMO Base Address: <tt> 0x000C</tt> */ 110 #define MXC_R_SIMO_VREGO_D ((uint32_t)0x00000010UL) /**< Offset from SIMO Base Address: <tt> 0x0010</tt> */ 111 #define MXC_R_SIMO_IPKA ((uint32_t)0x00000014UL) /**< Offset from SIMO Base Address: <tt> 0x0014</tt> */ 112 #define MXC_R_SIMO_IPKB ((uint32_t)0x00000018UL) /**< Offset from SIMO Base Address: <tt> 0x0018</tt> */ 113 #define MXC_R_SIMO_MAXTON ((uint32_t)0x0000001CUL) /**< Offset from SIMO Base Address: <tt> 0x001C</tt> */ 114 #define MXC_R_SIMO_ILOAD_A ((uint32_t)0x00000020UL) /**< Offset from SIMO Base Address: <tt> 0x0020</tt> */ 115 #define MXC_R_SIMO_ILOAD_B ((uint32_t)0x00000024UL) /**< Offset from SIMO Base Address: <tt> 0x0024</tt> */ 116 #define MXC_R_SIMO_ILOAD_C ((uint32_t)0x00000028UL) /**< Offset from SIMO Base Address: <tt> 0x0028</tt> */ 117 #define MXC_R_SIMO_ILOAD_D ((uint32_t)0x0000002CUL) /**< Offset from SIMO Base Address: <tt> 0x002C</tt> */ 118 #define MXC_R_SIMO_BUCK_ALERT_THR_A ((uint32_t)0x00000030UL) /**< Offset from SIMO Base Address: <tt> 0x0030</tt> */ 119 #define MXC_R_SIMO_BUCK_ALERT_THR_B ((uint32_t)0x00000034UL) /**< Offset from SIMO Base Address: <tt> 0x0034</tt> */ 120 #define MXC_R_SIMO_BUCK_ALERT_THR_C ((uint32_t)0x00000038UL) /**< Offset from SIMO Base Address: <tt> 0x0038</tt> */ 121 #define MXC_R_SIMO_BUCK_ALERT_THR_D ((uint32_t)0x0000003CUL) /**< Offset from SIMO Base Address: <tt> 0x003C</tt> */ 122 #define MXC_R_SIMO_BUCK_OUT_READY ((uint32_t)0x00000040UL) /**< Offset from SIMO Base Address: <tt> 0x0040</tt> */ 123 #define MXC_R_SIMO_ZERO_CROSS_CAL_A ((uint32_t)0x00000044UL) /**< Offset from SIMO Base Address: <tt> 0x0044</tt> */ 124 #define MXC_R_SIMO_ZERO_CROSS_CAL_B ((uint32_t)0x00000048UL) /**< Offset from SIMO Base Address: <tt> 0x0048</tt> */ 125 #define MXC_R_SIMO_ZERO_CROSS_CAL_C ((uint32_t)0x0000004CUL) /**< Offset from SIMO Base Address: <tt> 0x004C</tt> */ 126 #define MXC_R_SIMO_ZERO_CROSS_CAL_D ((uint32_t)0x00000050UL) /**< Offset from SIMO Base Address: <tt> 0x0050</tt> */ 127 /**@} end of group simo_registers */ 128 129 /** 130 * @ingroup simo_registers 131 * @defgroup SIMO_VREGO_A SIMO_VREGO_A 132 * @brief Buck Voltage Regulator A Control Register 133 * @{ 134 */ 135 #define MXC_F_SIMO_VREGO_A_VSETA_POS 0 /**< VREGO_A_VSETA Position */ 136 #define MXC_F_SIMO_VREGO_A_VSETA ((uint32_t)(0x7FUL << MXC_F_SIMO_VREGO_A_VSETA_POS)) /**< VREGO_A_VSETA Mask */ 137 138 #define MXC_F_SIMO_VREGO_A_RANGEA_POS 7 /**< VREGO_A_RANGEA Position */ 139 #define MXC_F_SIMO_VREGO_A_RANGEA ((uint32_t)(0x1UL << MXC_F_SIMO_VREGO_A_RANGEA_POS)) /**< VREGO_A_RANGEA Mask */ 140 141 /**@} end of group SIMO_VREGO_A_Register */ 142 143 /** 144 * @ingroup simo_registers 145 * @defgroup SIMO_VREGO_B SIMO_VREGO_B 146 * @brief Buck Voltage Regulator B Control Register 147 * @{ 148 */ 149 #define MXC_F_SIMO_VREGO_B_VSETB_POS 0 /**< VREGO_B_VSETB Position */ 150 #define MXC_F_SIMO_VREGO_B_VSETB ((uint32_t)(0x7FUL << MXC_F_SIMO_VREGO_B_VSETB_POS)) /**< VREGO_B_VSETB Mask */ 151 152 #define MXC_F_SIMO_VREGO_B_RANGEB_POS 7 /**< VREGO_B_RANGEB Position */ 153 #define MXC_F_SIMO_VREGO_B_RANGEB ((uint32_t)(0x1UL << MXC_F_SIMO_VREGO_B_RANGEB_POS)) /**< VREGO_B_RANGEB Mask */ 154 155 /**@} end of group SIMO_VREGO_B_Register */ 156 157 /** 158 * @ingroup simo_registers 159 * @defgroup SIMO_VREGO_C SIMO_VREGO_C 160 * @brief Buck Voltage Regulator C Control Register 161 * @{ 162 */ 163 #define MXC_F_SIMO_VREGO_C_VSETC_POS 0 /**< VREGO_C_VSETC Position */ 164 #define MXC_F_SIMO_VREGO_C_VSETC ((uint32_t)(0x7FUL << MXC_F_SIMO_VREGO_C_VSETC_POS)) /**< VREGO_C_VSETC Mask */ 165 166 #define MXC_F_SIMO_VREGO_C_RANGEC_POS 7 /**< VREGO_C_RANGEC Position */ 167 #define MXC_F_SIMO_VREGO_C_RANGEC ((uint32_t)(0x1UL << MXC_F_SIMO_VREGO_C_RANGEC_POS)) /**< VREGO_C_RANGEC Mask */ 168 169 /**@} end of group SIMO_VREGO_C_Register */ 170 171 /** 172 * @ingroup simo_registers 173 * @defgroup SIMO_VREGO_D SIMO_VREGO_D 174 * @brief Buck Voltage Regulator D Control Register 175 * @{ 176 */ 177 #define MXC_F_SIMO_VREGO_D_VSETD_POS 0 /**< VREGO_D_VSETD Position */ 178 #define MXC_F_SIMO_VREGO_D_VSETD ((uint32_t)(0x7FUL << MXC_F_SIMO_VREGO_D_VSETD_POS)) /**< VREGO_D_VSETD Mask */ 179 180 #define MXC_F_SIMO_VREGO_D_RANGED_POS 7 /**< VREGO_D_RANGED Position */ 181 #define MXC_F_SIMO_VREGO_D_RANGED ((uint32_t)(0x1UL << MXC_F_SIMO_VREGO_D_RANGED_POS)) /**< VREGO_D_RANGED Mask */ 182 183 /**@} end of group SIMO_VREGO_D_Register */ 184 185 /** 186 * @ingroup simo_registers 187 * @defgroup SIMO_IPKA SIMO_IPKA 188 * @brief High Side FET Peak Current VREGO_A/VREGO_B Register 189 * @{ 190 */ 191 #define MXC_F_SIMO_IPKA_IPKSETA_POS 0 /**< IPKA_IPKSETA Position */ 192 #define MXC_F_SIMO_IPKA_IPKSETA ((uint32_t)(0xFUL << MXC_F_SIMO_IPKA_IPKSETA_POS)) /**< IPKA_IPKSETA Mask */ 193 194 #define MXC_F_SIMO_IPKA_IPKSETB_POS 4 /**< IPKA_IPKSETB Position */ 195 #define MXC_F_SIMO_IPKA_IPKSETB ((uint32_t)(0xFUL << MXC_F_SIMO_IPKA_IPKSETB_POS)) /**< IPKA_IPKSETB Mask */ 196 197 /**@} end of group SIMO_IPKA_Register */ 198 199 /** 200 * @ingroup simo_registers 201 * @defgroup SIMO_IPKB SIMO_IPKB 202 * @brief High Side FET Peak Current VREGO_C/VREGO_D Register 203 * @{ 204 */ 205 #define MXC_F_SIMO_IPKB_IPKSETC_POS 0 /**< IPKB_IPKSETC Position */ 206 #define MXC_F_SIMO_IPKB_IPKSETC ((uint32_t)(0xFUL << MXC_F_SIMO_IPKB_IPKSETC_POS)) /**< IPKB_IPKSETC Mask */ 207 208 #define MXC_F_SIMO_IPKB_IPKSETD_POS 4 /**< IPKB_IPKSETD Position */ 209 #define MXC_F_SIMO_IPKB_IPKSETD ((uint32_t)(0xFUL << MXC_F_SIMO_IPKB_IPKSETD_POS)) /**< IPKB_IPKSETD Mask */ 210 211 /**@} end of group SIMO_IPKB_Register */ 212 213 /** 214 * @ingroup simo_registers 215 * @defgroup SIMO_MAXTON SIMO_MAXTON 216 * @brief Maximum High Side FET Time On Register 217 * @{ 218 */ 219 #define MXC_F_SIMO_MAXTON_TONSET_POS 0 /**< MAXTON_TONSET Position */ 220 #define MXC_F_SIMO_MAXTON_TONSET ((uint32_t)(0xFUL << MXC_F_SIMO_MAXTON_TONSET_POS)) /**< MAXTON_TONSET Mask */ 221 222 /**@} end of group SIMO_MAXTON_Register */ 223 224 /** 225 * @ingroup simo_registers 226 * @defgroup SIMO_ILOAD_A SIMO_ILOAD_A 227 * @brief Buck Cycle Count VREGO_A Register 228 * @{ 229 */ 230 #define MXC_F_SIMO_ILOAD_A_ILOADA_POS 0 /**< ILOAD_A_ILOADA Position */ 231 #define MXC_F_SIMO_ILOAD_A_ILOADA ((uint32_t)(0xFFUL << MXC_F_SIMO_ILOAD_A_ILOADA_POS)) /**< ILOAD_A_ILOADA Mask */ 232 233 /**@} end of group SIMO_ILOAD_A_Register */ 234 235 /** 236 * @ingroup simo_registers 237 * @defgroup SIMO_ILOAD_B SIMO_ILOAD_B 238 * @brief Buck Cycle Count VREGO_B Register 239 * @{ 240 */ 241 #define MXC_F_SIMO_ILOAD_B_ILOADB_POS 0 /**< ILOAD_B_ILOADB Position */ 242 #define MXC_F_SIMO_ILOAD_B_ILOADB ((uint32_t)(0xFFUL << MXC_F_SIMO_ILOAD_B_ILOADB_POS)) /**< ILOAD_B_ILOADB Mask */ 243 244 /**@} end of group SIMO_ILOAD_B_Register */ 245 246 /** 247 * @ingroup simo_registers 248 * @defgroup SIMO_ILOAD_C SIMO_ILOAD_C 249 * @brief Buck Cycle Count VREGO_C Register 250 * @{ 251 */ 252 #define MXC_F_SIMO_ILOAD_C_ILOADC_POS 0 /**< ILOAD_C_ILOADC Position */ 253 #define MXC_F_SIMO_ILOAD_C_ILOADC ((uint32_t)(0xFFUL << MXC_F_SIMO_ILOAD_C_ILOADC_POS)) /**< ILOAD_C_ILOADC Mask */ 254 255 /**@} end of group SIMO_ILOAD_C_Register */ 256 257 /** 258 * @ingroup simo_registers 259 * @defgroup SIMO_ILOAD_D SIMO_ILOAD_D 260 * @brief Buck Cycle Count VREGO_D Register 261 * @{ 262 */ 263 #define MXC_F_SIMO_ILOAD_D_ILOADD_POS 0 /**< ILOAD_D_ILOADD Position */ 264 #define MXC_F_SIMO_ILOAD_D_ILOADD ((uint32_t)(0xFFUL << MXC_F_SIMO_ILOAD_D_ILOADD_POS)) /**< ILOAD_D_ILOADD Mask */ 265 266 /**@} end of group SIMO_ILOAD_D_Register */ 267 268 /** 269 * @ingroup simo_registers 270 * @defgroup SIMO_BUCK_ALERT_THR_A SIMO_BUCK_ALERT_THR_A 271 * @brief Buck Cycle Count Alert VERGO_A Register 272 * @{ 273 */ 274 #define MXC_F_SIMO_BUCK_ALERT_THR_A_BUCKTHRA_POS 0 /**< BUCK_ALERT_THR_A_BUCKTHRA Position */ 275 #define MXC_F_SIMO_BUCK_ALERT_THR_A_BUCKTHRA ((uint32_t)(0xFFUL << MXC_F_SIMO_BUCK_ALERT_THR_A_BUCKTHRA_POS)) /**< BUCK_ALERT_THR_A_BUCKTHRA Mask */ 276 277 /**@} end of group SIMO_BUCK_ALERT_THR_A_Register */ 278 279 /** 280 * @ingroup simo_registers 281 * @defgroup SIMO_BUCK_ALERT_THR_B SIMO_BUCK_ALERT_THR_B 282 * @brief Buck Cycle Count Alert VERGO_B Register 283 * @{ 284 */ 285 #define MXC_F_SIMO_BUCK_ALERT_THR_B_BUCKTHRB_POS 0 /**< BUCK_ALERT_THR_B_BUCKTHRB Position */ 286 #define MXC_F_SIMO_BUCK_ALERT_THR_B_BUCKTHRB ((uint32_t)(0xFFUL << MXC_F_SIMO_BUCK_ALERT_THR_B_BUCKTHRB_POS)) /**< BUCK_ALERT_THR_B_BUCKTHRB Mask */ 287 288 /**@} end of group SIMO_BUCK_ALERT_THR_B_Register */ 289 290 /** 291 * @ingroup simo_registers 292 * @defgroup SIMO_BUCK_ALERT_THR_C SIMO_BUCK_ALERT_THR_C 293 * @brief Buck Cycle Count Alert VERGO_C Register 294 * @{ 295 */ 296 #define MXC_F_SIMO_BUCK_ALERT_THR_C_BUCKTHRC_POS 0 /**< BUCK_ALERT_THR_C_BUCKTHRC Position */ 297 #define MXC_F_SIMO_BUCK_ALERT_THR_C_BUCKTHRC ((uint32_t)(0xFFUL << MXC_F_SIMO_BUCK_ALERT_THR_C_BUCKTHRC_POS)) /**< BUCK_ALERT_THR_C_BUCKTHRC Mask */ 298 299 /**@} end of group SIMO_BUCK_ALERT_THR_C_Register */ 300 301 /** 302 * @ingroup simo_registers 303 * @defgroup SIMO_BUCK_ALERT_THR_D SIMO_BUCK_ALERT_THR_D 304 * @brief Buck Cycle Count Alert VERGO_D Register 305 * @{ 306 */ 307 #define MXC_F_SIMO_BUCK_ALERT_THR_D_BUCKTHRD_POS 0 /**< BUCK_ALERT_THR_D_BUCKTHRD Position */ 308 #define MXC_F_SIMO_BUCK_ALERT_THR_D_BUCKTHRD ((uint32_t)(0xFFUL << MXC_F_SIMO_BUCK_ALERT_THR_D_BUCKTHRD_POS)) /**< BUCK_ALERT_THR_D_BUCKTHRD Mask */ 309 310 /**@} end of group SIMO_BUCK_ALERT_THR_D_Register */ 311 312 /** 313 * @ingroup simo_registers 314 * @defgroup SIMO_BUCK_OUT_READY SIMO_BUCK_OUT_READY 315 * @brief Buck Regulator Output Ready Register 316 * @{ 317 */ 318 #define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYA_POS 0 /**< BUCK_OUT_READY_BUCKOUTRDYA Position */ 319 #define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYA ((uint32_t)(0x1UL << MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYA_POS)) /**< BUCK_OUT_READY_BUCKOUTRDYA Mask */ 320 321 #define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYB_POS 1 /**< BUCK_OUT_READY_BUCKOUTRDYB Position */ 322 #define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYB ((uint32_t)(0x1UL << MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYB_POS)) /**< BUCK_OUT_READY_BUCKOUTRDYB Mask */ 323 324 #define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYC_POS 2 /**< BUCK_OUT_READY_BUCKOUTRDYC Position */ 325 #define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYC ((uint32_t)(0x1UL << MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYC_POS)) /**< BUCK_OUT_READY_BUCKOUTRDYC Mask */ 326 327 #define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYD_POS 3 /**< BUCK_OUT_READY_BUCKOUTRDYD Position */ 328 #define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYD ((uint32_t)(0x1UL << MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYD_POS)) /**< BUCK_OUT_READY_BUCKOUTRDYD Mask */ 329 330 /**@} end of group SIMO_BUCK_OUT_READY_Register */ 331 332 /** 333 * @ingroup simo_registers 334 * @defgroup SIMO_ZERO_CROSS_CAL_A SIMO_ZERO_CROSS_CAL_A 335 * @brief Zero Cross Calibration VERGO_A Register 336 * @{ 337 */ 338 #define MXC_F_SIMO_ZERO_CROSS_CAL_A_ZXCALA_POS 0 /**< ZERO_CROSS_CAL_A_ZXCALA Position */ 339 #define MXC_F_SIMO_ZERO_CROSS_CAL_A_ZXCALA ((uint32_t)(0xFUL << MXC_F_SIMO_ZERO_CROSS_CAL_A_ZXCALA_POS)) /**< ZERO_CROSS_CAL_A_ZXCALA Mask */ 340 341 /**@} end of group SIMO_ZERO_CROSS_CAL_A_Register */ 342 343 /** 344 * @ingroup simo_registers 345 * @defgroup SIMO_ZERO_CROSS_CAL_B SIMO_ZERO_CROSS_CAL_B 346 * @brief Zero Cross Calibration VERGO_B Register 347 * @{ 348 */ 349 #define MXC_F_SIMO_ZERO_CROSS_CAL_B_ZXCALB_POS 0 /**< ZERO_CROSS_CAL_B_ZXCALB Position */ 350 #define MXC_F_SIMO_ZERO_CROSS_CAL_B_ZXCALB ((uint32_t)(0xFUL << MXC_F_SIMO_ZERO_CROSS_CAL_B_ZXCALB_POS)) /**< ZERO_CROSS_CAL_B_ZXCALB Mask */ 351 352 /**@} end of group SIMO_ZERO_CROSS_CAL_B_Register */ 353 354 /** 355 * @ingroup simo_registers 356 * @defgroup SIMO_ZERO_CROSS_CAL_C SIMO_ZERO_CROSS_CAL_C 357 * @brief Zero Cross Calibration VERGO_C Register 358 * @{ 359 */ 360 #define MXC_F_SIMO_ZERO_CROSS_CAL_C_ZXCALC_POS 0 /**< ZERO_CROSS_CAL_C_ZXCALC Position */ 361 #define MXC_F_SIMO_ZERO_CROSS_CAL_C_ZXCALC ((uint32_t)(0xFUL << MXC_F_SIMO_ZERO_CROSS_CAL_C_ZXCALC_POS)) /**< ZERO_CROSS_CAL_C_ZXCALC Mask */ 362 363 /**@} end of group SIMO_ZERO_CROSS_CAL_C_Register */ 364 365 /** 366 * @ingroup simo_registers 367 * @defgroup SIMO_ZERO_CROSS_CAL_D SIMO_ZERO_CROSS_CAL_D 368 * @brief Zero Cross Calibration VERGO_D Register 369 * @{ 370 */ 371 #define MXC_F_SIMO_ZERO_CROSS_CAL_D_ZXCALD_POS 0 /**< ZERO_CROSS_CAL_D_ZXCALD Position */ 372 #define MXC_F_SIMO_ZERO_CROSS_CAL_D_ZXCALD ((uint32_t)(0xFUL << MXC_F_SIMO_ZERO_CROSS_CAL_D_ZXCALD_POS)) /**< ZERO_CROSS_CAL_D_ZXCALD Mask */ 373 374 /**@} end of group SIMO_ZERO_CROSS_CAL_D_Register */ 375 376 #ifdef __cplusplus 377 } 378 #endif 379 380 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_SIMO_REGS_H_ 381
