1 /** 2 * @file ptg_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the PTG Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup ptg_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_PTG_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_PTG_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup ptg 67 * @defgroup ptg_registers PTG_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the PTG Peripheral Module. 69 * @details Pulse Train Generation 70 */ 71 72 /** 73 * @ingroup ptg_registers 74 * Structure type to access the PTG Registers. 75 */ 76 typedef struct { 77 __IO uint32_t enable; /**< <tt>\b 0x0000:</tt> PTG ENABLE Register */ 78 __IO uint32_t resync; /**< <tt>\b 0x0004:</tt> PTG RESYNC Register */ 79 __IO uint32_t stop_intfl; /**< <tt>\b 0x0008:</tt> PTG STOP_INTFL Register */ 80 __IO uint32_t stop_inten; /**< <tt>\b 0x000C:</tt> PTG STOP_INTEN Register */ 81 __O uint32_t safe_en; /**< <tt>\b 0x0010:</tt> PTG SAFE_EN Register */ 82 __O uint32_t safe_dis; /**< <tt>\b 0x0014:</tt> PTG SAFE_DIS Register */ 83 __IO uint32_t ready_intfl; /**< <tt>\b 0x0018:</tt> PTG READY_INTFL Register */ 84 __IO uint32_t ready_inten; /**< <tt>\b 0x001C:</tt> PTG READY_INTEN Register */ 85 } mxc_ptg_regs_t; 86 87 /* Register offsets for module PTG */ 88 /** 89 * @ingroup ptg_registers 90 * @defgroup PTG_Register_Offsets Register Offsets 91 * @brief PTG Peripheral Register Offsets from the PTG Base Peripheral Address. 92 * @{ 93 */ 94 #define MXC_R_PTG_ENABLE ((uint32_t)0x00000000UL) /**< Offset from PTG Base Address: <tt> 0x0000</tt> */ 95 #define MXC_R_PTG_RESYNC ((uint32_t)0x00000004UL) /**< Offset from PTG Base Address: <tt> 0x0004</tt> */ 96 #define MXC_R_PTG_STOP_INTFL ((uint32_t)0x00000008UL) /**< Offset from PTG Base Address: <tt> 0x0008</tt> */ 97 #define MXC_R_PTG_STOP_INTEN ((uint32_t)0x0000000CUL) /**< Offset from PTG Base Address: <tt> 0x000C</tt> */ 98 #define MXC_R_PTG_SAFE_EN ((uint32_t)0x00000010UL) /**< Offset from PTG Base Address: <tt> 0x0010</tt> */ 99 #define MXC_R_PTG_SAFE_DIS ((uint32_t)0x00000014UL) /**< Offset from PTG Base Address: <tt> 0x0014</tt> */ 100 #define MXC_R_PTG_READY_INTFL ((uint32_t)0x00000018UL) /**< Offset from PTG Base Address: <tt> 0x0018</tt> */ 101 #define MXC_R_PTG_READY_INTEN ((uint32_t)0x0000001CUL) /**< Offset from PTG Base Address: <tt> 0x001C</tt> */ 102 /**@} end of group ptg_registers */ 103 104 /** 105 * @ingroup ptg_registers 106 * @defgroup PTG_ENABLE PTG_ENABLE 107 * @brief Global Enable/Disable Controls for All Pulse Trains 108 * @{ 109 */ 110 #define MXC_F_PTG_ENABLE_PT0_POS 0 /**< ENABLE_PT0 Position */ 111 #define MXC_F_PTG_ENABLE_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT0_POS)) /**< ENABLE_PT0 Mask */ 112 113 #define MXC_F_PTG_ENABLE_PT1_POS 1 /**< ENABLE_PT1 Position */ 114 #define MXC_F_PTG_ENABLE_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT1_POS)) /**< ENABLE_PT1 Mask */ 115 116 #define MXC_F_PTG_ENABLE_PT2_POS 2 /**< ENABLE_PT2 Position */ 117 #define MXC_F_PTG_ENABLE_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT2_POS)) /**< ENABLE_PT2 Mask */ 118 119 #define MXC_F_PTG_ENABLE_PT3_POS 3 /**< ENABLE_PT3 Position */ 120 #define MXC_F_PTG_ENABLE_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT3_POS)) /**< ENABLE_PT3 Mask */ 121 122 /**@} end of group PTG_ENABLE_Register */ 123 124 /** 125 * @ingroup ptg_registers 126 * @defgroup PTG_RESYNC PTG_RESYNC 127 * @brief Global Resync (All Pulse Trains) Control 128 * @{ 129 */ 130 #define MXC_F_PTG_RESYNC_PT0_POS 0 /**< RESYNC_PT0 Position */ 131 #define MXC_F_PTG_RESYNC_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT0_POS)) /**< RESYNC_PT0 Mask */ 132 133 #define MXC_F_PTG_RESYNC_PT1_POS 1 /**< RESYNC_PT1 Position */ 134 #define MXC_F_PTG_RESYNC_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT1_POS)) /**< RESYNC_PT1 Mask */ 135 136 #define MXC_F_PTG_RESYNC_PT2_POS 2 /**< RESYNC_PT2 Position */ 137 #define MXC_F_PTG_RESYNC_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT2_POS)) /**< RESYNC_PT2 Mask */ 138 139 #define MXC_F_PTG_RESYNC_PT3_POS 3 /**< RESYNC_PT3 Position */ 140 #define MXC_F_PTG_RESYNC_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT3_POS)) /**< RESYNC_PT3 Mask */ 141 142 /**@} end of group PTG_RESYNC_Register */ 143 144 /** 145 * @ingroup ptg_registers 146 * @defgroup PTG_STOP_INTFL PTG_STOP_INTFL 147 * @brief Pulse Train Stop Interrupt Flags 148 * @{ 149 */ 150 #define MXC_F_PTG_STOP_INTFL_PT0_POS 0 /**< STOP_INTFL_PT0 Position */ 151 #define MXC_F_PTG_STOP_INTFL_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT0_POS)) /**< STOP_INTFL_PT0 Mask */ 152 153 #define MXC_F_PTG_STOP_INTFL_PT1_POS 1 /**< STOP_INTFL_PT1 Position */ 154 #define MXC_F_PTG_STOP_INTFL_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT1_POS)) /**< STOP_INTFL_PT1 Mask */ 155 156 #define MXC_F_PTG_STOP_INTFL_PT2_POS 2 /**< STOP_INTFL_PT2 Position */ 157 #define MXC_F_PTG_STOP_INTFL_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT2_POS)) /**< STOP_INTFL_PT2 Mask */ 158 159 #define MXC_F_PTG_STOP_INTFL_PT3_POS 3 /**< STOP_INTFL_PT3 Position */ 160 #define MXC_F_PTG_STOP_INTFL_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT3_POS)) /**< STOP_INTFL_PT3 Mask */ 161 162 /**@} end of group PTG_STOP_INTFL_Register */ 163 164 /** 165 * @ingroup ptg_registers 166 * @defgroup PTG_STOP_INTEN PTG_STOP_INTEN 167 * @brief Pulse Train Stop Interrupt Enable/Disable 168 * @{ 169 */ 170 #define MXC_F_PTG_STOP_INTEN_PT0_POS 0 /**< STOP_INTEN_PT0 Position */ 171 #define MXC_F_PTG_STOP_INTEN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT0_POS)) /**< STOP_INTEN_PT0 Mask */ 172 173 #define MXC_F_PTG_STOP_INTEN_PT1_POS 1 /**< STOP_INTEN_PT1 Position */ 174 #define MXC_F_PTG_STOP_INTEN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT1_POS)) /**< STOP_INTEN_PT1 Mask */ 175 176 #define MXC_F_PTG_STOP_INTEN_PT2_POS 2 /**< STOP_INTEN_PT2 Position */ 177 #define MXC_F_PTG_STOP_INTEN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT2_POS)) /**< STOP_INTEN_PT2 Mask */ 178 179 #define MXC_F_PTG_STOP_INTEN_PT3_POS 3 /**< STOP_INTEN_PT3 Position */ 180 #define MXC_F_PTG_STOP_INTEN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT3_POS)) /**< STOP_INTEN_PT3 Mask */ 181 182 /**@} end of group PTG_STOP_INTEN_Register */ 183 184 /** 185 * @ingroup ptg_registers 186 * @defgroup PTG_SAFE_EN PTG_SAFE_EN 187 * @brief Pulse Train Global Safe Enable. 188 * @{ 189 */ 190 #define MXC_F_PTG_SAFE_EN_PT0_POS 0 /**< SAFE_EN_PT0 Position */ 191 #define MXC_F_PTG_SAFE_EN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT0_POS)) /**< SAFE_EN_PT0 Mask */ 192 193 #define MXC_F_PTG_SAFE_EN_PT1_POS 1 /**< SAFE_EN_PT1 Position */ 194 #define MXC_F_PTG_SAFE_EN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT1_POS)) /**< SAFE_EN_PT1 Mask */ 195 196 #define MXC_F_PTG_SAFE_EN_PT2_POS 2 /**< SAFE_EN_PT2 Position */ 197 #define MXC_F_PTG_SAFE_EN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT2_POS)) /**< SAFE_EN_PT2 Mask */ 198 199 #define MXC_F_PTG_SAFE_EN_PT3_POS 3 /**< SAFE_EN_PT3 Position */ 200 #define MXC_F_PTG_SAFE_EN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT3_POS)) /**< SAFE_EN_PT3 Mask */ 201 202 /**@} end of group PTG_SAFE_EN_Register */ 203 204 /** 205 * @ingroup ptg_registers 206 * @defgroup PTG_SAFE_DIS PTG_SAFE_DIS 207 * @brief Pulse Train Global Safe Disable. 208 * @{ 209 */ 210 #define MXC_F_PTG_SAFE_DIS_PT0_POS 0 /**< SAFE_DIS_PT0 Position */ 211 #define MXC_F_PTG_SAFE_DIS_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT0_POS)) /**< SAFE_DIS_PT0 Mask */ 212 213 #define MXC_F_PTG_SAFE_DIS_PT1_POS 1 /**< SAFE_DIS_PT1 Position */ 214 #define MXC_F_PTG_SAFE_DIS_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT1_POS)) /**< SAFE_DIS_PT1 Mask */ 215 216 #define MXC_F_PTG_SAFE_DIS_PT2_POS 2 /**< SAFE_DIS_PT2 Position */ 217 #define MXC_F_PTG_SAFE_DIS_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT2_POS)) /**< SAFE_DIS_PT2 Mask */ 218 219 #define MXC_F_PTG_SAFE_DIS_PT3_POS 3 /**< SAFE_DIS_PT3 Position */ 220 #define MXC_F_PTG_SAFE_DIS_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT3_POS)) /**< SAFE_DIS_PT3 Mask */ 221 222 /**@} end of group PTG_SAFE_DIS_Register */ 223 224 /** 225 * @ingroup ptg_registers 226 * @defgroup PTG_READY_INTFL PTG_READY_INTFL 227 * @brief Pulse Train Ready Interrupt Flags 228 * @{ 229 */ 230 #define MXC_F_PTG_READY_INTFL_PT0_POS 0 /**< READY_INTFL_PT0 Position */ 231 #define MXC_F_PTG_READY_INTFL_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT0_POS)) /**< READY_INTFL_PT0 Mask */ 232 233 #define MXC_F_PTG_READY_INTFL_PT1_POS 1 /**< READY_INTFL_PT1 Position */ 234 #define MXC_F_PTG_READY_INTFL_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT1_POS)) /**< READY_INTFL_PT1 Mask */ 235 236 #define MXC_F_PTG_READY_INTFL_PT2_POS 2 /**< READY_INTFL_PT2 Position */ 237 #define MXC_F_PTG_READY_INTFL_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT2_POS)) /**< READY_INTFL_PT2 Mask */ 238 239 #define MXC_F_PTG_READY_INTFL_PT3_POS 3 /**< READY_INTFL_PT3 Position */ 240 #define MXC_F_PTG_READY_INTFL_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT3_POS)) /**< READY_INTFL_PT3 Mask */ 241 242 /**@} end of group PTG_READY_INTFL_Register */ 243 244 /** 245 * @ingroup ptg_registers 246 * @defgroup PTG_READY_INTEN PTG_READY_INTEN 247 * @brief Pulse Train Ready Interrupt Enable/Disable 248 * @{ 249 */ 250 #define MXC_F_PTG_READY_INTEN_PT0_POS 0 /**< READY_INTEN_PT0 Position */ 251 #define MXC_F_PTG_READY_INTEN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT0_POS)) /**< READY_INTEN_PT0 Mask */ 252 253 #define MXC_F_PTG_READY_INTEN_PT1_POS 1 /**< READY_INTEN_PT1 Position */ 254 #define MXC_F_PTG_READY_INTEN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT1_POS)) /**< READY_INTEN_PT1 Mask */ 255 256 #define MXC_F_PTG_READY_INTEN_PT2_POS 2 /**< READY_INTEN_PT2 Position */ 257 #define MXC_F_PTG_READY_INTEN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT2_POS)) /**< READY_INTEN_PT2 Mask */ 258 259 #define MXC_F_PTG_READY_INTEN_PT3_POS 3 /**< READY_INTEN_PT3 Position */ 260 #define MXC_F_PTG_READY_INTEN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT3_POS)) /**< READY_INTEN_PT3 Mask */ 261 262 /**@} end of group PTG_READY_INTEN_Register */ 263 264 #ifdef __cplusplus 265 } 266 #endif 267 268 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_PTG_REGS_H_ 269
