1 /** 2 * @file mcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup mcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_MCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_MCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup mcr 67 * @defgroup mcr_registers MCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. 69 * @details Misc Control. 70 */ 71 72 /** 73 * @ingroup mcr_registers 74 * Structure type to access the MCR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t eccen; /**< <tt>\b 0x00:</tt> MCR ECCEN Register */ 78 __IO uint32_t ipo_mtrim; /**< <tt>\b 0x04:</tt> MCR IPO_MTRIM Register */ 79 __IO uint32_t outen; /**< <tt>\b 0x08:</tt> MCR OUTEN Register */ 80 __IO uint32_t cmp_ctrl; /**< <tt>\b 0x0C:</tt> MCR CMP_CTRL Register */ 81 __IO uint32_t ctrl; /**< <tt>\b 0x10:</tt> MCR CTRL Register */ 82 __R uint32_t rsv_0x14_0x1f[3]; 83 __IO uint32_t gpio3_ctrl; /**< <tt>\b 0x20:</tt> MCR GPIO3_CTRL Register */ 84 } mxc_mcr_regs_t; 85 86 /* Register offsets for module MCR */ 87 /** 88 * @ingroup mcr_registers 89 * @defgroup MCR_Register_Offsets Register Offsets 90 * @brief MCR Peripheral Register Offsets from the MCR Base Peripheral Address. 91 * @{ 92 */ 93 #define MXC_R_MCR_ECCEN ((uint32_t)0x00000000UL) /**< Offset from MCR Base Address: <tt> 0x0000</tt> */ 94 #define MXC_R_MCR_IPO_MTRIM ((uint32_t)0x00000004UL) /**< Offset from MCR Base Address: <tt> 0x0004</tt> */ 95 #define MXC_R_MCR_OUTEN ((uint32_t)0x00000008UL) /**< Offset from MCR Base Address: <tt> 0x0008</tt> */ 96 #define MXC_R_MCR_CMP_CTRL ((uint32_t)0x0000000CUL) /**< Offset from MCR Base Address: <tt> 0x000C</tt> */ 97 #define MXC_R_MCR_CTRL ((uint32_t)0x00000010UL) /**< Offset from MCR Base Address: <tt> 0x0010</tt> */ 98 #define MXC_R_MCR_GPIO3_CTRL ((uint32_t)0x00000020UL) /**< Offset from MCR Base Address: <tt> 0x0020</tt> */ 99 /**@} end of group mcr_registers */ 100 101 /** 102 * @ingroup mcr_registers 103 * @defgroup MCR_ECCEN MCR_ECCEN 104 * @brief ECC Enable Register 105 * @{ 106 */ 107 #define MXC_F_MCR_ECCEN_RAM0_POS 0 /**< ECCEN_RAM0 Position */ 108 #define MXC_F_MCR_ECCEN_RAM0 ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_RAM0_POS)) /**< ECCEN_RAM0 Mask */ 109 110 /**@} end of group MCR_ECCEN_Register */ 111 112 /** 113 * @ingroup mcr_registers 114 * @defgroup MCR_IPO_MTRIM MCR_IPO_MTRIM 115 * @brief IPO Manual Register 116 * @{ 117 */ 118 #define MXC_F_MCR_IPO_MTRIM_MTRIM_POS 0 /**< IPO_MTRIM_MTRIM Position */ 119 #define MXC_F_MCR_IPO_MTRIM_MTRIM ((uint32_t)(0xFFUL << MXC_F_MCR_IPO_MTRIM_MTRIM_POS)) /**< IPO_MTRIM_MTRIM Mask */ 120 121 #define MXC_F_MCR_IPO_MTRIM_TRIM_RANGE_POS 8 /**< IPO_MTRIM_TRIM_RANGE Position */ 122 #define MXC_F_MCR_IPO_MTRIM_TRIM_RANGE ((uint32_t)(0x1UL << MXC_F_MCR_IPO_MTRIM_TRIM_RANGE_POS)) /**< IPO_MTRIM_TRIM_RANGE Mask */ 123 124 /**@} end of group MCR_IPO_MTRIM_Register */ 125 126 /** 127 * @ingroup mcr_registers 128 * @defgroup MCR_OUTEN MCR_OUTEN 129 * @brief Output Enable Register 130 * @{ 131 */ 132 #define MXC_F_MCR_OUTEN_SQWOUT_EN_POS 0 /**< OUTEN_SQWOUT_EN Position */ 133 #define MXC_F_MCR_OUTEN_SQWOUT_EN ((uint32_t)(0x1UL << MXC_F_MCR_OUTEN_SQWOUT_EN_POS)) /**< OUTEN_SQWOUT_EN Mask */ 134 135 #define MXC_F_MCR_OUTEN_PDOWN_OUT_EN_POS 1 /**< OUTEN_PDOWN_OUT_EN Position */ 136 #define MXC_F_MCR_OUTEN_PDOWN_OUT_EN ((uint32_t)(0x1UL << MXC_F_MCR_OUTEN_PDOWN_OUT_EN_POS)) /**< OUTEN_PDOWN_OUT_EN Mask */ 137 138 /**@} end of group MCR_OUTEN_Register */ 139 140 /** 141 * @ingroup mcr_registers 142 * @defgroup MCR_CMP_CTRL MCR_CMP_CTRL 143 * @brief Comparator Control Register. 144 * @{ 145 */ 146 #define MXC_F_MCR_CMP_CTRL_EN_POS 0 /**< CMP_CTRL_EN Position */ 147 #define MXC_F_MCR_CMP_CTRL_EN ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_EN_POS)) /**< CMP_CTRL_EN Mask */ 148 149 #define MXC_F_MCR_CMP_CTRL_POL_POS 5 /**< CMP_CTRL_POL Position */ 150 #define MXC_F_MCR_CMP_CTRL_POL ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_POL_POS)) /**< CMP_CTRL_POL Mask */ 151 152 #define MXC_F_MCR_CMP_CTRL_INT_EN_POS 6 /**< CMP_CTRL_INT_EN Position */ 153 #define MXC_F_MCR_CMP_CTRL_INT_EN ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_INT_EN_POS)) /**< CMP_CTRL_INT_EN Mask */ 154 155 #define MXC_F_MCR_CMP_CTRL_OUT_POS 14 /**< CMP_CTRL_OUT Position */ 156 #define MXC_F_MCR_CMP_CTRL_OUT ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_OUT_POS)) /**< CMP_CTRL_OUT Mask */ 157 158 #define MXC_F_MCR_CMP_CTRL_INT_FL_POS 15 /**< CMP_CTRL_INT_FL Position */ 159 #define MXC_F_MCR_CMP_CTRL_INT_FL ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_INT_FL_POS)) /**< CMP_CTRL_INT_FL Mask */ 160 161 /**@} end of group MCR_CMP_CTRL_Register */ 162 163 /** 164 * @ingroup mcr_registers 165 * @defgroup MCR_CTRL MCR_CTRL 166 * @brief Miscellaneous Control Register. 167 * @{ 168 */ 169 #define MXC_F_MCR_CTRL_CMPHYST_POS 0 /**< CTRL_CMPHYST Position */ 170 #define MXC_F_MCR_CTRL_CMPHYST ((uint32_t)(0x3UL << MXC_F_MCR_CTRL_CMPHYST_POS)) /**< CTRL_CMPHYST Mask */ 171 172 #define MXC_F_MCR_CTRL_INRO_EN_POS 2 /**< CTRL_INRO_EN Position */ 173 #define MXC_F_MCR_CTRL_INRO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_INRO_EN_POS)) /**< CTRL_INRO_EN Mask */ 174 175 #define MXC_F_MCR_CTRL_ERTCO_EN_POS 3 /**< CTRL_ERTCO_EN Position */ 176 #define MXC_F_MCR_CTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_ERTCO_EN_POS)) /**< CTRL_ERTCO_EN Mask */ 177 178 #define MXC_F_MCR_CTRL_IBRO_EN_POS 4 /**< CTRL_IBRO_EN Position */ 179 #define MXC_F_MCR_CTRL_IBRO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_IBRO_EN_POS)) /**< CTRL_IBRO_EN Mask */ 180 181 #define MXC_F_MCR_CTRL_32KOSC_EN_POS 5 /**< CTRL_32KOSC_EN Position */ 182 #define MXC_F_MCR_CTRL_32KOSC_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_32KOSC_EN_POS)) /**< CTRL_32KOSC_EN Mask */ 183 184 #define MXC_F_MCR_CTRL_SIMO_CLKSCL_EN_POS 8 /**< CTRL_SIMO_CLKSCL_EN Position */ 185 #define MXC_F_MCR_CTRL_SIMO_CLKSCL_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_SIMO_CLKSCL_EN_POS)) /**< CTRL_SIMO_CLKSCL_EN Mask */ 186 187 #define MXC_F_MCR_CTRL_SIMO_RSTD_POS 9 /**< CTRL_SIMO_RSTD Position */ 188 #define MXC_F_MCR_CTRL_SIMO_RSTD ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_SIMO_RSTD_POS)) /**< CTRL_SIMO_RSTD Mask */ 189 190 /**@} end of group MCR_CTRL_Register */ 191 192 /** 193 * @ingroup mcr_registers 194 * @defgroup MCR_GPIO3_CTRL MCR_GPIO3_CTRL 195 * @brief GPIO3 Pin Control Register. 196 * @{ 197 */ 198 #define MXC_F_MCR_GPIO3_CTRL_P30_DO_POS 0 /**< GPIO3_CTRL_P30_DO Position */ 199 #define MXC_F_MCR_GPIO3_CTRL_P30_DO ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_DO_POS)) /**< GPIO3_CTRL_P30_DO Mask */ 200 201 #define MXC_F_MCR_GPIO3_CTRL_P30_OE_POS 1 /**< GPIO3_CTRL_P30_OE Position */ 202 #define MXC_F_MCR_GPIO3_CTRL_P30_OE ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_OE_POS)) /**< GPIO3_CTRL_P30_OE Mask */ 203 204 #define MXC_F_MCR_GPIO3_CTRL_P30_PE_POS 2 /**< GPIO3_CTRL_P30_PE Position */ 205 #define MXC_F_MCR_GPIO3_CTRL_P30_PE ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_PE_POS)) /**< GPIO3_CTRL_P30_PE Mask */ 206 207 #define MXC_F_MCR_GPIO3_CTRL_P30_IN_POS 3 /**< GPIO3_CTRL_P30_IN Position */ 208 #define MXC_F_MCR_GPIO3_CTRL_P30_IN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_IN_POS)) /**< GPIO3_CTRL_P30_IN Mask */ 209 210 #define MXC_F_MCR_GPIO3_CTRL_P31_DO_POS 4 /**< GPIO3_CTRL_P31_DO Position */ 211 #define MXC_F_MCR_GPIO3_CTRL_P31_DO ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_DO_POS)) /**< GPIO3_CTRL_P31_DO Mask */ 212 213 #define MXC_F_MCR_GPIO3_CTRL_P31_OE_POS 5 /**< GPIO3_CTRL_P31_OE Position */ 214 #define MXC_F_MCR_GPIO3_CTRL_P31_OE ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_OE_POS)) /**< GPIO3_CTRL_P31_OE Mask */ 215 216 #define MXC_F_MCR_GPIO3_CTRL_P31_PE_POS 6 /**< GPIO3_CTRL_P31_PE Position */ 217 #define MXC_F_MCR_GPIO3_CTRL_P31_PE ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_PE_POS)) /**< GPIO3_CTRL_P31_PE Mask */ 218 219 #define MXC_F_MCR_GPIO3_CTRL_P31_IN_POS 7 /**< GPIO3_CTRL_P31_IN Position */ 220 #define MXC_F_MCR_GPIO3_CTRL_P31_IN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_IN_POS)) /**< GPIO3_CTRL_P31_IN Mask */ 221 222 /**@} end of group MCR_GPIO3_CTRL_Register */ 223 224 #ifdef __cplusplus 225 } 226 #endif 227 228 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_MCR_REGS_H_ 229
