1 /** 2 * @file gcfr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the GCFR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup gcfr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_GCFR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_GCFR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup gcfr 67 * @defgroup gcfr_registers GCFR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the GCFR Peripheral Module. 69 * @details Global Control Function Register. 70 */ 71 72 /** 73 * @ingroup gcfr_registers 74 * Structure type to access the GCFR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t reg0; /**< <tt>\b 0x00:</tt> GCFR REG0 Register */ 78 __IO uint32_t reg1; /**< <tt>\b 0x04:</tt> GCFR REG1 Register */ 79 } mxc_gcfr_regs_t; 80 81 /* Register offsets for module GCFR */ 82 /** 83 * @ingroup gcfr_registers 84 * @defgroup GCFR_Register_Offsets Register Offsets 85 * @brief GCFR Peripheral Register Offsets from the GCFR Base Peripheral Address. 86 * @{ 87 */ 88 #define MXC_R_GCFR_REG0 ((uint32_t)0x00000000UL) /**< Offset from GCFR Base Address: <tt> 0x0000</tt> */ 89 #define MXC_R_GCFR_REG1 ((uint32_t)0x00000004UL) /**< Offset from GCFR Base Address: <tt> 0x0004</tt> */ 90 /**@} end of group gcfr_registers */ 91 92 /** 93 * @ingroup gcfr_registers 94 * @defgroup GCFR_REG0 GCFR_REG0 95 * @brief Register 0. 96 * @{ 97 */ 98 #define MXC_F_GCFR_REG0_ISO_WUP_POS 0 /**< REG0_ISO_WUP Position */ 99 #define MXC_F_GCFR_REG0_ISO_WUP ((uint32_t)(0x1FFUL << MXC_F_GCFR_REG0_ISO_WUP_POS)) /**< REG0_ISO_WUP Mask */ 100 101 #define MXC_F_GCFR_REG0_IPO_WUP_POS 16 /**< REG0_IPO_WUP Position */ 102 #define MXC_F_GCFR_REG0_IPO_WUP ((uint32_t)(0x7FFUL << MXC_F_GCFR_REG0_IPO_WUP_POS)) /**< REG0_IPO_WUP Mask */ 103 104 /**@} end of group GCFR_REG0_Register */ 105 106 /** 107 * @ingroup gcfr_registers 108 * @defgroup GCFR_REG1 GCFR_REG1 109 * @brief Register 1. 110 * @{ 111 */ 112 #define MXC_F_GCFR_REG1_ERFO_WUP_POS 0 /**< REG1_ERFO_WUP Position */ 113 #define MXC_F_GCFR_REG1_ERFO_WUP ((uint32_t)(0x3FFFUL << MXC_F_GCFR_REG1_ERFO_WUP_POS)) /**< REG1_ERFO_WUP Mask */ 114 115 #define MXC_F_GCFR_REG1_IBRO_WUP_POS 16 /**< REG1_IBRO_WUP Position */ 116 #define MXC_F_GCFR_REG1_IBRO_WUP ((uint32_t)(0x3FUL << MXC_F_GCFR_REG1_IBRO_WUP_POS)) /**< REG1_IBRO_WUP Mask */ 117 118 /**@} end of group GCFR_REG1_Register */ 119 120 #ifdef __cplusplus 121 } 122 #endif 123 124 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_GCFR_REGS_H_ 125
