1 /** 2 * @file fcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup fcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_FCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_FCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup fcr 67 * @defgroup fcr_registers FCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. 69 * @details Function Control Register. 70 */ 71 72 /** 73 * @ingroup fcr_registers 74 * Structure type to access the FCR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t fctrl0; /**< <tt>\b 0x00:</tt> FCR FCTRL0 Register */ 78 __IO uint32_t autocal0; /**< <tt>\b 0x04:</tt> FCR AUTOCAL0 Register */ 79 __IO uint32_t autocal1; /**< <tt>\b 0x08:</tt> FCR AUTOCAL1 Register */ 80 __IO uint32_t autocal2; /**< <tt>\b 0x0C:</tt> FCR AUTOCAL2 Register */ 81 __IO uint32_t urvbootaddr; /**< <tt>\b 0x10:</tt> FCR URVBOOTADDR Register */ 82 __IO uint32_t urvctrl; /**< <tt>\b 0x14:</tt> FCR URVCTRL Register */ 83 __IO uint32_t erfoks; /**< <tt>\b 0x18:</tt> FCR ERFOKS Register */ 84 __IO uint32_t erfo_intfl; /**< <tt>\b 0x1C:</tt> FCR ERFO_INTFL Register */ 85 __IO uint32_t erfo_inten; /**< <tt>\b 0x20:</tt> FCR ERFO_INTEN Register */ 86 } mxc_fcr_regs_t; 87 88 /* Register offsets for module FCR */ 89 /** 90 * @ingroup fcr_registers 91 * @defgroup FCR_Register_Offsets Register Offsets 92 * @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address. 93 * @{ 94 */ 95 #define MXC_R_FCR_FCTRL0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: <tt> 0x0000</tt> */ 96 #define MXC_R_FCR_AUTOCAL0 ((uint32_t)0x00000004UL) /**< Offset from FCR Base Address: <tt> 0x0004</tt> */ 97 #define MXC_R_FCR_AUTOCAL1 ((uint32_t)0x00000008UL) /**< Offset from FCR Base Address: <tt> 0x0008</tt> */ 98 #define MXC_R_FCR_AUTOCAL2 ((uint32_t)0x0000000CUL) /**< Offset from FCR Base Address: <tt> 0x000C</tt> */ 99 #define MXC_R_FCR_URVBOOTADDR ((uint32_t)0x00000010UL) /**< Offset from FCR Base Address: <tt> 0x0010</tt> */ 100 #define MXC_R_FCR_URVCTRL ((uint32_t)0x00000014UL) /**< Offset from FCR Base Address: <tt> 0x0014</tt> */ 101 #define MXC_R_FCR_ERFOKS ((uint32_t)0x00000018UL) /**< Offset from FCR Base Address: <tt> 0x0018</tt> */ 102 #define MXC_R_FCR_ERFO_INTFL ((uint32_t)0x0000001CUL) /**< Offset from FCR Base Address: <tt> 0x001C</tt> */ 103 #define MXC_R_FCR_ERFO_INTEN ((uint32_t)0x00000020UL) /**< Offset from FCR Base Address: <tt> 0x0020</tt> */ 104 /**@} end of group fcr_registers */ 105 106 /** 107 * @ingroup fcr_registers 108 * @defgroup FCR_FCTRL0 FCR_FCTRL0 109 * @brief Function Control 0. 110 * @{ 111 */ 112 #define MXC_F_FCR_FCTRL0_I2C0DGEN0_POS 20 /**< FCTRL0_I2C0DGEN0 Position */ 113 #define MXC_F_FCR_FCTRL0_I2C0DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN0_POS)) /**< FCTRL0_I2C0DGEN0 Mask */ 114 115 #define MXC_F_FCR_FCTRL0_I2C0DGEN1_POS 21 /**< FCTRL0_I2C0DGEN1 Position */ 116 #define MXC_F_FCR_FCTRL0_I2C0DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN1_POS)) /**< FCTRL0_I2C0DGEN1 Mask */ 117 118 #define MXC_F_FCR_FCTRL0_I2C1DGEN0_POS 22 /**< FCTRL0_I2C1DGEN0 Position */ 119 #define MXC_F_FCR_FCTRL0_I2C1DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN0_POS)) /**< FCTRL0_I2C1DGEN0 Mask */ 120 121 #define MXC_F_FCR_FCTRL0_I2C1DGEN1_POS 23 /**< FCTRL0_I2C1DGEN1 Position */ 122 #define MXC_F_FCR_FCTRL0_I2C1DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN1_POS)) /**< FCTRL0_I2C1DGEN1 Mask */ 123 124 #define MXC_F_FCR_FCTRL0_I2C2DGEN0_POS 24 /**< FCTRL0_I2C2DGEN0 Position */ 125 #define MXC_F_FCR_FCTRL0_I2C2DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2DGEN0_POS)) /**< FCTRL0_I2C2DGEN0 Mask */ 126 127 #define MXC_F_FCR_FCTRL0_I2C2DGEN1_POS 25 /**< FCTRL0_I2C2DGEN1 Position */ 128 #define MXC_F_FCR_FCTRL0_I2C2DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2DGEN1_POS)) /**< FCTRL0_I2C2DGEN1 Mask */ 129 130 /**@} end of group FCR_FCTRL0_Register */ 131 132 /** 133 * @ingroup fcr_registers 134 * @defgroup FCR_AUTOCAL0 FCR_AUTOCAL0 135 * @brief Automatic Calibration 0. 136 * @{ 137 */ 138 #define MXC_F_FCR_AUTOCAL0_ACEN_POS 0 /**< AUTOCAL0_ACEN Position */ 139 #define MXC_F_FCR_AUTOCAL0_ACEN ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ACEN_POS)) /**< AUTOCAL0_ACEN Mask */ 140 141 #define MXC_F_FCR_AUTOCAL0_ACRUN_POS 1 /**< AUTOCAL0_ACRUN Position */ 142 #define MXC_F_FCR_AUTOCAL0_ACRUN ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ACRUN_POS)) /**< AUTOCAL0_ACRUN Mask */ 143 144 #define MXC_F_FCR_AUTOCAL0_LDTRM_POS 2 /**< AUTOCAL0_LDTRM Position */ 145 #define MXC_F_FCR_AUTOCAL0_LDTRM ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_LDTRM_POS)) /**< AUTOCAL0_LDTRM Mask */ 146 147 #define MXC_F_FCR_AUTOCAL0_GAININV_POS 3 /**< AUTOCAL0_GAININV Position */ 148 #define MXC_F_FCR_AUTOCAL0_GAININV ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_GAININV_POS)) /**< AUTOCAL0_GAININV Mask */ 149 150 #define MXC_F_FCR_AUTOCAL0_ATOMIC_POS 4 /**< AUTOCAL0_ATOMIC Position */ 151 #define MXC_F_FCR_AUTOCAL0_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ATOMIC_POS)) /**< AUTOCAL0_ATOMIC Mask */ 152 153 #define MXC_F_FCR_AUTOCAL0_MU_POS 8 /**< AUTOCAL0_MU Position */ 154 #define MXC_F_FCR_AUTOCAL0_MU ((uint32_t)(0xFFFUL << MXC_F_FCR_AUTOCAL0_MU_POS)) /**< AUTOCAL0_MU Mask */ 155 156 #define MXC_F_FCR_AUTOCAL0_HIRC96MACTMROUT_POS 23 /**< AUTOCAL0_HIRC96MACTMROUT Position */ 157 #define MXC_F_FCR_AUTOCAL0_HIRC96MACTMROUT ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL0_HIRC96MACTMROUT_POS)) /**< AUTOCAL0_HIRC96MACTMROUT Mask */ 158 159 /**@} end of group FCR_AUTOCAL0_Register */ 160 161 /** 162 * @ingroup fcr_registers 163 * @defgroup FCR_AUTOCAL1 FCR_AUTOCAL1 164 * @brief Automatic Calibration 1. 165 * @{ 166 */ 167 #define MXC_F_FCR_AUTOCAL1_INITTRM_POS 0 /**< AUTOCAL1_INITTRM Position */ 168 #define MXC_F_FCR_AUTOCAL1_INITTRM ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL1_INITTRM_POS)) /**< AUTOCAL1_INITTRM Mask */ 169 170 /**@} end of group FCR_AUTOCAL1_Register */ 171 172 /** 173 * @ingroup fcr_registers 174 * @defgroup FCR_AUTOCAL2 FCR_AUTOCAL2 175 * @brief Automatic Calibration 2 176 * @{ 177 */ 178 #define MXC_F_FCR_AUTOCAL2_DONECNT_POS 0 /**< AUTOCAL2_DONECNT Position */ 179 #define MXC_F_FCR_AUTOCAL2_DONECNT ((uint32_t)(0xFFUL << MXC_F_FCR_AUTOCAL2_DONECNT_POS)) /**< AUTOCAL2_DONECNT Mask */ 180 181 #define MXC_F_FCR_AUTOCAL2_ACDIV_POS 8 /**< AUTOCAL2_ACDIV Position */ 182 #define MXC_F_FCR_AUTOCAL2_ACDIV ((uint32_t)(0x1FFFUL << MXC_F_FCR_AUTOCAL2_ACDIV_POS)) /**< AUTOCAL2_ACDIV Mask */ 183 184 /**@} end of group FCR_AUTOCAL2_Register */ 185 186 /** 187 * @ingroup fcr_registers 188 * @defgroup FCR_URVCTRL FCR_URVCTRL 189 * @brief RISC-V Control Register. 190 * @{ 191 */ 192 #define MXC_F_FCR_URVCTRL_MEMSEL_POS 0 /**< URVCTRL_MEMSEL Position */ 193 #define MXC_F_FCR_URVCTRL_MEMSEL ((uint32_t)(0x1UL << MXC_F_FCR_URVCTRL_MEMSEL_POS)) /**< URVCTRL_MEMSEL Mask */ 194 195 #define MXC_F_FCR_URVCTRL_IFLUSHEN_POS 1 /**< URVCTRL_IFLUSHEN Position */ 196 #define MXC_F_FCR_URVCTRL_IFLUSHEN ((uint32_t)(0x1UL << MXC_F_FCR_URVCTRL_IFLUSHEN_POS)) /**< URVCTRL_IFLUSHEN Mask */ 197 198 /**@} end of group FCR_URVCTRL_Register */ 199 200 /** 201 * @ingroup fcr_registers 202 * @defgroup FCR_ERFOKS FCR_ERFOKS 203 * @brief ERFO Kick Start Register. 204 * @{ 205 */ 206 #define MXC_F_FCR_ERFOKS_KSERFO_CNT_POS 0 /**< ERFOKS_KSERFO_CNT Position */ 207 #define MXC_F_FCR_ERFOKS_KSERFO_CNT ((uint32_t)(0x7FUL << MXC_F_FCR_ERFOKS_KSERFO_CNT_POS)) /**< ERFOKS_KSERFO_CNT Mask */ 208 209 #define MXC_F_FCR_ERFOKS_KSERFO_EN_POS 7 /**< ERFOKS_KSERFO_EN Position */ 210 #define MXC_F_FCR_ERFOKS_KSERFO_EN ((uint32_t)(0x1UL << MXC_F_FCR_ERFOKS_KSERFO_EN_POS)) /**< ERFOKS_KSERFO_EN Mask */ 211 212 #define MXC_F_FCR_ERFOKS_KSERFODRIVER_POS 8 /**< ERFOKS_KSERFODRIVER Position */ 213 #define MXC_F_FCR_ERFOKS_KSERFODRIVER ((uint32_t)(0x7UL << MXC_F_FCR_ERFOKS_KSERFODRIVER_POS)) /**< ERFOKS_KSERFODRIVER Mask */ 214 215 #define MXC_F_FCR_ERFOKS_KSERFO2X_POS 11 /**< ERFOKS_KSERFO2X Position */ 216 #define MXC_F_FCR_ERFOKS_KSERFO2X ((uint32_t)(0x1UL << MXC_F_FCR_ERFOKS_KSERFO2X_POS)) /**< ERFOKS_KSERFO2X Mask */ 217 218 #define MXC_F_FCR_ERFOKS_KSCLKSEL_POS 12 /**< ERFOKS_KSCLKSEL Position */ 219 #define MXC_F_FCR_ERFOKS_KSCLKSEL ((uint32_t)(0x3UL << MXC_F_FCR_ERFOKS_KSCLKSEL_POS)) /**< ERFOKS_KSCLKSEL Mask */ 220 #define MXC_V_FCR_ERFOKS_KSCLKSEL_ISO ((uint32_t)0x2UL) /**< ERFOKS_KSCLKSEL_ISO Value */ 221 #define MXC_S_FCR_ERFOKS_KSCLKSEL_ISO (MXC_V_FCR_ERFOKS_KSCLKSEL_ISO << MXC_F_FCR_ERFOKS_KSCLKSEL_POS) /**< ERFOKS_KSCLKSEL_ISO Setting */ 222 #define MXC_V_FCR_ERFOKS_KSCLKSEL_IPO ((uint32_t)0x3UL) /**< ERFOKS_KSCLKSEL_IPO Value */ 223 #define MXC_S_FCR_ERFOKS_KSCLKSEL_IPO (MXC_V_FCR_ERFOKS_KSCLKSEL_IPO << MXC_F_FCR_ERFOKS_KSCLKSEL_POS) /**< ERFOKS_KSCLKSEL_IPO Setting */ 224 225 /**@} end of group FCR_ERFOKS_Register */ 226 227 /** 228 * @ingroup fcr_registers 229 * @defgroup FCR_ERFO_INTFL FCR_ERFO_INTFL 230 * @brief ERFO Ready Interrupt Flag register. 231 * @{ 232 */ 233 #define MXC_F_FCR_ERFO_INTFL_RDY_POS 0 /**< ERFO_INTFL_RDY Position */ 234 #define MXC_F_FCR_ERFO_INTFL_RDY ((uint32_t)(0x1UL << MXC_F_FCR_ERFO_INTFL_RDY_POS)) /**< ERFO_INTFL_RDY Mask */ 235 236 /**@} end of group FCR_ERFO_INTFL_Register */ 237 238 /** 239 * @ingroup fcr_registers 240 * @defgroup FCR_ERFO_INTEN FCR_ERFO_INTEN 241 * @brief ERFO Ready Interrupt Enable register. 242 * @{ 243 */ 244 #define MXC_F_FCR_ERFO_INTEN_RDY_POS 0 /**< ERFO_INTEN_RDY Position */ 245 #define MXC_F_FCR_ERFO_INTEN_RDY ((uint32_t)(0x1UL << MXC_F_FCR_ERFO_INTEN_RDY_POS)) /**< ERFO_INTEN_RDY Mask */ 246 247 /**@} end of group FCR_ERFO_INTEN_Register */ 248 249 #ifdef __cplusplus 250 } 251 #endif 252 253 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_FCR_REGS_H_ 254
