1 /** 2 * @file aes_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup aes_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_AES_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_AES_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup aes 67 * @defgroup aes_registers AES_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module. 69 * @details AES Keys. 70 */ 71 72 /** 73 * @ingroup aes_registers 74 * Structure type to access the AES Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> AES CTRL Register */ 78 __IO uint32_t status; /**< <tt>\b 0x0004:</tt> AES STATUS Register */ 79 __IO uint32_t intfl; /**< <tt>\b 0x0008:</tt> AES INTFL Register */ 80 __IO uint32_t inten; /**< <tt>\b 0x000C:</tt> AES INTEN Register */ 81 __IO uint32_t fifo; /**< <tt>\b 0x0010:</tt> AES FIFO Register */ 82 } mxc_aes_regs_t; 83 84 /* Register offsets for module AES */ 85 /** 86 * @ingroup aes_registers 87 * @defgroup AES_Register_Offsets Register Offsets 88 * @brief AES Peripheral Register Offsets from the AES Base Peripheral Address. 89 * @{ 90 */ 91 #define MXC_R_AES_CTRL ((uint32_t)0x00000000UL) /**< Offset from AES Base Address: <tt> 0x0000</tt> */ 92 #define MXC_R_AES_STATUS ((uint32_t)0x00000004UL) /**< Offset from AES Base Address: <tt> 0x0004</tt> */ 93 #define MXC_R_AES_INTFL ((uint32_t)0x00000008UL) /**< Offset from AES Base Address: <tt> 0x0008</tt> */ 94 #define MXC_R_AES_INTEN ((uint32_t)0x0000000CUL) /**< Offset from AES Base Address: <tt> 0x000C</tt> */ 95 #define MXC_R_AES_FIFO ((uint32_t)0x00000010UL) /**< Offset from AES Base Address: <tt> 0x0010</tt> */ 96 /**@} end of group aes_registers */ 97 98 /** 99 * @ingroup aes_registers 100 * @defgroup AES_CTRL AES_CTRL 101 * @brief AES Control Register 102 * @{ 103 */ 104 #define MXC_F_AES_CTRL_EN_POS 0 /**< CTRL_EN Position */ 105 #define MXC_F_AES_CTRL_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_EN_POS)) /**< CTRL_EN Mask */ 106 107 #define MXC_F_AES_CTRL_DMA_RX_EN_POS 1 /**< CTRL_DMA_RX_EN Position */ 108 #define MXC_F_AES_CTRL_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_RX_EN_POS)) /**< CTRL_DMA_RX_EN Mask */ 109 110 #define MXC_F_AES_CTRL_DMA_TX_EN_POS 2 /**< CTRL_DMA_TX_EN Position */ 111 #define MXC_F_AES_CTRL_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_TX_EN_POS)) /**< CTRL_DMA_TX_EN Mask */ 112 113 #define MXC_F_AES_CTRL_START_POS 3 /**< CTRL_START Position */ 114 #define MXC_F_AES_CTRL_START ((uint32_t)(0x1UL << MXC_F_AES_CTRL_START_POS)) /**< CTRL_START Mask */ 115 116 #define MXC_F_AES_CTRL_INPUT_FLUSH_POS 4 /**< CTRL_INPUT_FLUSH Position */ 117 #define MXC_F_AES_CTRL_INPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_CTRL_INPUT_FLUSH_POS)) /**< CTRL_INPUT_FLUSH Mask */ 118 119 #define MXC_F_AES_CTRL_OUTPUT_FLUSH_POS 5 /**< CTRL_OUTPUT_FLUSH Position */ 120 #define MXC_F_AES_CTRL_OUTPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_CTRL_OUTPUT_FLUSH_POS)) /**< CTRL_OUTPUT_FLUSH Mask */ 121 122 #define MXC_F_AES_CTRL_KEY_SIZE_POS 6 /**< CTRL_KEY_SIZE Position */ 123 #define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x3UL << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< CTRL_KEY_SIZE Mask */ 124 #define MXC_V_AES_CTRL_KEY_SIZE_AES128 ((uint32_t)0x0UL) /**< CTRL_KEY_SIZE_AES128 Value */ 125 #define MXC_S_AES_CTRL_KEY_SIZE_AES128 (MXC_V_AES_CTRL_KEY_SIZE_AES128 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES128 Setting */ 126 #define MXC_V_AES_CTRL_KEY_SIZE_AES192 ((uint32_t)0x1UL) /**< CTRL_KEY_SIZE_AES192 Value */ 127 #define MXC_S_AES_CTRL_KEY_SIZE_AES192 (MXC_V_AES_CTRL_KEY_SIZE_AES192 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES192 Setting */ 128 #define MXC_V_AES_CTRL_KEY_SIZE_AES256 ((uint32_t)0x2UL) /**< CTRL_KEY_SIZE_AES256 Value */ 129 #define MXC_S_AES_CTRL_KEY_SIZE_AES256 (MXC_V_AES_CTRL_KEY_SIZE_AES256 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES256 Setting */ 130 131 #define MXC_F_AES_CTRL_TYPE_POS 8 /**< CTRL_TYPE Position */ 132 #define MXC_F_AES_CTRL_TYPE ((uint32_t)(0x3UL << MXC_F_AES_CTRL_TYPE_POS)) /**< CTRL_TYPE Mask */ 133 134 /**@} end of group AES_CTRL_Register */ 135 136 /** 137 * @ingroup aes_registers 138 * @defgroup AES_STATUS AES_STATUS 139 * @brief AES Status Register 140 * @{ 141 */ 142 #define MXC_F_AES_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ 143 #define MXC_F_AES_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_AES_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ 144 145 #define MXC_F_AES_STATUS_INPUT_EM_POS 1 /**< STATUS_INPUT_EM Position */ 146 #define MXC_F_AES_STATUS_INPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_EM_POS)) /**< STATUS_INPUT_EM Mask */ 147 148 #define MXC_F_AES_STATUS_INPUT_FULL_POS 2 /**< STATUS_INPUT_FULL Position */ 149 #define MXC_F_AES_STATUS_INPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_FULL_POS)) /**< STATUS_INPUT_FULL Mask */ 150 151 #define MXC_F_AES_STATUS_OUTPUT_EM_POS 3 /**< STATUS_OUTPUT_EM Position */ 152 #define MXC_F_AES_STATUS_OUTPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_EM_POS)) /**< STATUS_OUTPUT_EM Mask */ 153 154 #define MXC_F_AES_STATUS_OUTPUT_FULL_POS 4 /**< STATUS_OUTPUT_FULL Position */ 155 #define MXC_F_AES_STATUS_OUTPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_FULL_POS)) /**< STATUS_OUTPUT_FULL Mask */ 156 157 /**@} end of group AES_STATUS_Register */ 158 159 /** 160 * @ingroup aes_registers 161 * @defgroup AES_INTFL AES_INTFL 162 * @brief AES Interrupt Flag Register 163 * @{ 164 */ 165 #define MXC_F_AES_INTFL_DONE_POS 0 /**< INTFL_DONE Position */ 166 #define MXC_F_AES_INTFL_DONE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_DONE_POS)) /**< INTFL_DONE Mask */ 167 168 #define MXC_F_AES_INTFL_KEY_CHANGE_POS 1 /**< INTFL_KEY_CHANGE Position */ 169 #define MXC_F_AES_INTFL_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_CHANGE_POS)) /**< INTFL_KEY_CHANGE Mask */ 170 171 #define MXC_F_AES_INTFL_KEY_ZERO_POS 2 /**< INTFL_KEY_ZERO Position */ 172 #define MXC_F_AES_INTFL_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_ZERO_POS)) /**< INTFL_KEY_ZERO Mask */ 173 174 #define MXC_F_AES_INTFL_OV_POS 3 /**< INTFL_OV Position */ 175 #define MXC_F_AES_INTFL_OV ((uint32_t)(0x1UL << MXC_F_AES_INTFL_OV_POS)) /**< INTFL_OV Mask */ 176 177 #define MXC_F_AES_INTFL_KEY_ONE_POS 4 /**< INTFL_KEY_ONE Position */ 178 #define MXC_F_AES_INTFL_KEY_ONE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_ONE_POS)) /**< INTFL_KEY_ONE Mask */ 179 180 /**@} end of group AES_INTFL_Register */ 181 182 /** 183 * @ingroup aes_registers 184 * @defgroup AES_INTEN AES_INTEN 185 * @brief AES Interrupt Enable Register 186 * @{ 187 */ 188 #define MXC_F_AES_INTEN_DONE_POS 0 /**< INTEN_DONE Position */ 189 #define MXC_F_AES_INTEN_DONE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_DONE_POS)) /**< INTEN_DONE Mask */ 190 191 #define MXC_F_AES_INTEN_KEY_CHANGE_POS 1 /**< INTEN_KEY_CHANGE Position */ 192 #define MXC_F_AES_INTEN_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_CHANGE_POS)) /**< INTEN_KEY_CHANGE Mask */ 193 194 #define MXC_F_AES_INTEN_KEY_ZERO_POS 2 /**< INTEN_KEY_ZERO Position */ 195 #define MXC_F_AES_INTEN_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ZERO_POS)) /**< INTEN_KEY_ZERO Mask */ 196 197 #define MXC_F_AES_INTEN_OV_POS 3 /**< INTEN_OV Position */ 198 #define MXC_F_AES_INTEN_OV ((uint32_t)(0x1UL << MXC_F_AES_INTEN_OV_POS)) /**< INTEN_OV Mask */ 199 200 #define MXC_F_AES_INTEN_KEY_ONE_POS 4 /**< INTEN_KEY_ONE Position */ 201 #define MXC_F_AES_INTEN_KEY_ONE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ONE_POS)) /**< INTEN_KEY_ONE Mask */ 202 203 /**@} end of group AES_INTEN_Register */ 204 205 /** 206 * @ingroup aes_registers 207 * @defgroup AES_FIFO AES_FIFO 208 * @brief AES Data Register 209 * @{ 210 */ 211 #define MXC_F_AES_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ 212 #define MXC_F_AES_FIFO_DATA ((uint32_t)(0x1UL << MXC_F_AES_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ 213 214 /**@} end of group AES_FIFO_Register */ 215 216 #ifdef __cplusplus 217 } 218 #endif 219 220 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_AES_REGS_H_ 221
