1 /** 2 * @file usbhs_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the USBHS Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup usbhs_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_USBHS_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_USBHS_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup usbhs 67 * @defgroup usbhs_registers USBHS_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the USBHS Peripheral Module. 69 * @details USB 2.0 High-speed Controller. 70 */ 71 72 /** 73 * @ingroup usbhs_registers 74 * Structure type to access the USBHS Registers. 75 */ 76 typedef struct { 77 __IO uint8_t faddr; /**< <tt>\b 0x00:</tt> USBHS FADDR Register */ 78 __IO uint8_t power; /**< <tt>\b 0x01:</tt> USBHS POWER Register */ 79 __IO uint16_t intrin; /**< <tt>\b 0x02:</tt> USBHS INTRIN Register */ 80 __IO uint16_t introut; /**< <tt>\b 0x04:</tt> USBHS INTROUT Register */ 81 __IO uint16_t intrinen; /**< <tt>\b 0x06:</tt> USBHS INTRINEN Register */ 82 __IO uint16_t introuten; /**< <tt>\b 0x08:</tt> USBHS INTROUTEN Register */ 83 __IO uint8_t intrusb; /**< <tt>\b 0x0A:</tt> USBHS INTRUSB Register */ 84 __IO uint8_t intrusben; /**< <tt>\b 0x0B:</tt> USBHS INTRUSBEN Register */ 85 __IO uint16_t frame; /**< <tt>\b 0x0C:</tt> USBHS FRAME Register */ 86 __IO uint8_t index; /**< <tt>\b 0x0E:</tt> USBHS INDEX Register */ 87 __IO uint8_t testmode; /**< <tt>\b 0x0F:</tt> USBHS TESTMODE Register */ 88 __IO uint16_t inmaxp; /**< <tt>\b 0x10:</tt> USBHS INMAXP Register */ 89 union { 90 __IO uint8_t csr0; /**< <tt>\b 0x12:</tt> USBHS CSR0 Register */ 91 __IO uint8_t incsrl; /**< <tt>\b 0x12:</tt> USBHS INCSRL Register */ 92 }; 93 __IO uint8_t incsru; /**< <tt>\b 0x13:</tt> USBHS INCSRU Register */ 94 __IO uint16_t outmaxp; /**< <tt>\b 0x14:</tt> USBHS OUTMAXP Register */ 95 __IO uint8_t outcsrl; /**< <tt>\b 0x16:</tt> USBHS OUTCSRL Register */ 96 __IO uint8_t outcsru; /**< <tt>\b 0x17:</tt> USBHS OUTCSRU Register */ 97 union { 98 __IO uint16_t count0; /**< <tt>\b 0x18:</tt> USBHS COUNT0 Register */ 99 __IO uint16_t outcount; /**< <tt>\b 0x18:</tt> USBHS OUTCOUNT Register */ 100 }; 101 __R uint16_t rsv_0x1a_0x1f[3]; 102 __IO uint32_t fifo0; /**< <tt>\b 0x20:</tt> USBHS FIFO0 Register */ 103 __IO uint32_t fifo1; /**< <tt>\b 0x24:</tt> USBHS FIFO1 Register */ 104 __IO uint32_t fifo2; /**< <tt>\b 0x28:</tt> USBHS FIFO2 Register */ 105 __IO uint32_t fifo3; /**< <tt>\b 0x2c:</tt> USBHS FIFO3 Register */ 106 __IO uint32_t fifo4; /**< <tt>\b 0x30:</tt> USBHS FIFO4 Register */ 107 __IO uint32_t fifo5; /**< <tt>\b 0x34:</tt> USBHS FIFO5 Register */ 108 __IO uint32_t fifo6; /**< <tt>\b 0x38:</tt> USBHS FIFO6 Register */ 109 __IO uint32_t fifo7; /**< <tt>\b 0x3c:</tt> USBHS FIFO7 Register */ 110 __IO uint32_t fifo8; /**< <tt>\b 0x40:</tt> USBHS FIFO8 Register */ 111 __IO uint32_t fifo9; /**< <tt>\b 0x44:</tt> USBHS FIFO9 Register */ 112 __IO uint32_t fifo10; /**< <tt>\b 0x48:</tt> USBHS FIFO10 Register */ 113 __IO uint32_t fifo11; /**< <tt>\b 0x4c:</tt> USBHS FIFO11 Register */ 114 __IO uint32_t fifo12; /**< <tt>\b 0x50:</tt> USBHS FIFO12 Register */ 115 __IO uint32_t fifo13; /**< <tt>\b 0x54:</tt> USBHS FIFO13 Register */ 116 __IO uint32_t fifo14; /**< <tt>\b 0x58:</tt> USBHS FIFO14 Register */ 117 __IO uint32_t fifo15; /**< <tt>\b 0x5c:</tt> USBHS FIFO15 Register */ 118 __R uint32_t rsv_0x60_0x6b[3]; 119 __IO uint16_t hwvers; /**< <tt>\b 0x6c:</tt> USBHS HWVERS Register */ 120 __R uint16_t rsv_0x6e_0x77[5]; 121 __IO uint8_t epinfo; /**< <tt>\b 0x78:</tt> USBHS EPINFO Register */ 122 __IO uint8_t raminfo; /**< <tt>\b 0x79:</tt> USBHS RAMINFO Register */ 123 __IO uint8_t softreset; /**< <tt>\b 0x7A:</tt> USBHS SOFTRESET Register */ 124 __R uint8_t rsv_0x7b_0x7f[5]; 125 __IO uint16_t ctuch; /**< <tt>\b 0x80:</tt> USBHS CTUCH Register */ 126 __IO uint16_t cthsrtn; /**< <tt>\b 0x82:</tt> USBHS CTHSRTN Register */ 127 __R uint32_t rsv_0x84_0x3ff[223]; 128 __IO uint32_t mxm_usb_reg_00; /**< <tt>\b 0x400:</tt> USBHS MXM_USB_REG_00 Register */ 129 __IO uint32_t m31_phy_utmi_reset; /**< <tt>\b 0x404:</tt> USBHS M31_PHY_UTMI_RESET Register */ 130 __IO uint32_t m31_phy_utmi_vcontrol; /**< <tt>\b 0x408:</tt> USBHS M31_PHY_UTMI_VCONTROL Register */ 131 __IO uint32_t m31_phy_clk_en; /**< <tt>\b 0x40C:</tt> USBHS M31_PHY_CLK_EN Register */ 132 __IO uint32_t m31_phy_ponrst; /**< <tt>\b 0x410:</tt> USBHS M31_PHY_PONRST Register */ 133 __IO uint32_t m31_phy_noncry_rstb; /**< <tt>\b 0x414:</tt> USBHS M31_PHY_NONCRY_RSTB Register */ 134 __IO uint32_t m31_phy_noncry_en; /**< <tt>\b 0x418:</tt> USBHS M31_PHY_NONCRY_EN Register */ 135 __R uint32_t rsv_0x41c; 136 __IO uint32_t m31_phy_u2_compliance_en; /**< <tt>\b 0x420:</tt> USBHS M31_PHY_U2_COMPLIANCE_EN Register */ 137 __IO uint32_t m31_phy_u2_compliance_dac_adj; /**< <tt>\b 0x424:</tt> USBHS M31_PHY_U2_COMPLIANCE_DAC_ADJ Register */ 138 __IO uint32_t m31_phy_u2_compliance_dac_adj_en; /**< <tt>\b 0x428:</tt> USBHS M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN Register */ 139 __IO uint32_t m31_phy_clk_rdy; /**< <tt>\b 0x42C:</tt> USBHS M31_PHY_CLK_RDY Register */ 140 __IO uint32_t m31_phy_pll_en; /**< <tt>\b 0x430:</tt> USBHS M31_PHY_PLL_EN Register */ 141 __IO uint32_t m31_phy_bist_ok; /**< <tt>\b 0x434:</tt> USBHS M31_PHY_BIST_OK Register */ 142 __IO uint32_t m31_phy_data_oe; /**< <tt>\b 0x438:</tt> USBHS M31_PHY_DATA_OE Register */ 143 __IO uint32_t m31_phy_oscouten; /**< <tt>\b 0x43C:</tt> USBHS M31_PHY_OSCOUTEN Register */ 144 __IO uint32_t m31_phy_lpm_alive; /**< <tt>\b 0x440:</tt> USBHS M31_PHY_LPM_ALIVE Register */ 145 __IO uint32_t m31_phy_hs_bist_mode; /**< <tt>\b 0x444:</tt> USBHS M31_PHY_HS_BIST_MODE Register */ 146 __IO uint32_t m31_phy_coreclkin; /**< <tt>\b 0x448:</tt> USBHS M31_PHY_CORECLKIN Register */ 147 __IO uint32_t m31_phy_xtlsel; /**< <tt>\b 0x44C:</tt> USBHS M31_PHY_XTLSEL Register */ 148 __IO uint32_t m31_phy_ls_en; /**< <tt>\b 0x450:</tt> USBHS M31_PHY_LS_EN Register */ 149 __IO uint32_t m31_phy_debug_sel; /**< <tt>\b 0x454:</tt> USBHS M31_PHY_DEBUG_SEL Register */ 150 __IO uint32_t m31_phy_debug_out; /**< <tt>\b 0x458:</tt> USBHS M31_PHY_DEBUG_OUT Register */ 151 __IO uint32_t m31_phy_outclksel; /**< <tt>\b 0x45C:</tt> USBHS M31_PHY_OUTCLKSEL Register */ 152 __IO uint32_t m31_phy_xcfgi_31_0; /**< <tt>\b 0x460:</tt> USBHS M31_PHY_XCFGI_31_0 Register */ 153 __IO uint32_t m31_phy_xcfgi_63_32; /**< <tt>\b 0x464:</tt> USBHS M31_PHY_XCFGI_63_32 Register */ 154 __IO uint32_t m31_phy_xcfgi_95_64; /**< <tt>\b 0x468:</tt> USBHS M31_PHY_XCFGI_95_64 Register */ 155 __IO uint32_t m31_phy_xcfgi_127_96; /**< <tt>\b 0x46C:</tt> USBHS M31_PHY_XCFGI_127_96 Register */ 156 __IO uint32_t m31_phy_xcfgi_137_128; /**< <tt>\b 0x470:</tt> USBHS M31_PHY_XCFGI_137_128 Register */ 157 __IO uint32_t m31_phy_xcfg_hs_coarse_tune_num; /**< <tt>\b 0x474:</tt> USBHS M31_PHY_XCFG_HS_COARSE_TUNE_NUM Register */ 158 __IO uint32_t m31_phy_xcfg_hs_fine_tune_num; /**< <tt>\b 0x478:</tt> USBHS M31_PHY_XCFG_HS_FINE_TUNE_NUM Register */ 159 __IO uint32_t m31_phy_xcfg_fs_coarse_tune_num; /**< <tt>\b 0x47C:</tt> USBHS M31_PHY_XCFG_FS_COARSE_TUNE_NUM Register */ 160 __IO uint32_t m31_phy_xcfg_fs_fine_tune_num; /**< <tt>\b 0x480:</tt> USBHS M31_PHY_XCFG_FS_FINE_TUNE_NUM Register */ 161 __IO uint32_t m31_phy_xcfg_lock_range_max; /**< <tt>\b 0x484:</tt> USBHS M31_PHY_XCFG_LOCK_RANGE_MAX Register */ 162 __IO uint32_t m31_phy_xcfgi_lock_range_min; /**< <tt>\b 0x488:</tt> USBHS M31_PHY_XCFGI_LOCK_RANGE_MIN Register */ 163 __IO uint32_t m31_phy_xcfg_ob_rsel; /**< <tt>\b 0x48C:</tt> USBHS M31_PHY_XCFG_OB_RSEL Register */ 164 __IO uint32_t m31_phy_xcfg_oc_rsel; /**< <tt>\b 0x490:</tt> USBHS M31_PHY_XCFG_OC_RSEL Register */ 165 __IO uint32_t m31_phy_xcfgo; /**< <tt>\b 0x494:</tt> USBHS M31_PHY_XCFGO Register */ 166 __IO uint32_t mxm_int; /**< <tt>\b 0x498:</tt> USBHS MXM_INT Register */ 167 __IO uint32_t mxm_int_en; /**< <tt>\b 0x49C:</tt> USBHS MXM_INT_EN Register */ 168 __IO uint32_t mxm_suspend; /**< <tt>\b 0x4A0:</tt> USBHS MXM_SUSPEND Register */ 169 __IO uint32_t mxm_reg_a4; /**< <tt>\b 0x4A4:</tt> USBHS MXM_REG_A4 Register */ 170 } mxc_usbhs_regs_t; 171 172 /* Register offsets for module USBHS */ 173 /** 174 * @ingroup usbhs_registers 175 * @defgroup USBHS_Register_Offsets Register Offsets 176 * @brief USBHS Peripheral Register Offsets from the USBHS Base Peripheral Address. 177 * @{ 178 */ 179 #define MXC_R_USBHS_FADDR ((uint32_t)0x00000000UL) /**< Offset from USBHS Base Address: <tt> 0x0000</tt> */ 180 #define MXC_R_USBHS_POWER ((uint32_t)0x00000001UL) /**< Offset from USBHS Base Address: <tt> 0x0001</tt> */ 181 #define MXC_R_USBHS_INTRIN ((uint32_t)0x00000002UL) /**< Offset from USBHS Base Address: <tt> 0x0002</tt> */ 182 #define MXC_R_USBHS_INTROUT ((uint32_t)0x00000004UL) /**< Offset from USBHS Base Address: <tt> 0x0004</tt> */ 183 #define MXC_R_USBHS_INTRINEN ((uint32_t)0x00000006UL) /**< Offset from USBHS Base Address: <tt> 0x0006</tt> */ 184 #define MXC_R_USBHS_INTROUTEN ((uint32_t)0x00000008UL) /**< Offset from USBHS Base Address: <tt> 0x0008</tt> */ 185 #define MXC_R_USBHS_INTRUSB ((uint32_t)0x0000000AUL) /**< Offset from USBHS Base Address: <tt> 0x000A</tt> */ 186 #define MXC_R_USBHS_INTRUSBEN ((uint32_t)0x0000000BUL) /**< Offset from USBHS Base Address: <tt> 0x000B</tt> */ 187 #define MXC_R_USBHS_FRAME ((uint32_t)0x0000000CUL) /**< Offset from USBHS Base Address: <tt> 0x000C</tt> */ 188 #define MXC_R_USBHS_INDEX ((uint32_t)0x0000000EUL) /**< Offset from USBHS Base Address: <tt> 0x000E</tt> */ 189 #define MXC_R_USBHS_TESTMODE ((uint32_t)0x0000000FUL) /**< Offset from USBHS Base Address: <tt> 0x000F</tt> */ 190 #define MXC_R_USBHS_INMAXP ((uint32_t)0x00000010UL) /**< Offset from USBHS Base Address: <tt> 0x0010</tt> */ 191 #define MXC_R_USBHS_CSR0 ((uint32_t)0x00000012UL) /**< Offset from USBHS Base Address: <tt> 0x0012</tt> */ 192 #define MXC_R_USBHS_INCSRL ((uint32_t)0x00000012UL) /**< Offset from USBHS Base Address: <tt> 0x0012</tt> */ 193 #define MXC_R_USBHS_INCSRU ((uint32_t)0x00000013UL) /**< Offset from USBHS Base Address: <tt> 0x0013</tt> */ 194 #define MXC_R_USBHS_OUTMAXP ((uint32_t)0x00000014UL) /**< Offset from USBHS Base Address: <tt> 0x0014</tt> */ 195 #define MXC_R_USBHS_OUTCSRL ((uint32_t)0x00000016UL) /**< Offset from USBHS Base Address: <tt> 0x0016</tt> */ 196 #define MXC_R_USBHS_OUTCSRU ((uint32_t)0x00000017UL) /**< Offset from USBHS Base Address: <tt> 0x0017</tt> */ 197 #define MXC_R_USBHS_COUNT0 ((uint32_t)0x00000018UL) /**< Offset from USBHS Base Address: <tt> 0x0018</tt> */ 198 #define MXC_R_USBHS_OUTCOUNT ((uint32_t)0x00000018UL) /**< Offset from USBHS Base Address: <tt> 0x0018</tt> */ 199 #define MXC_R_USBHS_FIFO0 ((uint32_t)0x00000020UL) /**< Offset from USBHS Base Address: <tt> 0x0020</tt> */ 200 #define MXC_R_USBHS_FIFO1 ((uint32_t)0x00000024UL) /**< Offset from USBHS Base Address: <tt> 0x0024</tt> */ 201 #define MXC_R_USBHS_FIFO2 ((uint32_t)0x00000028UL) /**< Offset from USBHS Base Address: <tt> 0x0028</tt> */ 202 #define MXC_R_USBHS_FIFO3 ((uint32_t)0x0000002CUL) /**< Offset from USBHS Base Address: <tt> 0x002C</tt> */ 203 #define MXC_R_USBHS_FIFO4 ((uint32_t)0x00000030UL) /**< Offset from USBHS Base Address: <tt> 0x0030</tt> */ 204 #define MXC_R_USBHS_FIFO5 ((uint32_t)0x00000034UL) /**< Offset from USBHS Base Address: <tt> 0x0034</tt> */ 205 #define MXC_R_USBHS_FIFO6 ((uint32_t)0x00000038UL) /**< Offset from USBHS Base Address: <tt> 0x0038</tt> */ 206 #define MXC_R_USBHS_FIFO7 ((uint32_t)0x0000003CUL) /**< Offset from USBHS Base Address: <tt> 0x003C</tt> */ 207 #define MXC_R_USBHS_FIFO8 ((uint32_t)0x00000040UL) /**< Offset from USBHS Base Address: <tt> 0x0040</tt> */ 208 #define MXC_R_USBHS_FIFO9 ((uint32_t)0x00000044UL) /**< Offset from USBHS Base Address: <tt> 0x0044</tt> */ 209 #define MXC_R_USBHS_FIFO10 ((uint32_t)0x00000048UL) /**< Offset from USBHS Base Address: <tt> 0x0048</tt> */ 210 #define MXC_R_USBHS_FIFO11 ((uint32_t)0x0000004CUL) /**< Offset from USBHS Base Address: <tt> 0x004C</tt> */ 211 #define MXC_R_USBHS_FIFO12 ((uint32_t)0x00000050UL) /**< Offset from USBHS Base Address: <tt> 0x0050</tt> */ 212 #define MXC_R_USBHS_FIFO13 ((uint32_t)0x00000054UL) /**< Offset from USBHS Base Address: <tt> 0x0054</tt> */ 213 #define MXC_R_USBHS_FIFO14 ((uint32_t)0x00000058UL) /**< Offset from USBHS Base Address: <tt> 0x0058</tt> */ 214 #define MXC_R_USBHS_FIFO15 ((uint32_t)0x0000005CUL) /**< Offset from USBHS Base Address: <tt> 0x005C</tt> */ 215 #define MXC_R_USBHS_HWVERS ((uint32_t)0x0000006CUL) /**< Offset from USBHS Base Address: <tt> 0x006C</tt> */ 216 #define MXC_R_USBHS_EPINFO ((uint32_t)0x00000078UL) /**< Offset from USBHS Base Address: <tt> 0x0078</tt> */ 217 #define MXC_R_USBHS_RAMINFO ((uint32_t)0x00000079UL) /**< Offset from USBHS Base Address: <tt> 0x0079</tt> */ 218 #define MXC_R_USBHS_SOFTRESET ((uint32_t)0x0000007AUL) /**< Offset from USBHS Base Address: <tt> 0x007A</tt> */ 219 #define MXC_R_USBHS_CTUCH ((uint32_t)0x00000080UL) /**< Offset from USBHS Base Address: <tt> 0x0080</tt> */ 220 #define MXC_R_USBHS_CTHSRTN ((uint32_t)0x00000082UL) /**< Offset from USBHS Base Address: <tt> 0x0082</tt> */ 221 #define MXC_R_USBHS_MXM_USB_REG_00 ((uint32_t)0x00000400UL) /**< Offset from USBHS Base Address: <tt> 0x0400</tt> */ 222 #define MXC_R_USBHS_M31_PHY_UTMI_RESET ((uint32_t)0x00000404UL) /**< Offset from USBHS Base Address: <tt> 0x0404</tt> */ 223 #define MXC_R_USBHS_M31_PHY_UTMI_VCONTROL ((uint32_t)0x00000408UL) /**< Offset from USBHS Base Address: <tt> 0x0408</tt> */ 224 #define MXC_R_USBHS_M31_PHY_CLK_EN ((uint32_t)0x0000040CUL) /**< Offset from USBHS Base Address: <tt> 0x040C</tt> */ 225 #define MXC_R_USBHS_M31_PHY_PONRST ((uint32_t)0x00000410UL) /**< Offset from USBHS Base Address: <tt> 0x0410</tt> */ 226 #define MXC_R_USBHS_M31_PHY_NONCRY_RSTB ((uint32_t)0x00000414UL) /**< Offset from USBHS Base Address: <tt> 0x0414</tt> */ 227 #define MXC_R_USBHS_M31_PHY_NONCRY_EN ((uint32_t)0x00000418UL) /**< Offset from USBHS Base Address: <tt> 0x0418</tt> */ 228 #define MXC_R_USBHS_M31_PHY_U2_COMPLIANCE_EN ((uint32_t)0x00000420UL) /**< Offset from USBHS Base Address: <tt> 0x0420</tt> */ 229 #define MXC_R_USBHS_M31_PHY_U2_COMPLIANCE_DAC_ADJ ((uint32_t)0x00000424UL) /**< Offset from USBHS Base Address: <tt> 0x0424</tt> */ 230 #define MXC_R_USBHS_M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN ((uint32_t)0x00000428UL) /**< Offset from USBHS Base Address: <tt> 0x0428</tt> */ 231 #define MXC_R_USBHS_M31_PHY_CLK_RDY ((uint32_t)0x0000042CUL) /**< Offset from USBHS Base Address: <tt> 0x042C</tt> */ 232 #define MXC_R_USBHS_M31_PHY_PLL_EN ((uint32_t)0x00000430UL) /**< Offset from USBHS Base Address: <tt> 0x0430</tt> */ 233 #define MXC_R_USBHS_M31_PHY_BIST_OK ((uint32_t)0x00000434UL) /**< Offset from USBHS Base Address: <tt> 0x0434</tt> */ 234 #define MXC_R_USBHS_M31_PHY_DATA_OE ((uint32_t)0x00000438UL) /**< Offset from USBHS Base Address: <tt> 0x0438</tt> */ 235 #define MXC_R_USBHS_M31_PHY_OSCOUTEN ((uint32_t)0x0000043CUL) /**< Offset from USBHS Base Address: <tt> 0x043C</tt> */ 236 #define MXC_R_USBHS_M31_PHY_LPM_ALIVE ((uint32_t)0x00000440UL) /**< Offset from USBHS Base Address: <tt> 0x0440</tt> */ 237 #define MXC_R_USBHS_M31_PHY_HS_BIST_MODE ((uint32_t)0x00000444UL) /**< Offset from USBHS Base Address: <tt> 0x0444</tt> */ 238 #define MXC_R_USBHS_M31_PHY_CORECLKIN ((uint32_t)0x00000448UL) /**< Offset from USBHS Base Address: <tt> 0x0448</tt> */ 239 #define MXC_R_USBHS_M31_PHY_XTLSEL ((uint32_t)0x0000044CUL) /**< Offset from USBHS Base Address: <tt> 0x044C</tt> */ 240 #define MXC_R_USBHS_M31_PHY_LS_EN ((uint32_t)0x00000450UL) /**< Offset from USBHS Base Address: <tt> 0x0450</tt> */ 241 #define MXC_R_USBHS_M31_PHY_DEBUG_SEL ((uint32_t)0x00000454UL) /**< Offset from USBHS Base Address: <tt> 0x0454</tt> */ 242 #define MXC_R_USBHS_M31_PHY_DEBUG_OUT ((uint32_t)0x00000458UL) /**< Offset from USBHS Base Address: <tt> 0x0458</tt> */ 243 #define MXC_R_USBHS_M31_PHY_OUTCLKSEL ((uint32_t)0x0000045CUL) /**< Offset from USBHS Base Address: <tt> 0x045C</tt> */ 244 #define MXC_R_USBHS_M31_PHY_XCFGI_31_0 ((uint32_t)0x00000460UL) /**< Offset from USBHS Base Address: <tt> 0x0460</tt> */ 245 #define MXC_R_USBHS_M31_PHY_XCFGI_63_32 ((uint32_t)0x00000464UL) /**< Offset from USBHS Base Address: <tt> 0x0464</tt> */ 246 #define MXC_R_USBHS_M31_PHY_XCFGI_95_64 ((uint32_t)0x00000468UL) /**< Offset from USBHS Base Address: <tt> 0x0468</tt> */ 247 #define MXC_R_USBHS_M31_PHY_XCFGI_127_96 ((uint32_t)0x0000046CUL) /**< Offset from USBHS Base Address: <tt> 0x046C</tt> */ 248 #define MXC_R_USBHS_M31_PHY_XCFGI_137_128 ((uint32_t)0x00000470UL) /**< Offset from USBHS Base Address: <tt> 0x0470</tt> */ 249 #define MXC_R_USBHS_M31_PHY_XCFG_HS_COARSE_TUNE_NUM ((uint32_t)0x00000474UL) /**< Offset from USBHS Base Address: <tt> 0x0474</tt> */ 250 #define MXC_R_USBHS_M31_PHY_XCFG_HS_FINE_TUNE_NUM ((uint32_t)0x00000478UL) /**< Offset from USBHS Base Address: <tt> 0x0478</tt> */ 251 #define MXC_R_USBHS_M31_PHY_XCFG_FS_COARSE_TUNE_NUM ((uint32_t)0x0000047CUL) /**< Offset from USBHS Base Address: <tt> 0x047C</tt> */ 252 #define MXC_R_USBHS_M31_PHY_XCFG_FS_FINE_TUNE_NUM ((uint32_t)0x00000480UL) /**< Offset from USBHS Base Address: <tt> 0x0480</tt> */ 253 #define MXC_R_USBHS_M31_PHY_XCFG_LOCK_RANGE_MAX ((uint32_t)0x00000484UL) /**< Offset from USBHS Base Address: <tt> 0x0484</tt> */ 254 #define MXC_R_USBHS_M31_PHY_XCFGI_LOCK_RANGE_MIN ((uint32_t)0x00000488UL) /**< Offset from USBHS Base Address: <tt> 0x0488</tt> */ 255 #define MXC_R_USBHS_M31_PHY_XCFG_OB_RSEL ((uint32_t)0x0000048CUL) /**< Offset from USBHS Base Address: <tt> 0x048C</tt> */ 256 #define MXC_R_USBHS_M31_PHY_XCFG_OC_RSEL ((uint32_t)0x00000490UL) /**< Offset from USBHS Base Address: <tt> 0x0490</tt> */ 257 #define MXC_R_USBHS_M31_PHY_XCFGO ((uint32_t)0x00000494UL) /**< Offset from USBHS Base Address: <tt> 0x0494</tt> */ 258 #define MXC_R_USBHS_MXM_INT ((uint32_t)0x00000498UL) /**< Offset from USBHS Base Address: <tt> 0x0498</tt> */ 259 #define MXC_R_USBHS_MXM_INT_EN ((uint32_t)0x0000049CUL) /**< Offset from USBHS Base Address: <tt> 0x049C</tt> */ 260 #define MXC_R_USBHS_MXM_SUSPEND ((uint32_t)0x000004A0UL) /**< Offset from USBHS Base Address: <tt> 0x04A0</tt> */ 261 #define MXC_R_USBHS_MXM_REG_A4 ((uint32_t)0x000004A4UL) /**< Offset from USBHS Base Address: <tt> 0x04A4</tt> */ 262 /**@} end of group usbhs_registers */ 263 264 /** 265 * @ingroup usbhs_registers 266 * @defgroup USBHS_FADDR USBHS_FADDR 267 * @brief Function address register. 268 * @{ 269 */ 270 #define MXC_F_USBHS_FADDR_ADDR_POS 0 /**< FADDR_ADDR Position */ 271 #define MXC_F_USBHS_FADDR_ADDR ((uint8_t)(0x7FUL << MXC_F_USBHS_FADDR_ADDR_POS)) /**< FADDR_ADDR Mask */ 272 273 #define MXC_F_USBHS_FADDR_UPDATE_POS 7 /**< FADDR_UPDATE Position */ 274 #define MXC_F_USBHS_FADDR_UPDATE ((uint8_t)(0x1UL << MXC_F_USBHS_FADDR_UPDATE_POS)) /**< FADDR_UPDATE Mask */ 275 276 /**@} end of group USBHS_FADDR_Register */ 277 278 /** 279 * @ingroup usbhs_registers 280 * @defgroup USBHS_POWER USBHS_POWER 281 * @brief Power management register. 282 * @{ 283 */ 284 #define MXC_F_USBHS_POWER_EN_SUSPENDM_POS 0 /**< POWER_EN_SUSPENDM Position */ 285 #define MXC_F_USBHS_POWER_EN_SUSPENDM ((uint8_t)(0x1UL << MXC_F_USBHS_POWER_EN_SUSPENDM_POS)) /**< POWER_EN_SUSPENDM Mask */ 286 287 #define MXC_F_USBHS_POWER_SUSPEND_POS 1 /**< POWER_SUSPEND Position */ 288 #define MXC_F_USBHS_POWER_SUSPEND ((uint8_t)(0x1UL << MXC_F_USBHS_POWER_SUSPEND_POS)) /**< POWER_SUSPEND Mask */ 289 290 #define MXC_F_USBHS_POWER_RESUME_POS 2 /**< POWER_RESUME Position */ 291 #define MXC_F_USBHS_POWER_RESUME ((uint8_t)(0x1UL << MXC_F_USBHS_POWER_RESUME_POS)) /**< POWER_RESUME Mask */ 292 293 #define MXC_F_USBHS_POWER_RESET_POS 3 /**< POWER_RESET Position */ 294 #define MXC_F_USBHS_POWER_RESET ((uint8_t)(0x1UL << MXC_F_USBHS_POWER_RESET_POS)) /**< POWER_RESET Mask */ 295 296 #define MXC_F_USBHS_POWER_HS_MODE_POS 4 /**< POWER_HS_MODE Position */ 297 #define MXC_F_USBHS_POWER_HS_MODE ((uint8_t)(0x1UL << MXC_F_USBHS_POWER_HS_MODE_POS)) /**< POWER_HS_MODE Mask */ 298 299 #define MXC_F_USBHS_POWER_HS_ENABLE_POS 5 /**< POWER_HS_ENABLE Position */ 300 #define MXC_F_USBHS_POWER_HS_ENABLE ((uint8_t)(0x1UL << MXC_F_USBHS_POWER_HS_ENABLE_POS)) /**< POWER_HS_ENABLE Mask */ 301 302 #define MXC_F_USBHS_POWER_SOFTCONN_POS 6 /**< POWER_SOFTCONN Position */ 303 #define MXC_F_USBHS_POWER_SOFTCONN ((uint8_t)(0x1UL << MXC_F_USBHS_POWER_SOFTCONN_POS)) /**< POWER_SOFTCONN Mask */ 304 305 #define MXC_F_USBHS_POWER_ISO_UPDATE_POS 7 /**< POWER_ISO_UPDATE Position */ 306 #define MXC_F_USBHS_POWER_ISO_UPDATE ((uint8_t)(0x1UL << MXC_F_USBHS_POWER_ISO_UPDATE_POS)) /**< POWER_ISO_UPDATE Mask */ 307 308 /**@} end of group USBHS_POWER_Register */ 309 310 /** 311 * @ingroup usbhs_registers 312 * @defgroup USBHS_INTRIN USBHS_INTRIN 313 * @brief Interrupt register for EP0 and IN EP1-15. 314 * @{ 315 */ 316 #define MXC_F_USBHS_INTRIN_EP15_IN_INT_POS 15 /**< INTRIN_EP15_IN_INT Position */ 317 #define MXC_F_USBHS_INTRIN_EP15_IN_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTRIN_EP15_IN_INT_POS)) /**< INTRIN_EP15_IN_INT Mask */ 318 319 #define MXC_F_USBHS_INTRIN_EP14_IN_INT_POS 14 /**< INTRIN_EP14_IN_INT Position */ 320 #define MXC_F_USBHS_INTRIN_EP14_IN_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTRIN_EP14_IN_INT_POS)) /**< INTRIN_EP14_IN_INT Mask */ 321 322 #define MXC_F_USBHS_INTRIN_EP13_IN_INT_POS 13 /**< INTRIN_EP13_IN_INT Position */ 323 #define MXC_F_USBHS_INTRIN_EP13_IN_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTRIN_EP13_IN_INT_POS)) /**< INTRIN_EP13_IN_INT Mask */ 324 325 #define MXC_F_USBHS_INTRIN_EP12_IN_INT_POS 12 /**< INTRIN_EP12_IN_INT Position */ 326 #define MXC_F_USBHS_INTRIN_EP12_IN_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTRIN_EP12_IN_INT_POS)) /**< INTRIN_EP12_IN_INT Mask */ 327 328 #define MXC_F_USBHS_INTRIN_EP11_IN_INT_POS 11 /**< INTRIN_EP11_IN_INT Position */ 329 #define MXC_F_USBHS_INTRIN_EP11_IN_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTRIN_EP11_IN_INT_POS)) /**< INTRIN_EP11_IN_INT Mask */ 330 331 #define MXC_F_USBHS_INTRIN_EP10_IN_INT_POS 10 /**< INTRIN_EP10_IN_INT Position */ 332 #define MXC_F_USBHS_INTRIN_EP10_IN_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTRIN_EP10_IN_INT_POS)) /**< INTRIN_EP10_IN_INT Mask */ 333 334 #define MXC_F_USBHS_INTRIN_EP9_IN_INT_POS 9 /**< INTRIN_EP9_IN_INT Position */ 335 #define MXC_F_USBHS_INTRIN_EP9_IN_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTRIN_EP9_IN_INT_POS)) /**< INTRIN_EP9_IN_INT Mask */ 336 337 #define MXC_F_USBHS_INTRIN_EP8_IN_INT_POS 8 /**< INTRIN_EP8_IN_INT Position */ 338 #define MXC_F_USBHS_INTRIN_EP8_IN_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTRIN_EP8_IN_INT_POS)) /**< INTRIN_EP8_IN_INT Mask */ 339 340 #define MXC_F_USBHS_INTRIN_EP7_IN_INT_POS 7 /**< INTRIN_EP7_IN_INT Position */ 341 #define MXC_F_USBHS_INTRIN_EP7_IN_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTRIN_EP7_IN_INT_POS)) /**< INTRIN_EP7_IN_INT Mask */ 342 343 #define MXC_F_USBHS_INTRIN_EP6_IN_INT_POS 6 /**< INTRIN_EP6_IN_INT Position */ 344 #define MXC_F_USBHS_INTRIN_EP6_IN_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTRIN_EP6_IN_INT_POS)) /**< INTRIN_EP6_IN_INT Mask */ 345 346 #define MXC_F_USBHS_INTRIN_EP5_IN_INT_POS 5 /**< INTRIN_EP5_IN_INT Position */ 347 #define MXC_F_USBHS_INTRIN_EP5_IN_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTRIN_EP5_IN_INT_POS)) /**< INTRIN_EP5_IN_INT Mask */ 348 349 #define MXC_F_USBHS_INTRIN_EP4_IN_INT_POS 4 /**< INTRIN_EP4_IN_INT Position */ 350 #define MXC_F_USBHS_INTRIN_EP4_IN_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTRIN_EP4_IN_INT_POS)) /**< INTRIN_EP4_IN_INT Mask */ 351 352 #define MXC_F_USBHS_INTRIN_EP3_IN_INT_POS 3 /**< INTRIN_EP3_IN_INT Position */ 353 #define MXC_F_USBHS_INTRIN_EP3_IN_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTRIN_EP3_IN_INT_POS)) /**< INTRIN_EP3_IN_INT Mask */ 354 355 #define MXC_F_USBHS_INTRIN_EP2_IN_INT_POS 2 /**< INTRIN_EP2_IN_INT Position */ 356 #define MXC_F_USBHS_INTRIN_EP2_IN_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTRIN_EP2_IN_INT_POS)) /**< INTRIN_EP2_IN_INT Mask */ 357 358 #define MXC_F_USBHS_INTRIN_EP1_IN_INT_POS 1 /**< INTRIN_EP1_IN_INT Position */ 359 #define MXC_F_USBHS_INTRIN_EP1_IN_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTRIN_EP1_IN_INT_POS)) /**< INTRIN_EP1_IN_INT Mask */ 360 361 #define MXC_F_USBHS_INTRIN_EP0_IN_INT_POS 0 /**< INTRIN_EP0_IN_INT Position */ 362 #define MXC_F_USBHS_INTRIN_EP0_IN_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTRIN_EP0_IN_INT_POS)) /**< INTRIN_EP0_IN_INT Mask */ 363 364 /**@} end of group USBHS_INTRIN_Register */ 365 366 /** 367 * @ingroup usbhs_registers 368 * @defgroup USBHS_INTROUT USBHS_INTROUT 369 * @brief Interrupt register for OUT EP 1-15. 370 * @{ 371 */ 372 #define MXC_F_USBHS_INTROUT_EP15_OUT_INT_POS 15 /**< INTROUT_EP15_OUT_INT Position */ 373 #define MXC_F_USBHS_INTROUT_EP15_OUT_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUT_EP15_OUT_INT_POS)) /**< INTROUT_EP15_OUT_INT Mask */ 374 375 #define MXC_F_USBHS_INTROUT_EP14_OUT_INT_POS 14 /**< INTROUT_EP14_OUT_INT Position */ 376 #define MXC_F_USBHS_INTROUT_EP14_OUT_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUT_EP14_OUT_INT_POS)) /**< INTROUT_EP14_OUT_INT Mask */ 377 378 #define MXC_F_USBHS_INTROUT_EP13_OUT_INT_POS 13 /**< INTROUT_EP13_OUT_INT Position */ 379 #define MXC_F_USBHS_INTROUT_EP13_OUT_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUT_EP13_OUT_INT_POS)) /**< INTROUT_EP13_OUT_INT Mask */ 380 381 #define MXC_F_USBHS_INTROUT_EP12_OUT_INT_POS 12 /**< INTROUT_EP12_OUT_INT Position */ 382 #define MXC_F_USBHS_INTROUT_EP12_OUT_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUT_EP12_OUT_INT_POS)) /**< INTROUT_EP12_OUT_INT Mask */ 383 384 #define MXC_F_USBHS_INTROUT_EP11_OUT_INT_POS 11 /**< INTROUT_EP11_OUT_INT Position */ 385 #define MXC_F_USBHS_INTROUT_EP11_OUT_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUT_EP11_OUT_INT_POS)) /**< INTROUT_EP11_OUT_INT Mask */ 386 387 #define MXC_F_USBHS_INTROUT_EP10_OUT_INT_POS 10 /**< INTROUT_EP10_OUT_INT Position */ 388 #define MXC_F_USBHS_INTROUT_EP10_OUT_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUT_EP10_OUT_INT_POS)) /**< INTROUT_EP10_OUT_INT Mask */ 389 390 #define MXC_F_USBHS_INTROUT_EP9_OUT_INT_POS 9 /**< INTROUT_EP9_OUT_INT Position */ 391 #define MXC_F_USBHS_INTROUT_EP9_OUT_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUT_EP9_OUT_INT_POS)) /**< INTROUT_EP9_OUT_INT Mask */ 392 393 #define MXC_F_USBHS_INTROUT_EP8_OUT_INT_POS 8 /**< INTROUT_EP8_OUT_INT Position */ 394 #define MXC_F_USBHS_INTROUT_EP8_OUT_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUT_EP8_OUT_INT_POS)) /**< INTROUT_EP8_OUT_INT Mask */ 395 396 #define MXC_F_USBHS_INTROUT_EP7_OUT_INT_POS 7 /**< INTROUT_EP7_OUT_INT Position */ 397 #define MXC_F_USBHS_INTROUT_EP7_OUT_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUT_EP7_OUT_INT_POS)) /**< INTROUT_EP7_OUT_INT Mask */ 398 399 #define MXC_F_USBHS_INTROUT_EP6_OUT_INT_POS 6 /**< INTROUT_EP6_OUT_INT Position */ 400 #define MXC_F_USBHS_INTROUT_EP6_OUT_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUT_EP6_OUT_INT_POS)) /**< INTROUT_EP6_OUT_INT Mask */ 401 402 #define MXC_F_USBHS_INTROUT_EP5_OUT_INT_POS 5 /**< INTROUT_EP5_OUT_INT Position */ 403 #define MXC_F_USBHS_INTROUT_EP5_OUT_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUT_EP5_OUT_INT_POS)) /**< INTROUT_EP5_OUT_INT Mask */ 404 405 #define MXC_F_USBHS_INTROUT_EP4_OUT_INT_POS 4 /**< INTROUT_EP4_OUT_INT Position */ 406 #define MXC_F_USBHS_INTROUT_EP4_OUT_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUT_EP4_OUT_INT_POS)) /**< INTROUT_EP4_OUT_INT Mask */ 407 408 #define MXC_F_USBHS_INTROUT_EP3_OUT_INT_POS 3 /**< INTROUT_EP3_OUT_INT Position */ 409 #define MXC_F_USBHS_INTROUT_EP3_OUT_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUT_EP3_OUT_INT_POS)) /**< INTROUT_EP3_OUT_INT Mask */ 410 411 #define MXC_F_USBHS_INTROUT_EP2_OUT_INT_POS 2 /**< INTROUT_EP2_OUT_INT Position */ 412 #define MXC_F_USBHS_INTROUT_EP2_OUT_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUT_EP2_OUT_INT_POS)) /**< INTROUT_EP2_OUT_INT Mask */ 413 414 #define MXC_F_USBHS_INTROUT_EP1_OUT_INT_POS 1 /**< INTROUT_EP1_OUT_INT Position */ 415 #define MXC_F_USBHS_INTROUT_EP1_OUT_INT ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUT_EP1_OUT_INT_POS)) /**< INTROUT_EP1_OUT_INT Mask */ 416 417 /**@} end of group USBHS_INTROUT_Register */ 418 419 /** 420 * @ingroup usbhs_registers 421 * @defgroup USBHS_INTRINEN USBHS_INTRINEN 422 * @brief Interrupt enable for EP 0 and IN EP 1-15. 423 * @{ 424 */ 425 #define MXC_F_USBHS_INTRINEN_EP15_IN_INT_EN_POS 15 /**< INTRINEN_EP15_IN_INT_EN Position */ 426 #define MXC_F_USBHS_INTRINEN_EP15_IN_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTRINEN_EP15_IN_INT_EN_POS)) /**< INTRINEN_EP15_IN_INT_EN Mask */ 427 428 #define MXC_F_USBHS_INTRINEN_EP14_IN_INT_EN_POS 14 /**< INTRINEN_EP14_IN_INT_EN Position */ 429 #define MXC_F_USBHS_INTRINEN_EP14_IN_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTRINEN_EP14_IN_INT_EN_POS)) /**< INTRINEN_EP14_IN_INT_EN Mask */ 430 431 #define MXC_F_USBHS_INTRINEN_EP13_IN_INT_EN_POS 13 /**< INTRINEN_EP13_IN_INT_EN Position */ 432 #define MXC_F_USBHS_INTRINEN_EP13_IN_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTRINEN_EP13_IN_INT_EN_POS)) /**< INTRINEN_EP13_IN_INT_EN Mask */ 433 434 #define MXC_F_USBHS_INTRINEN_EP12_IN_INT_EN_POS 12 /**< INTRINEN_EP12_IN_INT_EN Position */ 435 #define MXC_F_USBHS_INTRINEN_EP12_IN_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTRINEN_EP12_IN_INT_EN_POS)) /**< INTRINEN_EP12_IN_INT_EN Mask */ 436 437 #define MXC_F_USBHS_INTRINEN_EP11_IN_INT_EN_POS 11 /**< INTRINEN_EP11_IN_INT_EN Position */ 438 #define MXC_F_USBHS_INTRINEN_EP11_IN_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTRINEN_EP11_IN_INT_EN_POS)) /**< INTRINEN_EP11_IN_INT_EN Mask */ 439 440 #define MXC_F_USBHS_INTRINEN_EP10_IN_INT_EN_POS 10 /**< INTRINEN_EP10_IN_INT_EN Position */ 441 #define MXC_F_USBHS_INTRINEN_EP10_IN_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTRINEN_EP10_IN_INT_EN_POS)) /**< INTRINEN_EP10_IN_INT_EN Mask */ 442 443 #define MXC_F_USBHS_INTRINEN_EP9_IN_INT_EN_POS 9 /**< INTRINEN_EP9_IN_INT_EN Position */ 444 #define MXC_F_USBHS_INTRINEN_EP9_IN_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTRINEN_EP9_IN_INT_EN_POS)) /**< INTRINEN_EP9_IN_INT_EN Mask */ 445 446 #define MXC_F_USBHS_INTRINEN_EP8_IN_INT_EN_POS 8 /**< INTRINEN_EP8_IN_INT_EN Position */ 447 #define MXC_F_USBHS_INTRINEN_EP8_IN_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTRINEN_EP8_IN_INT_EN_POS)) /**< INTRINEN_EP8_IN_INT_EN Mask */ 448 449 #define MXC_F_USBHS_INTRINEN_EP7_IN_INT_EN_POS 7 /**< INTRINEN_EP7_IN_INT_EN Position */ 450 #define MXC_F_USBHS_INTRINEN_EP7_IN_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTRINEN_EP7_IN_INT_EN_POS)) /**< INTRINEN_EP7_IN_INT_EN Mask */ 451 452 #define MXC_F_USBHS_INTRINEN_EP6_IN_INT_EN_POS 6 /**< INTRINEN_EP6_IN_INT_EN Position */ 453 #define MXC_F_USBHS_INTRINEN_EP6_IN_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTRINEN_EP6_IN_INT_EN_POS)) /**< INTRINEN_EP6_IN_INT_EN Mask */ 454 455 #define MXC_F_USBHS_INTRINEN_EP5_IN_INT_EN_POS 5 /**< INTRINEN_EP5_IN_INT_EN Position */ 456 #define MXC_F_USBHS_INTRINEN_EP5_IN_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTRINEN_EP5_IN_INT_EN_POS)) /**< INTRINEN_EP5_IN_INT_EN Mask */ 457 458 #define MXC_F_USBHS_INTRINEN_EP4_IN_INT_EN_POS 4 /**< INTRINEN_EP4_IN_INT_EN Position */ 459 #define MXC_F_USBHS_INTRINEN_EP4_IN_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTRINEN_EP4_IN_INT_EN_POS)) /**< INTRINEN_EP4_IN_INT_EN Mask */ 460 461 #define MXC_F_USBHS_INTRINEN_EP3_IN_INT_EN_POS 3 /**< INTRINEN_EP3_IN_INT_EN Position */ 462 #define MXC_F_USBHS_INTRINEN_EP3_IN_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTRINEN_EP3_IN_INT_EN_POS)) /**< INTRINEN_EP3_IN_INT_EN Mask */ 463 464 #define MXC_F_USBHS_INTRINEN_EP2_IN_INT_EN_POS 2 /**< INTRINEN_EP2_IN_INT_EN Position */ 465 #define MXC_F_USBHS_INTRINEN_EP2_IN_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTRINEN_EP2_IN_INT_EN_POS)) /**< INTRINEN_EP2_IN_INT_EN Mask */ 466 467 #define MXC_F_USBHS_INTRINEN_EP1_IN_INT_EN_POS 1 /**< INTRINEN_EP1_IN_INT_EN Position */ 468 #define MXC_F_USBHS_INTRINEN_EP1_IN_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTRINEN_EP1_IN_INT_EN_POS)) /**< INTRINEN_EP1_IN_INT_EN Mask */ 469 470 #define MXC_F_USBHS_INTRINEN_EP0_INT_EN_POS 0 /**< INTRINEN_EP0_INT_EN Position */ 471 #define MXC_F_USBHS_INTRINEN_EP0_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTRINEN_EP0_INT_EN_POS)) /**< INTRINEN_EP0_INT_EN Mask */ 472 473 /**@} end of group USBHS_INTRINEN_Register */ 474 475 /** 476 * @ingroup usbhs_registers 477 * @defgroup USBHS_INTROUTEN USBHS_INTROUTEN 478 * @brief Interrupt enable for OUT EP 1-15. 479 * @{ 480 */ 481 #define MXC_F_USBHS_INTROUTEN_EP15_OUT_INT_EN_POS 15 /**< INTROUTEN_EP15_OUT_INT_EN Position */ 482 #define MXC_F_USBHS_INTROUTEN_EP15_OUT_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUTEN_EP15_OUT_INT_EN_POS)) /**< INTROUTEN_EP15_OUT_INT_EN Mask */ 483 484 #define MXC_F_USBHS_INTROUTEN_EP14_OUT_INT_EN_POS 14 /**< INTROUTEN_EP14_OUT_INT_EN Position */ 485 #define MXC_F_USBHS_INTROUTEN_EP14_OUT_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUTEN_EP14_OUT_INT_EN_POS)) /**< INTROUTEN_EP14_OUT_INT_EN Mask */ 486 487 #define MXC_F_USBHS_INTROUTEN_EP13_OUT_INT_EN_POS 13 /**< INTROUTEN_EP13_OUT_INT_EN Position */ 488 #define MXC_F_USBHS_INTROUTEN_EP13_OUT_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUTEN_EP13_OUT_INT_EN_POS)) /**< INTROUTEN_EP13_OUT_INT_EN Mask */ 489 490 #define MXC_F_USBHS_INTROUTEN_EP12_OUT_INT_EN_POS 12 /**< INTROUTEN_EP12_OUT_INT_EN Position */ 491 #define MXC_F_USBHS_INTROUTEN_EP12_OUT_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUTEN_EP12_OUT_INT_EN_POS)) /**< INTROUTEN_EP12_OUT_INT_EN Mask */ 492 493 #define MXC_F_USBHS_INTROUTEN_EP11_OUT_INT_EN_POS 11 /**< INTROUTEN_EP11_OUT_INT_EN Position */ 494 #define MXC_F_USBHS_INTROUTEN_EP11_OUT_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUTEN_EP11_OUT_INT_EN_POS)) /**< INTROUTEN_EP11_OUT_INT_EN Mask */ 495 496 #define MXC_F_USBHS_INTROUTEN_EP10_OUT_INT_EN_POS 10 /**< INTROUTEN_EP10_OUT_INT_EN Position */ 497 #define MXC_F_USBHS_INTROUTEN_EP10_OUT_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUTEN_EP10_OUT_INT_EN_POS)) /**< INTROUTEN_EP10_OUT_INT_EN Mask */ 498 499 #define MXC_F_USBHS_INTROUTEN_EP9_OUT_INT_EN_POS 9 /**< INTROUTEN_EP9_OUT_INT_EN Position */ 500 #define MXC_F_USBHS_INTROUTEN_EP9_OUT_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUTEN_EP9_OUT_INT_EN_POS)) /**< INTROUTEN_EP9_OUT_INT_EN Mask */ 501 502 #define MXC_F_USBHS_INTROUTEN_EP8_OUT_INT_EN_POS 8 /**< INTROUTEN_EP8_OUT_INT_EN Position */ 503 #define MXC_F_USBHS_INTROUTEN_EP8_OUT_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUTEN_EP8_OUT_INT_EN_POS)) /**< INTROUTEN_EP8_OUT_INT_EN Mask */ 504 505 #define MXC_F_USBHS_INTROUTEN_EP7_OUT_INT_EN_POS 7 /**< INTROUTEN_EP7_OUT_INT_EN Position */ 506 #define MXC_F_USBHS_INTROUTEN_EP7_OUT_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUTEN_EP7_OUT_INT_EN_POS)) /**< INTROUTEN_EP7_OUT_INT_EN Mask */ 507 508 #define MXC_F_USBHS_INTROUTEN_EP6_OUT_INT_EN_POS 6 /**< INTROUTEN_EP6_OUT_INT_EN Position */ 509 #define MXC_F_USBHS_INTROUTEN_EP6_OUT_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUTEN_EP6_OUT_INT_EN_POS)) /**< INTROUTEN_EP6_OUT_INT_EN Mask */ 510 511 #define MXC_F_USBHS_INTROUTEN_EP5_OUT_INT_EN_POS 5 /**< INTROUTEN_EP5_OUT_INT_EN Position */ 512 #define MXC_F_USBHS_INTROUTEN_EP5_OUT_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUTEN_EP5_OUT_INT_EN_POS)) /**< INTROUTEN_EP5_OUT_INT_EN Mask */ 513 514 #define MXC_F_USBHS_INTROUTEN_EP4_OUT_INT_EN_POS 4 /**< INTROUTEN_EP4_OUT_INT_EN Position */ 515 #define MXC_F_USBHS_INTROUTEN_EP4_OUT_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUTEN_EP4_OUT_INT_EN_POS)) /**< INTROUTEN_EP4_OUT_INT_EN Mask */ 516 517 #define MXC_F_USBHS_INTROUTEN_EP3_OUT_INT_EN_POS 3 /**< INTROUTEN_EP3_OUT_INT_EN Position */ 518 #define MXC_F_USBHS_INTROUTEN_EP3_OUT_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUTEN_EP3_OUT_INT_EN_POS)) /**< INTROUTEN_EP3_OUT_INT_EN Mask */ 519 520 #define MXC_F_USBHS_INTROUTEN_EP2_OUT_INT_EN_POS 2 /**< INTROUTEN_EP2_OUT_INT_EN Position */ 521 #define MXC_F_USBHS_INTROUTEN_EP2_OUT_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUTEN_EP2_OUT_INT_EN_POS)) /**< INTROUTEN_EP2_OUT_INT_EN Mask */ 522 523 #define MXC_F_USBHS_INTROUTEN_EP1_OUT_INT_EN_POS 1 /**< INTROUTEN_EP1_OUT_INT_EN Position */ 524 #define MXC_F_USBHS_INTROUTEN_EP1_OUT_INT_EN ((uint16_t)(0x1UL << MXC_F_USBHS_INTROUTEN_EP1_OUT_INT_EN_POS)) /**< INTROUTEN_EP1_OUT_INT_EN Mask */ 525 526 /**@} end of group USBHS_INTROUTEN_Register */ 527 528 /** 529 * @ingroup usbhs_registers 530 * @defgroup USBHS_INTRUSB USBHS_INTRUSB 531 * @brief Interrupt register for common USB interrupts. 532 * @{ 533 */ 534 #define MXC_F_USBHS_INTRUSB_SOF_INT_POS 3 /**< INTRUSB_SOF_INT Position */ 535 #define MXC_F_USBHS_INTRUSB_SOF_INT ((uint8_t)(0x1UL << MXC_F_USBHS_INTRUSB_SOF_INT_POS)) /**< INTRUSB_SOF_INT Mask */ 536 537 #define MXC_F_USBHS_INTRUSB_RESET_INT_POS 2 /**< INTRUSB_RESET_INT Position */ 538 #define MXC_F_USBHS_INTRUSB_RESET_INT ((uint8_t)(0x1UL << MXC_F_USBHS_INTRUSB_RESET_INT_POS)) /**< INTRUSB_RESET_INT Mask */ 539 540 #define MXC_F_USBHS_INTRUSB_RESUME_INT_POS 1 /**< INTRUSB_RESUME_INT Position */ 541 #define MXC_F_USBHS_INTRUSB_RESUME_INT ((uint8_t)(0x1UL << MXC_F_USBHS_INTRUSB_RESUME_INT_POS)) /**< INTRUSB_RESUME_INT Mask */ 542 543 #define MXC_F_USBHS_INTRUSB_SUSPEND_INT_POS 0 /**< INTRUSB_SUSPEND_INT Position */ 544 #define MXC_F_USBHS_INTRUSB_SUSPEND_INT ((uint8_t)(0x1UL << MXC_F_USBHS_INTRUSB_SUSPEND_INT_POS)) /**< INTRUSB_SUSPEND_INT Mask */ 545 546 /**@} end of group USBHS_INTRUSB_Register */ 547 548 /** 549 * @ingroup usbhs_registers 550 * @defgroup USBHS_INTRUSBEN USBHS_INTRUSBEN 551 * @brief Interrupt enable for common USB interrupts. 552 * @{ 553 */ 554 #define MXC_F_USBHS_INTRUSBEN_SOF_INT_EN_POS 3 /**< INTRUSBEN_SOF_INT_EN Position */ 555 #define MXC_F_USBHS_INTRUSBEN_SOF_INT_EN ((uint8_t)(0x1UL << MXC_F_USBHS_INTRUSBEN_SOF_INT_EN_POS)) /**< INTRUSBEN_SOF_INT_EN Mask */ 556 557 #define MXC_F_USBHS_INTRUSBEN_RESET_INT_EN_POS 2 /**< INTRUSBEN_RESET_INT_EN Position */ 558 #define MXC_F_USBHS_INTRUSBEN_RESET_INT_EN ((uint8_t)(0x1UL << MXC_F_USBHS_INTRUSBEN_RESET_INT_EN_POS)) /**< INTRUSBEN_RESET_INT_EN Mask */ 559 560 #define MXC_F_USBHS_INTRUSBEN_RESUME_INT_EN_POS 1 /**< INTRUSBEN_RESUME_INT_EN Position */ 561 #define MXC_F_USBHS_INTRUSBEN_RESUME_INT_EN ((uint8_t)(0x1UL << MXC_F_USBHS_INTRUSBEN_RESUME_INT_EN_POS)) /**< INTRUSBEN_RESUME_INT_EN Mask */ 562 563 #define MXC_F_USBHS_INTRUSBEN_SUSPEND_INT_EN_POS 0 /**< INTRUSBEN_SUSPEND_INT_EN Position */ 564 #define MXC_F_USBHS_INTRUSBEN_SUSPEND_INT_EN ((uint8_t)(0x1UL << MXC_F_USBHS_INTRUSBEN_SUSPEND_INT_EN_POS)) /**< INTRUSBEN_SUSPEND_INT_EN Mask */ 565 566 /**@} end of group USBHS_INTRUSBEN_Register */ 567 568 /** 569 * @ingroup usbhs_registers 570 * @defgroup USBHS_FRAME USBHS_FRAME 571 * @brief Frame number. 572 * @{ 573 */ 574 #define MXC_F_USBHS_FRAME_FRAMENUM_POS 0 /**< FRAME_FRAMENUM Position */ 575 #define MXC_F_USBHS_FRAME_FRAMENUM ((uint16_t)(0x7FFUL << MXC_F_USBHS_FRAME_FRAMENUM_POS)) /**< FRAME_FRAMENUM Mask */ 576 577 /**@} end of group USBHS_FRAME_Register */ 578 579 /** 580 * @ingroup usbhs_registers 581 * @defgroup USBHS_INDEX USBHS_INDEX 582 * @brief Index for banked registers. 583 * @{ 584 */ 585 #define MXC_F_USBHS_INDEX_INDEX_POS 0 /**< INDEX_INDEX Position */ 586 #define MXC_F_USBHS_INDEX_INDEX ((uint8_t)(0xFUL << MXC_F_USBHS_INDEX_INDEX_POS)) /**< INDEX_INDEX Mask */ 587 588 /**@} end of group USBHS_INDEX_Register */ 589 590 /** 591 * @ingroup usbhs_registers 592 * @defgroup USBHS_TESTMODE USBHS_TESTMODE 593 * @brief USB 2.0 test mode enable register. 594 * @{ 595 */ 596 #define MXC_F_USBHS_TESTMODE_FORCE_FS_POS 5 /**< TESTMODE_FORCE_FS Position */ 597 #define MXC_F_USBHS_TESTMODE_FORCE_FS ((uint8_t)(0x1UL << MXC_F_USBHS_TESTMODE_FORCE_FS_POS)) /**< TESTMODE_FORCE_FS Mask */ 598 599 #define MXC_F_USBHS_TESTMODE_FORCE_HS_POS 4 /**< TESTMODE_FORCE_HS Position */ 600 #define MXC_F_USBHS_TESTMODE_FORCE_HS ((uint8_t)(0x1UL << MXC_F_USBHS_TESTMODE_FORCE_HS_POS)) /**< TESTMODE_FORCE_HS Mask */ 601 602 #define MXC_F_USBHS_TESTMODE_TEST_PKT_POS 3 /**< TESTMODE_TEST_PKT Position */ 603 #define MXC_F_USBHS_TESTMODE_TEST_PKT ((uint8_t)(0x1UL << MXC_F_USBHS_TESTMODE_TEST_PKT_POS)) /**< TESTMODE_TEST_PKT Mask */ 604 605 #define MXC_F_USBHS_TESTMODE_TEST_K_POS 2 /**< TESTMODE_TEST_K Position */ 606 #define MXC_F_USBHS_TESTMODE_TEST_K ((uint8_t)(0x1UL << MXC_F_USBHS_TESTMODE_TEST_K_POS)) /**< TESTMODE_TEST_K Mask */ 607 608 #define MXC_F_USBHS_TESTMODE_TEST_J_POS 1 /**< TESTMODE_TEST_J Position */ 609 #define MXC_F_USBHS_TESTMODE_TEST_J ((uint8_t)(0x1UL << MXC_F_USBHS_TESTMODE_TEST_J_POS)) /**< TESTMODE_TEST_J Mask */ 610 611 #define MXC_F_USBHS_TESTMODE_TEST_SE0_NAK_POS 0 /**< TESTMODE_TEST_SE0_NAK Position */ 612 #define MXC_F_USBHS_TESTMODE_TEST_SE0_NAK ((uint8_t)(0x1UL << MXC_F_USBHS_TESTMODE_TEST_SE0_NAK_POS)) /**< TESTMODE_TEST_SE0_NAK Mask */ 613 614 /**@} end of group USBHS_TESTMODE_Register */ 615 616 /** 617 * @ingroup usbhs_registers 618 * @defgroup USBHS_INMAXP USBHS_INMAXP 619 * @brief Maximum packet size for INx endpoint (x == INDEX). 620 * @{ 621 */ 622 #define MXC_F_USBHS_INMAXP_MAXPACKETSIZE_POS 0 /**< INMAXP_MAXPACKETSIZE Position */ 623 #define MXC_F_USBHS_INMAXP_MAXPACKETSIZE ((uint16_t)(0x7FFUL << MXC_F_USBHS_INMAXP_MAXPACKETSIZE_POS)) /**< INMAXP_MAXPACKETSIZE Mask */ 624 625 #define MXC_F_USBHS_INMAXP_NUMPACKMINUS1_POS 11 /**< INMAXP_NUMPACKMINUS1 Position */ 626 #define MXC_F_USBHS_INMAXP_NUMPACKMINUS1 ((uint16_t)(0x1FUL << MXC_F_USBHS_INMAXP_NUMPACKMINUS1_POS)) /**< INMAXP_NUMPACKMINUS1 Mask */ 627 628 /**@} end of group USBHS_INMAXP_Register */ 629 630 /** 631 * @ingroup usbhs_registers 632 * @defgroup USBHS_CSR0 USBHS_CSR0 633 * @brief Control status register for EP 0 (when INDEX == 0). 634 * @{ 635 */ 636 #define MXC_F_USBHS_CSR0_SERV_SETUP_END_POS 7 /**< CSR0_SERV_SETUP_END Position */ 637 #define MXC_F_USBHS_CSR0_SERV_SETUP_END ((uint8_t)(0x1UL << MXC_F_USBHS_CSR0_SERV_SETUP_END_POS)) /**< CSR0_SERV_SETUP_END Mask */ 638 639 #define MXC_F_USBHS_CSR0_SERV_OUTPKTRDY_POS 6 /**< CSR0_SERV_OUTPKTRDY Position */ 640 #define MXC_F_USBHS_CSR0_SERV_OUTPKTRDY ((uint8_t)(0x1UL << MXC_F_USBHS_CSR0_SERV_OUTPKTRDY_POS)) /**< CSR0_SERV_OUTPKTRDY Mask */ 641 642 #define MXC_F_USBHS_CSR0_SEND_STALL_POS 5 /**< CSR0_SEND_STALL Position */ 643 #define MXC_F_USBHS_CSR0_SEND_STALL ((uint8_t)(0x1UL << MXC_F_USBHS_CSR0_SEND_STALL_POS)) /**< CSR0_SEND_STALL Mask */ 644 645 #define MXC_F_USBHS_CSR0_SETUP_END_POS 4 /**< CSR0_SETUP_END Position */ 646 #define MXC_F_USBHS_CSR0_SETUP_END ((uint8_t)(0x1UL << MXC_F_USBHS_CSR0_SETUP_END_POS)) /**< CSR0_SETUP_END Mask */ 647 648 #define MXC_F_USBHS_CSR0_DATA_END_POS 3 /**< CSR0_DATA_END Position */ 649 #define MXC_F_USBHS_CSR0_DATA_END ((uint8_t)(0x1UL << MXC_F_USBHS_CSR0_DATA_END_POS)) /**< CSR0_DATA_END Mask */ 650 651 #define MXC_F_USBHS_CSR0_SENT_STALL_POS 2 /**< CSR0_SENT_STALL Position */ 652 #define MXC_F_USBHS_CSR0_SENT_STALL ((uint8_t)(0x1UL << MXC_F_USBHS_CSR0_SENT_STALL_POS)) /**< CSR0_SENT_STALL Mask */ 653 654 #define MXC_F_USBHS_CSR0_INPKTRDY_POS 1 /**< CSR0_INPKTRDY Position */ 655 #define MXC_F_USBHS_CSR0_INPKTRDY ((uint8_t)(0x1UL << MXC_F_USBHS_CSR0_INPKTRDY_POS)) /**< CSR0_INPKTRDY Mask */ 656 657 #define MXC_F_USBHS_CSR0_OUTPKTRDY_POS 0 /**< CSR0_OUTPKTRDY Position */ 658 #define MXC_F_USBHS_CSR0_OUTPKTRDY ((uint8_t)(0x1UL << MXC_F_USBHS_CSR0_OUTPKTRDY_POS)) /**< CSR0_OUTPKTRDY Mask */ 659 660 /**@} end of group USBHS_CSR0_Register */ 661 662 /** 663 * @ingroup usbhs_registers 664 * @defgroup USBHS_INCSRL USBHS_INCSRL 665 * @brief Control status lower register for INx endpoint (x == INDEX). 666 * @{ 667 */ 668 #define MXC_F_USBHS_INCSRL_INCOMPTX_POS 7 /**< INCSRL_INCOMPTX Position */ 669 #define MXC_F_USBHS_INCSRL_INCOMPTX ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_INCOMPTX_POS)) /**< INCSRL_INCOMPTX Mask */ 670 671 #define MXC_F_USBHS_INCSRL_CLRDATATOG_POS 6 /**< INCSRL_CLRDATATOG Position */ 672 #define MXC_F_USBHS_INCSRL_CLRDATATOG ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_CLRDATATOG_POS)) /**< INCSRL_CLRDATATOG Mask */ 673 674 #define MXC_F_USBHS_INCSRL_SENTSTALL_POS 5 /**< INCSRL_SENTSTALL Position */ 675 #define MXC_F_USBHS_INCSRL_SENTSTALL ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_SENTSTALL_POS)) /**< INCSRL_SENTSTALL Mask */ 676 677 #define MXC_F_USBHS_INCSRL_SENDSTALL_POS 4 /**< INCSRL_SENDSTALL Position */ 678 #define MXC_F_USBHS_INCSRL_SENDSTALL ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_SENDSTALL_POS)) /**< INCSRL_SENDSTALL Mask */ 679 #define MXC_V_USBHS_INCSRL_SENDSTALL_TERMINATE ((uint8_t)0x0UL) /**< INCSRL_SENDSTALL_TERMINATE Value */ 680 #define MXC_S_USBHS_INCSRL_SENDSTALL_TERMINATE (MXC_V_USBHS_INCSRL_SENDSTALL_TERMINATE << MXC_F_USBHS_INCSRL_SENDSTALL_POS) /**< INCSRL_SENDSTALL_TERMINATE Setting */ 681 #define MXC_V_USBHS_INCSRL_SENDSTALL_RESPOND ((uint8_t)0x1UL) /**< INCSRL_SENDSTALL_RESPOND Value */ 682 #define MXC_S_USBHS_INCSRL_SENDSTALL_RESPOND (MXC_V_USBHS_INCSRL_SENDSTALL_RESPOND << MXC_F_USBHS_INCSRL_SENDSTALL_POS) /**< INCSRL_SENDSTALL_RESPOND Setting */ 683 684 #define MXC_F_USBHS_INCSRL_FLUSHFIFO_POS 3 /**< INCSRL_FLUSHFIFO Position */ 685 #define MXC_F_USBHS_INCSRL_FLUSHFIFO ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_FLUSHFIFO_POS)) /**< INCSRL_FLUSHFIFO Mask */ 686 687 #define MXC_F_USBHS_INCSRL_UNDERRUN_POS 2 /**< INCSRL_UNDERRUN Position */ 688 #define MXC_F_USBHS_INCSRL_UNDERRUN ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_UNDERRUN_POS)) /**< INCSRL_UNDERRUN Mask */ 689 690 #define MXC_F_USBHS_INCSRL_FIFONOTEMPTY_POS 1 /**< INCSRL_FIFONOTEMPTY Position */ 691 #define MXC_F_USBHS_INCSRL_FIFONOTEMPTY ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_FIFONOTEMPTY_POS)) /**< INCSRL_FIFONOTEMPTY Mask */ 692 693 #define MXC_F_USBHS_INCSRL_INPKTRDY_POS 0 /**< INCSRL_INPKTRDY Position */ 694 #define MXC_F_USBHS_INCSRL_INPKTRDY ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRL_INPKTRDY_POS)) /**< INCSRL_INPKTRDY Mask */ 695 696 /**@} end of group USBHS_INCSRL_Register */ 697 698 /** 699 * @ingroup usbhs_registers 700 * @defgroup USBHS_INCSRU USBHS_INCSRU 701 * @brief Control status upper register for INx endpoint (x == INDEX). 702 * @{ 703 */ 704 #define MXC_F_USBHS_INCSRU_AUTOSET_POS 7 /**< INCSRU_AUTOSET Position */ 705 #define MXC_F_USBHS_INCSRU_AUTOSET ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRU_AUTOSET_POS)) /**< INCSRU_AUTOSET Mask */ 706 #define MXC_V_USBHS_INCSRU_AUTOSET_SET ((uint8_t)0x0UL) /**< INCSRU_AUTOSET_SET Value */ 707 #define MXC_S_USBHS_INCSRU_AUTOSET_SET (MXC_V_USBHS_INCSRU_AUTOSET_SET << MXC_F_USBHS_INCSRU_AUTOSET_POS) /**< INCSRU_AUTOSET_SET Setting */ 708 #define MXC_V_USBHS_INCSRU_AUTOSET_AUTO ((uint8_t)0x1UL) /**< INCSRU_AUTOSET_AUTO Value */ 709 #define MXC_S_USBHS_INCSRU_AUTOSET_AUTO (MXC_V_USBHS_INCSRU_AUTOSET_AUTO << MXC_F_USBHS_INCSRU_AUTOSET_POS) /**< INCSRU_AUTOSET_AUTO Setting */ 710 711 #define MXC_F_USBHS_INCSRU_ISO_POS 6 /**< INCSRU_ISO Position */ 712 #define MXC_F_USBHS_INCSRU_ISO ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRU_ISO_POS)) /**< INCSRU_ISO Mask */ 713 #define MXC_V_USBHS_INCSRU_ISO_INTERRUPT ((uint8_t)0x0UL) /**< INCSRU_ISO_INTERRUPT Value */ 714 #define MXC_S_USBHS_INCSRU_ISO_INTERRUPT (MXC_V_USBHS_INCSRU_ISO_INTERRUPT << MXC_F_USBHS_INCSRU_ISO_POS) /**< INCSRU_ISO_INTERRUPT Setting */ 715 #define MXC_V_USBHS_INCSRU_ISO_ISOCHRONOUS ((uint8_t)0x1UL) /**< INCSRU_ISO_ISOCHRONOUS Value */ 716 #define MXC_S_USBHS_INCSRU_ISO_ISOCHRONOUS (MXC_V_USBHS_INCSRU_ISO_ISOCHRONOUS << MXC_F_USBHS_INCSRU_ISO_POS) /**< INCSRU_ISO_ISOCHRONOUS Setting */ 717 718 #define MXC_F_USBHS_INCSRU_MODE_POS 5 /**< INCSRU_MODE Position */ 719 #define MXC_F_USBHS_INCSRU_MODE ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRU_MODE_POS)) /**< INCSRU_MODE Mask */ 720 #define MXC_V_USBHS_INCSRU_MODE_OUT ((uint8_t)0x0UL) /**< INCSRU_MODE_OUT Value */ 721 #define MXC_S_USBHS_INCSRU_MODE_OUT (MXC_V_USBHS_INCSRU_MODE_OUT << MXC_F_USBHS_INCSRU_MODE_POS) /**< INCSRU_MODE_OUT Setting */ 722 #define MXC_V_USBHS_INCSRU_MODE_IN ((uint8_t)0x1UL) /**< INCSRU_MODE_IN Value */ 723 #define MXC_S_USBHS_INCSRU_MODE_IN (MXC_V_USBHS_INCSRU_MODE_IN << MXC_F_USBHS_INCSRU_MODE_POS) /**< INCSRU_MODE_IN Setting */ 724 725 #define MXC_F_USBHS_INCSRU_FRCDATATOG_POS 3 /**< INCSRU_FRCDATATOG Position */ 726 #define MXC_F_USBHS_INCSRU_FRCDATATOG ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRU_FRCDATATOG_POS)) /**< INCSRU_FRCDATATOG Mask */ 727 #define MXC_V_USBHS_INCSRU_FRCDATATOG_RECEIVED ((uint8_t)0x0UL) /**< INCSRU_FRCDATATOG_RECEIVED Value */ 728 #define MXC_S_USBHS_INCSRU_FRCDATATOG_RECEIVED (MXC_V_USBHS_INCSRU_FRCDATATOG_RECEIVED << MXC_F_USBHS_INCSRU_FRCDATATOG_POS) /**< INCSRU_FRCDATATOG_RECEIVED Setting */ 729 #define MXC_V_USBHS_INCSRU_FRCDATATOG_DONTCARE ((uint8_t)0x1UL) /**< INCSRU_FRCDATATOG_DONTCARE Value */ 730 #define MXC_S_USBHS_INCSRU_FRCDATATOG_DONTCARE (MXC_V_USBHS_INCSRU_FRCDATATOG_DONTCARE << MXC_F_USBHS_INCSRU_FRCDATATOG_POS) /**< INCSRU_FRCDATATOG_DONTCARE Setting */ 731 732 #define MXC_F_USBHS_INCSRU_DPKTBUFDIS_POS 1 /**< INCSRU_DPKTBUFDIS Position */ 733 #define MXC_F_USBHS_INCSRU_DPKTBUFDIS ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRU_DPKTBUFDIS_POS)) /**< INCSRU_DPKTBUFDIS Mask */ 734 #define MXC_V_USBHS_INCSRU_DPKTBUFDIS_EN ((uint8_t)0x0UL) /**< INCSRU_DPKTBUFDIS_EN Value */ 735 #define MXC_S_USBHS_INCSRU_DPKTBUFDIS_EN (MXC_V_USBHS_INCSRU_DPKTBUFDIS_EN << MXC_F_USBHS_INCSRU_DPKTBUFDIS_POS) /**< INCSRU_DPKTBUFDIS_EN Setting */ 736 #define MXC_V_USBHS_INCSRU_DPKTBUFDIS_DIS ((uint8_t)0x1UL) /**< INCSRU_DPKTBUFDIS_DIS Value */ 737 #define MXC_S_USBHS_INCSRU_DPKTBUFDIS_DIS (MXC_V_USBHS_INCSRU_DPKTBUFDIS_DIS << MXC_F_USBHS_INCSRU_DPKTBUFDIS_POS) /**< INCSRU_DPKTBUFDIS_DIS Setting */ 738 739 /**@} end of group USBHS_INCSRU_Register */ 740 741 /** 742 * @ingroup usbhs_registers 743 * @defgroup USBHS_OUTMAXP USBHS_OUTMAXP 744 * @brief Maximum packet size for OUTx endpoint (x == INDEX). 745 * @{ 746 */ 747 #define MXC_F_USBHS_OUTMAXP_NUMPACKMINUS1_POS 11 /**< OUTMAXP_NUMPACKMINUS1 Position */ 748 #define MXC_F_USBHS_OUTMAXP_NUMPACKMINUS1 ((uint16_t)(0x1FUL << MXC_F_USBHS_OUTMAXP_NUMPACKMINUS1_POS)) /**< OUTMAXP_NUMPACKMINUS1 Mask */ 749 750 #define MXC_F_USBHS_OUTMAXP_MAXPACKETSIZE_POS 0 /**< OUTMAXP_MAXPACKETSIZE Position */ 751 #define MXC_F_USBHS_OUTMAXP_MAXPACKETSIZE ((uint16_t)(0x7FFUL << MXC_F_USBHS_OUTMAXP_MAXPACKETSIZE_POS)) /**< OUTMAXP_MAXPACKETSIZE Mask */ 752 753 /**@} end of group USBHS_OUTMAXP_Register */ 754 755 /** 756 * @ingroup usbhs_registers 757 * @defgroup USBHS_OUTCSRL USBHS_OUTCSRL 758 * @brief Control status lower register for OUTx endpoint (x == INDEX). 759 * @{ 760 */ 761 #define MXC_F_USBHS_OUTCSRL_CLRDATATOG_POS 7 /**< OUTCSRL_CLRDATATOG Position */ 762 #define MXC_F_USBHS_OUTCSRL_CLRDATATOG ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_CLRDATATOG_POS)) /**< OUTCSRL_CLRDATATOG Mask */ 763 764 #define MXC_F_USBHS_OUTCSRL_SENTSTALL_POS 6 /**< OUTCSRL_SENTSTALL Position */ 765 #define MXC_F_USBHS_OUTCSRL_SENTSTALL ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_SENTSTALL_POS)) /**< OUTCSRL_SENTSTALL Mask */ 766 767 #define MXC_F_USBHS_OUTCSRL_SENDSTALL_POS 5 /**< OUTCSRL_SENDSTALL Position */ 768 #define MXC_F_USBHS_OUTCSRL_SENDSTALL ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_SENDSTALL_POS)) /**< OUTCSRL_SENDSTALL Mask */ 769 770 #define MXC_F_USBHS_OUTCSRL_FLUSHFIFO_POS 4 /**< OUTCSRL_FLUSHFIFO Position */ 771 #define MXC_F_USBHS_OUTCSRL_FLUSHFIFO ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_FLUSHFIFO_POS)) /**< OUTCSRL_FLUSHFIFO Mask */ 772 773 #define MXC_F_USBHS_OUTCSRL_DATAERROR_POS 3 /**< OUTCSRL_DATAERROR Position */ 774 #define MXC_F_USBHS_OUTCSRL_DATAERROR ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_DATAERROR_POS)) /**< OUTCSRL_DATAERROR Mask */ 775 776 #define MXC_F_USBHS_OUTCSRL_OVERRUN_POS 2 /**< OUTCSRL_OVERRUN Position */ 777 #define MXC_F_USBHS_OUTCSRL_OVERRUN ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_OVERRUN_POS)) /**< OUTCSRL_OVERRUN Mask */ 778 779 #define MXC_F_USBHS_OUTCSRL_FIFOFULL_POS 1 /**< OUTCSRL_FIFOFULL Position */ 780 #define MXC_F_USBHS_OUTCSRL_FIFOFULL ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_FIFOFULL_POS)) /**< OUTCSRL_FIFOFULL Mask */ 781 782 #define MXC_F_USBHS_OUTCSRL_OUTPKTRDY_POS 0 /**< OUTCSRL_OUTPKTRDY Position */ 783 #define MXC_F_USBHS_OUTCSRL_OUTPKTRDY ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRL_OUTPKTRDY_POS)) /**< OUTCSRL_OUTPKTRDY Mask */ 784 785 /**@} end of group USBHS_OUTCSRL_Register */ 786 787 /** 788 * @ingroup usbhs_registers 789 * @defgroup USBHS_OUTCSRU USBHS_OUTCSRU 790 * @brief Control status upper register for OUTx endpoint (x == INDEX). 791 * @{ 792 */ 793 #define MXC_F_USBHS_OUTCSRU_AUTOCLEAR_POS 7 /**< OUTCSRU_AUTOCLEAR Position */ 794 #define MXC_F_USBHS_OUTCSRU_AUTOCLEAR ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRU_AUTOCLEAR_POS)) /**< OUTCSRU_AUTOCLEAR Mask */ 795 796 #define MXC_F_USBHS_OUTCSRU_ISO_POS 6 /**< OUTCSRU_ISO Position */ 797 #define MXC_F_USBHS_OUTCSRU_ISO ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRU_ISO_POS)) /**< OUTCSRU_ISO Mask */ 798 799 #define MXC_F_USBHS_OUTCSRU_DISNYET_POS 4 /**< OUTCSRU_DISNYET Position */ 800 #define MXC_F_USBHS_OUTCSRU_DISNYET ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRU_DISNYET_POS)) /**< OUTCSRU_DISNYET Mask */ 801 802 #define MXC_F_USBHS_OUTCSRU_DPKTBUFDIS_POS 1 /**< OUTCSRU_DPKTBUFDIS Position */ 803 #define MXC_F_USBHS_OUTCSRU_DPKTBUFDIS ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRU_DPKTBUFDIS_POS)) /**< OUTCSRU_DPKTBUFDIS Mask */ 804 805 #define MXC_F_USBHS_OUTCSRU_INCOMPRX_POS 0 /**< OUTCSRU_INCOMPRX Position */ 806 #define MXC_F_USBHS_OUTCSRU_INCOMPRX ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRU_INCOMPRX_POS)) /**< OUTCSRU_INCOMPRX Mask */ 807 808 /**@} end of group USBHS_OUTCSRU_Register */ 809 810 /** 811 * @ingroup usbhs_registers 812 * @defgroup USBHS_COUNT0 USBHS_COUNT0 813 * @brief Number of received bytes in EP 0 FIFO (INDEX == 0). 814 * @{ 815 */ 816 #define MXC_F_USBHS_COUNT0_COUNT0_POS 0 /**< COUNT0_COUNT0 Position */ 817 #define MXC_F_USBHS_COUNT0_COUNT0 ((uint16_t)(0x7FUL << MXC_F_USBHS_COUNT0_COUNT0_POS)) /**< COUNT0_COUNT0 Mask */ 818 819 /**@} end of group USBHS_COUNT0_Register */ 820 821 /** 822 * @ingroup usbhs_registers 823 * @defgroup USBHS_OUTCOUNT USBHS_OUTCOUNT 824 * @brief Number of received bytes in OUT EPx FIFO (x == INDEX). 825 * @{ 826 */ 827 #define MXC_F_USBHS_OUTCOUNT_OUTCOUNT_POS 0 /**< OUTCOUNT_OUTCOUNT Position */ 828 #define MXC_F_USBHS_OUTCOUNT_OUTCOUNT ((uint16_t)(0x1FFFUL << MXC_F_USBHS_OUTCOUNT_OUTCOUNT_POS)) /**< OUTCOUNT_OUTCOUNT Mask */ 829 830 /**@} end of group USBHS_OUTCOUNT_Register */ 831 832 /** 833 * @ingroup usbhs_registers 834 * @defgroup USBHS_FIFO0 USBHS_FIFO0 835 * @brief Read for OUT data FIFO, write for IN data FIFO. 836 * @{ 837 */ 838 #define MXC_F_USBHS_FIFO0_USBHS_FIFO0_POS 0 /**< FIFO0_USBHS_FIFO0 Position */ 839 #define MXC_F_USBHS_FIFO0_USBHS_FIFO0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_USBHS_FIFO0_USBHS_FIFO0_POS)) /**< FIFO0_USBHS_FIFO0 Mask */ 840 841 /**@} end of group USBHS_FIFO0_Register */ 842 843 /** 844 * @ingroup usbhs_registers 845 * @defgroup USBHS_FIFO1 USBHS_FIFO1 846 * @brief Read for OUT data FIFO, write for IN data FIFO. 847 * @{ 848 */ 849 #define MXC_F_USBHS_FIFO1_USBHS_FIFO1_POS 0 /**< FIFO1_USBHS_FIFO1 Position */ 850 #define MXC_F_USBHS_FIFO1_USBHS_FIFO1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_USBHS_FIFO1_USBHS_FIFO1_POS)) /**< FIFO1_USBHS_FIFO1 Mask */ 851 852 /**@} end of group USBHS_FIFO1_Register */ 853 854 /** 855 * @ingroup usbhs_registers 856 * @defgroup USBHS_FIFO2 USBHS_FIFO2 857 * @brief Read for OUT data FIFO, write for IN data FIFO. 858 * @{ 859 */ 860 #define MXC_F_USBHS_FIFO2_USBHS_FIFO2_POS 0 /**< FIFO2_USBHS_FIFO2 Position */ 861 #define MXC_F_USBHS_FIFO2_USBHS_FIFO2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_USBHS_FIFO2_USBHS_FIFO2_POS)) /**< FIFO2_USBHS_FIFO2 Mask */ 862 863 /**@} end of group USBHS_FIFO2_Register */ 864 865 /** 866 * @ingroup usbhs_registers 867 * @defgroup USBHS_FIFO3 USBHS_FIFO3 868 * @brief Read for OUT data FIFO, write for IN data FIFO. 869 * @{ 870 */ 871 #define MXC_F_USBHS_FIFO3_USBHS_FIFO3_POS 0 /**< FIFO3_USBHS_FIFO3 Position */ 872 #define MXC_F_USBHS_FIFO3_USBHS_FIFO3 ((uint32_t)(0xFFFFFFFFUL << MXC_F_USBHS_FIFO3_USBHS_FIFO3_POS)) /**< FIFO3_USBHS_FIFO3 Mask */ 873 874 /**@} end of group USBHS_FIFO3_Register */ 875 876 /** 877 * @ingroup usbhs_registers 878 * @defgroup USBHS_FIFO4 USBHS_FIFO4 879 * @brief Read for OUT data FIFO, write for IN data FIFO. 880 * @{ 881 */ 882 #define MXC_F_USBHS_FIFO4_USBHS_FIFO4_POS 0 /**< FIFO4_USBHS_FIFO4 Position */ 883 #define MXC_F_USBHS_FIFO4_USBHS_FIFO4 ((uint32_t)(0xFFFFFFFFUL << MXC_F_USBHS_FIFO4_USBHS_FIFO4_POS)) /**< FIFO4_USBHS_FIFO4 Mask */ 884 885 /**@} end of group USBHS_FIFO4_Register */ 886 887 /** 888 * @ingroup usbhs_registers 889 * @defgroup USBHS_FIFO5 USBHS_FIFO5 890 * @brief Read for OUT data FIFO, write for IN data FIFO. 891 * @{ 892 */ 893 #define MXC_F_USBHS_FIFO5_USBHS_FIFO5_POS 0 /**< FIFO5_USBHS_FIFO5 Position */ 894 #define MXC_F_USBHS_FIFO5_USBHS_FIFO5 ((uint32_t)(0xFFFFFFFFUL << MXC_F_USBHS_FIFO5_USBHS_FIFO5_POS)) /**< FIFO5_USBHS_FIFO5 Mask */ 895 896 /**@} end of group USBHS_FIFO5_Register */ 897 898 /** 899 * @ingroup usbhs_registers 900 * @defgroup USBHS_FIFO6 USBHS_FIFO6 901 * @brief Read for OUT data FIFO, write for IN data FIFO. 902 * @{ 903 */ 904 #define MXC_F_USBHS_FIFO6_USBHS_FIFO6_POS 0 /**< FIFO6_USBHS_FIFO6 Position */ 905 #define MXC_F_USBHS_FIFO6_USBHS_FIFO6 ((uint32_t)(0xFFFFFFFFUL << MXC_F_USBHS_FIFO6_USBHS_FIFO6_POS)) /**< FIFO6_USBHS_FIFO6 Mask */ 906 907 /**@} end of group USBHS_FIFO6_Register */ 908 909 /** 910 * @ingroup usbhs_registers 911 * @defgroup USBHS_FIFO7 USBHS_FIFO7 912 * @brief Read for OUT data FIFO, write for IN data FIFO. 913 * @{ 914 */ 915 #define MXC_F_USBHS_FIFO7_USBHS_FIFO7_POS 0 /**< FIFO7_USBHS_FIFO7 Position */ 916 #define MXC_F_USBHS_FIFO7_USBHS_FIFO7 ((uint32_t)(0xFFFFFFFFUL << MXC_F_USBHS_FIFO7_USBHS_FIFO7_POS)) /**< FIFO7_USBHS_FIFO7 Mask */ 917 918 /**@} end of group USBHS_FIFO7_Register */ 919 920 /** 921 * @ingroup usbhs_registers 922 * @defgroup USBHS_FIFO8 USBHS_FIFO8 923 * @brief Read for OUT data FIFO, write for IN data FIFO. 924 * @{ 925 */ 926 #define MXC_F_USBHS_FIFO8_USBHS_FIFO8_POS 0 /**< FIFO8_USBHS_FIFO8 Position */ 927 #define MXC_F_USBHS_FIFO8_USBHS_FIFO8 ((uint32_t)(0xFFFFFFFFUL << MXC_F_USBHS_FIFO8_USBHS_FIFO8_POS)) /**< FIFO8_USBHS_FIFO8 Mask */ 928 929 /**@} end of group USBHS_FIFO8_Register */ 930 931 /** 932 * @ingroup usbhs_registers 933 * @defgroup USBHS_FIFO9 USBHS_FIFO9 934 * @brief Read for OUT data FIFO, write for IN data FIFO. 935 * @{ 936 */ 937 #define MXC_F_USBHS_FIFO9_USBHS_FIFO9_POS 0 /**< FIFO9_USBHS_FIFO9 Position */ 938 #define MXC_F_USBHS_FIFO9_USBHS_FIFO9 ((uint32_t)(0xFFFFFFFFUL << MXC_F_USBHS_FIFO9_USBHS_FIFO9_POS)) /**< FIFO9_USBHS_FIFO9 Mask */ 939 940 /**@} end of group USBHS_FIFO9_Register */ 941 942 /** 943 * @ingroup usbhs_registers 944 * @defgroup USBHS_FIFO10 USBHS_FIFO10 945 * @brief Read for OUT data FIFO, write for IN data FIFO. 946 * @{ 947 */ 948 #define MXC_F_USBHS_FIFO10_USBHS_FIFO10_POS 0 /**< FIFO10_USBHS_FIFO10 Position */ 949 #define MXC_F_USBHS_FIFO10_USBHS_FIFO10 ((uint32_t)(0xFFFFFFFFUL << MXC_F_USBHS_FIFO10_USBHS_FIFO10_POS)) /**< FIFO10_USBHS_FIFO10 Mask */ 950 951 /**@} end of group USBHS_FIFO10_Register */ 952 953 /** 954 * @ingroup usbhs_registers 955 * @defgroup USBHS_FIFO11 USBHS_FIFO11 956 * @brief Read for OUT data FIFO, write for IN data FIFO. 957 * @{ 958 */ 959 #define MXC_F_USBHS_FIFO11_USBHS_FIFO11_POS 0 /**< FIFO11_USBHS_FIFO11 Position */ 960 #define MXC_F_USBHS_FIFO11_USBHS_FIFO11 ((uint32_t)(0xFFFFFFFFUL << MXC_F_USBHS_FIFO11_USBHS_FIFO11_POS)) /**< FIFO11_USBHS_FIFO11 Mask */ 961 962 /**@} end of group USBHS_FIFO11_Register */ 963 964 /** 965 * @ingroup usbhs_registers 966 * @defgroup USBHS_FIFO12 USBHS_FIFO12 967 * @brief Read for OUT data FIFO, write for IN data FIFO. 968 * @{ 969 */ 970 #define MXC_F_USBHS_FIFO12_USBHS_FIFO12_POS 0 /**< FIFO12_USBHS_FIFO12 Position */ 971 #define MXC_F_USBHS_FIFO12_USBHS_FIFO12 ((uint32_t)(0xFFFFFFFFUL << MXC_F_USBHS_FIFO12_USBHS_FIFO12_POS)) /**< FIFO12_USBHS_FIFO12 Mask */ 972 973 /**@} end of group USBHS_FIFO12_Register */ 974 975 /** 976 * @ingroup usbhs_registers 977 * @defgroup USBHS_FIFO13 USBHS_FIFO13 978 * @brief Read for OUT data FIFO, write for IN data FIFO. 979 * @{ 980 */ 981 #define MXC_F_USBHS_FIFO13_USBHS_FIFO13_POS 0 /**< FIFO13_USBHS_FIFO13 Position */ 982 #define MXC_F_USBHS_FIFO13_USBHS_FIFO13 ((uint32_t)(0xFFFFFFFFUL << MXC_F_USBHS_FIFO13_USBHS_FIFO13_POS)) /**< FIFO13_USBHS_FIFO13 Mask */ 983 984 /**@} end of group USBHS_FIFO13_Register */ 985 986 /** 987 * @ingroup usbhs_registers 988 * @defgroup USBHS_FIFO14 USBHS_FIFO14 989 * @brief Read for OUT data FIFO, write for IN data FIFO. 990 * @{ 991 */ 992 #define MXC_F_USBHS_FIFO14_USBHS_FIFO14_POS 0 /**< FIFO14_USBHS_FIFO14 Position */ 993 #define MXC_F_USBHS_FIFO14_USBHS_FIFO14 ((uint32_t)(0xFFFFFFFFUL << MXC_F_USBHS_FIFO14_USBHS_FIFO14_POS)) /**< FIFO14_USBHS_FIFO14 Mask */ 994 995 /**@} end of group USBHS_FIFO14_Register */ 996 997 /** 998 * @ingroup usbhs_registers 999 * @defgroup USBHS_FIFO15 USBHS_FIFO15 1000 * @brief Read for OUT data FIFO, write for IN data FIFO. 1001 * @{ 1002 */ 1003 #define MXC_F_USBHS_FIFO15_USBHS_FIFO15_POS 0 /**< FIFO15_USBHS_FIFO15 Position */ 1004 #define MXC_F_USBHS_FIFO15_USBHS_FIFO15 ((uint32_t)(0xFFFFFFFFUL << MXC_F_USBHS_FIFO15_USBHS_FIFO15_POS)) /**< FIFO15_USBHS_FIFO15 Mask */ 1005 1006 /**@} end of group USBHS_FIFO15_Register */ 1007 1008 /** 1009 * @ingroup usbhs_registers 1010 * @defgroup USBHS_HWVERS USBHS_HWVERS 1011 * @brief HWVERS 1012 * @{ 1013 */ 1014 #define MXC_F_USBHS_HWVERS_USBHS_HWVERS_POS 0 /**< HWVERS_USBHS_HWVERS Position */ 1015 #define MXC_F_USBHS_HWVERS_USBHS_HWVERS ((uint16_t)(0xFFFFUL << MXC_F_USBHS_HWVERS_USBHS_HWVERS_POS)) /**< HWVERS_USBHS_HWVERS Mask */ 1016 1017 /**@} end of group USBHS_HWVERS_Register */ 1018 1019 /** 1020 * @ingroup usbhs_registers 1021 * @defgroup USBHS_EPINFO USBHS_EPINFO 1022 * @brief Endpoint hardware information. 1023 * @{ 1024 */ 1025 #define MXC_F_USBHS_EPINFO_OUTENDPOINTS_POS 4 /**< EPINFO_OUTENDPOINTS Position */ 1026 #define MXC_F_USBHS_EPINFO_OUTENDPOINTS ((uint8_t)(0xFUL << MXC_F_USBHS_EPINFO_OUTENDPOINTS_POS)) /**< EPINFO_OUTENDPOINTS Mask */ 1027 1028 #define MXC_F_USBHS_EPINFO_INTENDPOINTS_POS 0 /**< EPINFO_INTENDPOINTS Position */ 1029 #define MXC_F_USBHS_EPINFO_INTENDPOINTS ((uint8_t)(0xFUL << MXC_F_USBHS_EPINFO_INTENDPOINTS_POS)) /**< EPINFO_INTENDPOINTS Mask */ 1030 1031 /**@} end of group USBHS_EPINFO_Register */ 1032 1033 /** 1034 * @ingroup usbhs_registers 1035 * @defgroup USBHS_RAMINFO USBHS_RAMINFO 1036 * @brief RAM width information. 1037 * @{ 1038 */ 1039 #define MXC_F_USBHS_RAMINFO_RAMBITS_POS 0 /**< RAMINFO_RAMBITS Position */ 1040 #define MXC_F_USBHS_RAMINFO_RAMBITS ((uint8_t)(0xFUL << MXC_F_USBHS_RAMINFO_RAMBITS_POS)) /**< RAMINFO_RAMBITS Mask */ 1041 1042 /**@} end of group USBHS_RAMINFO_Register */ 1043 1044 /** 1045 * @ingroup usbhs_registers 1046 * @defgroup USBHS_SOFTRESET USBHS_SOFTRESET 1047 * @brief Software reset register. 1048 * @{ 1049 */ 1050 #define MXC_F_USBHS_SOFTRESET_RSTXS_POS 1 /**< SOFTRESET_RSTXS Position */ 1051 #define MXC_F_USBHS_SOFTRESET_RSTXS ((uint8_t)(0x1UL << MXC_F_USBHS_SOFTRESET_RSTXS_POS)) /**< SOFTRESET_RSTXS Mask */ 1052 1053 #define MXC_F_USBHS_SOFTRESET_RSTS_POS 0 /**< SOFTRESET_RSTS Position */ 1054 #define MXC_F_USBHS_SOFTRESET_RSTS ((uint8_t)(0x1UL << MXC_F_USBHS_SOFTRESET_RSTS_POS)) /**< SOFTRESET_RSTS Mask */ 1055 1056 /**@} end of group USBHS_SOFTRESET_Register */ 1057 1058 /** 1059 * @ingroup usbhs_registers 1060 * @defgroup USBHS_CTUCH USBHS_CTUCH 1061 * @brief Chirp timeout timer setting. 1062 * @{ 1063 */ 1064 #define MXC_F_USBHS_CTUCH_C_T_UCH_POS 0 /**< CTUCH_C_T_UCH Position */ 1065 #define MXC_F_USBHS_CTUCH_C_T_UCH ((uint16_t)(0xFFFFUL << MXC_F_USBHS_CTUCH_C_T_UCH_POS)) /**< CTUCH_C_T_UCH Mask */ 1066 1067 /**@} end of group USBHS_CTUCH_Register */ 1068 1069 /** 1070 * @ingroup usbhs_registers 1071 * @defgroup USBHS_CTHSRTN USBHS_CTHSRTN 1072 * @brief Sets delay between HS resume to UTM normal operating mode. 1073 * @{ 1074 */ 1075 #define MXC_F_USBHS_CTHSRTN_C_T_HSTRN_POS 0 /**< CTHSRTN_C_T_HSTRN Position */ 1076 #define MXC_F_USBHS_CTHSRTN_C_T_HSTRN ((uint16_t)(0xFFFFUL << MXC_F_USBHS_CTHSRTN_C_T_HSTRN_POS)) /**< CTHSRTN_C_T_HSTRN Mask */ 1077 1078 /**@} end of group USBHS_CTHSRTN_Register */ 1079 1080 /** 1081 * @ingroup usbhs_registers 1082 * @defgroup USBHS_MXM_INT USBHS_MXM_INT 1083 * @brief USB Added Maxim Interrupt Flag Register. 1084 * @{ 1085 */ 1086 #define MXC_F_USBHS_MXM_INT_VBUS_POS 0 /**< MXM_INT_VBUS Position */ 1087 #define MXC_F_USBHS_MXM_INT_VBUS ((uint32_t)(0x1UL << MXC_F_USBHS_MXM_INT_VBUS_POS)) /**< MXM_INT_VBUS Mask */ 1088 1089 #define MXC_F_USBHS_MXM_INT_NOVBUS_POS 1 /**< MXM_INT_NOVBUS Position */ 1090 #define MXC_F_USBHS_MXM_INT_NOVBUS ((uint32_t)(0x1UL << MXC_F_USBHS_MXM_INT_NOVBUS_POS)) /**< MXM_INT_NOVBUS Mask */ 1091 1092 /**@} end of group USBHS_MXM_INT_Register */ 1093 1094 /** 1095 * @ingroup usbhs_registers 1096 * @defgroup USBHS_MXM_INT_EN USBHS_MXM_INT_EN 1097 * @brief USB Added Maxim Interrupt Enable Register. 1098 * @{ 1099 */ 1100 #define MXC_F_USBHS_MXM_INT_EN_VBUS_POS 0 /**< MXM_INT_EN_VBUS Position */ 1101 #define MXC_F_USBHS_MXM_INT_EN_VBUS ((uint32_t)(0x1UL << MXC_F_USBHS_MXM_INT_EN_VBUS_POS)) /**< MXM_INT_EN_VBUS Mask */ 1102 1103 #define MXC_F_USBHS_MXM_INT_EN_NOVBUS_POS 1 /**< MXM_INT_EN_NOVBUS Position */ 1104 #define MXC_F_USBHS_MXM_INT_EN_NOVBUS ((uint32_t)(0x1UL << MXC_F_USBHS_MXM_INT_EN_NOVBUS_POS)) /**< MXM_INT_EN_NOVBUS Mask */ 1105 1106 /**@} end of group USBHS_MXM_INT_EN_Register */ 1107 1108 /** 1109 * @ingroup usbhs_registers 1110 * @defgroup USBHS_MXM_SUSPEND USBHS_MXM_SUSPEND 1111 * @brief USB Added Maxim Suspend Register. 1112 * @{ 1113 */ 1114 #define MXC_F_USBHS_MXM_SUSPEND_SEL_POS 0 /**< MXM_SUSPEND_SEL Position */ 1115 #define MXC_F_USBHS_MXM_SUSPEND_SEL ((uint32_t)(0x1UL << MXC_F_USBHS_MXM_SUSPEND_SEL_POS)) /**< MXM_SUSPEND_SEL Mask */ 1116 1117 /**@} end of group USBHS_MXM_SUSPEND_Register */ 1118 1119 /** 1120 * @ingroup usbhs_registers 1121 * @defgroup USBHS_MXM_REG_A4 USBHS_MXM_REG_A4 1122 * @brief USB Added Maxim Power Status Register 1123 * @{ 1124 */ 1125 #define MXC_F_USBHS_MXM_REG_A4_VRST_VDDB_N_A_POS 0 /**< MXM_REG_A4_VRST_VDDB_N_A Position */ 1126 #define MXC_F_USBHS_MXM_REG_A4_VRST_VDDB_N_A ((uint32_t)(0x1UL << MXC_F_USBHS_MXM_REG_A4_VRST_VDDB_N_A_POS)) /**< MXM_REG_A4_VRST_VDDB_N_A Mask */ 1127 1128 /**@} end of group USBHS_MXM_REG_A4_Register */ 1129 1130 #ifdef __cplusplus 1131 } 1132 #endif 1133 1134 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_USBHS_REGS_H_ 1135
