1 /** 2 * @file uart_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup uart_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2025 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_UART_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_UART_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup uart 67 * @defgroup uart_registers UART_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. 69 * @details UART 70 */ 71 72 /** 73 * @ingroup uart_registers 74 * Structure type to access the UART Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl0; /**< <tt>\b 0x00:</tt> UART CTRL0 Register */ 78 __IO uint32_t ctrl1; /**< <tt>\b 0x04:</tt> UART CTRL1 Register */ 79 __I uint32_t stat; /**< <tt>\b 0x08:</tt> UART STAT Register */ 80 __IO uint32_t int_en; /**< <tt>\b 0x0C:</tt> UART INT_EN Register */ 81 __IO uint32_t int_fl; /**< <tt>\b 0x10:</tt> UART INT_FL Register */ 82 __IO uint32_t baud0; /**< <tt>\b 0x14:</tt> UART BAUD0 Register */ 83 __IO uint32_t baud1; /**< <tt>\b 0x18:</tt> UART BAUD1 Register */ 84 __IO uint32_t fifo; /**< <tt>\b 0x1C:</tt> UART FIFO Register */ 85 __IO uint32_t dma; /**< <tt>\b 0x20:</tt> UART DMA Register */ 86 __IO uint32_t txfifo; /**< <tt>\b 0x24:</tt> UART TXFIFO Register */ 87 } mxc_uart_regs_t; 88 89 /* Register offsets for module UART */ 90 /** 91 * @ingroup uart_registers 92 * @defgroup UART_Register_Offsets Register Offsets 93 * @brief UART Peripheral Register Offsets from the UART Base Peripheral Address. 94 * @{ 95 */ 96 #define MXC_R_UART_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: <tt> 0x0000</tt> */ 97 #define MXC_R_UART_CTRL1 ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: <tt> 0x0004</tt> */ 98 #define MXC_R_UART_STAT ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: <tt> 0x0008</tt> */ 99 #define MXC_R_UART_INT_EN ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: <tt> 0x000C</tt> */ 100 #define MXC_R_UART_INT_FL ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt> 0x0010</tt> */ 101 #define MXC_R_UART_BAUD0 ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt> 0x0014</tt> */ 102 #define MXC_R_UART_BAUD1 ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: <tt> 0x0018</tt> */ 103 #define MXC_R_UART_FIFO ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: <tt> 0x001C</tt> */ 104 #define MXC_R_UART_DMA ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt> 0x0020</tt> */ 105 #define MXC_R_UART_TXFIFO ((uint32_t)0x00000024UL) /**< Offset from UART Base Address: <tt> 0x0024</tt> */ 106 /**@} end of group uart_registers */ 107 108 /** 109 * @ingroup uart_registers 110 * @defgroup UART_CTRL0 UART_CTRL0 111 * @brief Control Register. 112 * @{ 113 */ 114 #define MXC_F_UART_CTRL0_ENABLE_POS 0 /**< CTRL0_ENABLE Position */ 115 #define MXC_F_UART_CTRL0_ENABLE ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_ENABLE_POS)) /**< CTRL0_ENABLE Mask */ 116 #define MXC_V_UART_CTRL0_ENABLE_DIS ((uint32_t)0x0UL) /**< CTRL0_ENABLE_DIS Value */ 117 #define MXC_S_UART_CTRL0_ENABLE_DIS (MXC_V_UART_CTRL0_ENABLE_DIS << MXC_F_UART_CTRL0_ENABLE_POS) /**< CTRL0_ENABLE_DIS Setting */ 118 #define MXC_V_UART_CTRL0_ENABLE_EN ((uint32_t)0x1UL) /**< CTRL0_ENABLE_EN Value */ 119 #define MXC_S_UART_CTRL0_ENABLE_EN (MXC_V_UART_CTRL0_ENABLE_EN << MXC_F_UART_CTRL0_ENABLE_POS) /**< CTRL0_ENABLE_EN Setting */ 120 121 #define MXC_F_UART_CTRL0_PARITY_EN_POS 1 /**< CTRL0_PARITY_EN Position */ 122 #define MXC_F_UART_CTRL0_PARITY_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_PARITY_EN_POS)) /**< CTRL0_PARITY_EN Mask */ 123 #define MXC_V_UART_CTRL0_PARITY_EN_DIS ((uint32_t)0x0UL) /**< CTRL0_PARITY_EN_DIS Value */ 124 #define MXC_S_UART_CTRL0_PARITY_EN_DIS (MXC_V_UART_CTRL0_PARITY_EN_DIS << MXC_F_UART_CTRL0_PARITY_EN_POS) /**< CTRL0_PARITY_EN_DIS Setting */ 125 #define MXC_V_UART_CTRL0_PARITY_EN_EN ((uint32_t)0x1UL) /**< CTRL0_PARITY_EN_EN Value */ 126 #define MXC_S_UART_CTRL0_PARITY_EN_EN (MXC_V_UART_CTRL0_PARITY_EN_EN << MXC_F_UART_CTRL0_PARITY_EN_POS) /**< CTRL0_PARITY_EN_EN Setting */ 127 128 #define MXC_F_UART_CTRL0_PARITY_MODE_POS 2 /**< CTRL0_PARITY_MODE Position */ 129 #define MXC_F_UART_CTRL0_PARITY_MODE ((uint32_t)(0x3UL << MXC_F_UART_CTRL0_PARITY_MODE_POS)) /**< CTRL0_PARITY_MODE Mask */ 130 #define MXC_V_UART_CTRL0_PARITY_MODE_EVEN ((uint32_t)0x0UL) /**< CTRL0_PARITY_MODE_EVEN Value */ 131 #define MXC_S_UART_CTRL0_PARITY_MODE_EVEN (MXC_V_UART_CTRL0_PARITY_MODE_EVEN << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_EVEN Setting */ 132 #define MXC_V_UART_CTRL0_PARITY_MODE_ODD ((uint32_t)0x1UL) /**< CTRL0_PARITY_MODE_ODD Value */ 133 #define MXC_S_UART_CTRL0_PARITY_MODE_ODD (MXC_V_UART_CTRL0_PARITY_MODE_ODD << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_ODD Setting */ 134 #define MXC_V_UART_CTRL0_PARITY_MODE_MARK ((uint32_t)0x2UL) /**< CTRL0_PARITY_MODE_MARK Value */ 135 #define MXC_S_UART_CTRL0_PARITY_MODE_MARK (MXC_V_UART_CTRL0_PARITY_MODE_MARK << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_MARK Setting */ 136 #define MXC_V_UART_CTRL0_PARITY_MODE_SPACE ((uint32_t)0x3UL) /**< CTRL0_PARITY_MODE_SPACE Value */ 137 #define MXC_S_UART_CTRL0_PARITY_MODE_SPACE (MXC_V_UART_CTRL0_PARITY_MODE_SPACE << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_SPACE Setting */ 138 139 #define MXC_F_UART_CTRL0_PARITY_LVL_POS 4 /**< CTRL0_PARITY_LVL Position */ 140 #define MXC_F_UART_CTRL0_PARITY_LVL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_PARITY_LVL_POS)) /**< CTRL0_PARITY_LVL Mask */ 141 #define MXC_V_UART_CTRL0_PARITY_LVL_ZERO ((uint32_t)0x0UL) /**< CTRL0_PARITY_LVL_ZERO Value */ 142 #define MXC_S_UART_CTRL0_PARITY_LVL_ZERO (MXC_V_UART_CTRL0_PARITY_LVL_ZERO << MXC_F_UART_CTRL0_PARITY_LVL_POS) /**< CTRL0_PARITY_LVL_ZERO Setting */ 143 #define MXC_V_UART_CTRL0_PARITY_LVL_ONE ((uint32_t)0x1UL) /**< CTRL0_PARITY_LVL_ONE Value */ 144 #define MXC_S_UART_CTRL0_PARITY_LVL_ONE (MXC_V_UART_CTRL0_PARITY_LVL_ONE << MXC_F_UART_CTRL0_PARITY_LVL_POS) /**< CTRL0_PARITY_LVL_ONE Setting */ 145 146 #define MXC_F_UART_CTRL0_TXFLUSH_POS 5 /**< CTRL0_TXFLUSH Position */ 147 #define MXC_F_UART_CTRL0_TXFLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_TXFLUSH_POS)) /**< CTRL0_TXFLUSH Mask */ 148 #define MXC_V_UART_CTRL0_TXFLUSH_NOP ((uint32_t)0x0UL) /**< CTRL0_TXFLUSH_NOP Value */ 149 #define MXC_S_UART_CTRL0_TXFLUSH_NOP (MXC_V_UART_CTRL0_TXFLUSH_NOP << MXC_F_UART_CTRL0_TXFLUSH_POS) /**< CTRL0_TXFLUSH_NOP Setting */ 150 #define MXC_V_UART_CTRL0_TXFLUSH_FLUSH ((uint32_t)0x1UL) /**< CTRL0_TXFLUSH_FLUSH Value */ 151 #define MXC_S_UART_CTRL0_TXFLUSH_FLUSH (MXC_V_UART_CTRL0_TXFLUSH_FLUSH << MXC_F_UART_CTRL0_TXFLUSH_POS) /**< CTRL0_TXFLUSH_FLUSH Setting */ 152 153 #define MXC_F_UART_CTRL0_RXFLUSH_POS 6 /**< CTRL0_RXFLUSH Position */ 154 #define MXC_F_UART_CTRL0_RXFLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_RXFLUSH_POS)) /**< CTRL0_RXFLUSH Mask */ 155 #define MXC_V_UART_CTRL0_RXFLUSH_NOP ((uint32_t)0x0UL) /**< CTRL0_RXFLUSH_NOP Value */ 156 #define MXC_S_UART_CTRL0_RXFLUSH_NOP (MXC_V_UART_CTRL0_RXFLUSH_NOP << MXC_F_UART_CTRL0_RXFLUSH_POS) /**< CTRL0_RXFLUSH_NOP Setting */ 157 #define MXC_V_UART_CTRL0_RXFLUSH_FLUSH ((uint32_t)0x1UL) /**< CTRL0_RXFLUSH_FLUSH Value */ 158 #define MXC_S_UART_CTRL0_RXFLUSH_FLUSH (MXC_V_UART_CTRL0_RXFLUSH_FLUSH << MXC_F_UART_CTRL0_RXFLUSH_POS) /**< CTRL0_RXFLUSH_FLUSH Setting */ 159 160 #define MXC_F_UART_CTRL0_BITACC_POS 7 /**< CTRL0_BITACC Position */ 161 #define MXC_F_UART_CTRL0_BITACC ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_BITACC_POS)) /**< CTRL0_BITACC Mask */ 162 #define MXC_V_UART_CTRL0_BITACC_FRAME ((uint32_t)0x0UL) /**< CTRL0_BITACC_FRAME Value */ 163 #define MXC_S_UART_CTRL0_BITACC_FRAME (MXC_V_UART_CTRL0_BITACC_FRAME << MXC_F_UART_CTRL0_BITACC_POS) /**< CTRL0_BITACC_FRAME Setting */ 164 #define MXC_V_UART_CTRL0_BITACC_BIT ((uint32_t)0x1UL) /**< CTRL0_BITACC_BIT Value */ 165 #define MXC_S_UART_CTRL0_BITACC_BIT (MXC_V_UART_CTRL0_BITACC_BIT << MXC_F_UART_CTRL0_BITACC_POS) /**< CTRL0_BITACC_BIT Setting */ 166 167 #define MXC_F_UART_CTRL0_SIZE_POS 8 /**< CTRL0_SIZE Position */ 168 #define MXC_F_UART_CTRL0_SIZE ((uint32_t)(0x3UL << MXC_F_UART_CTRL0_SIZE_POS)) /**< CTRL0_SIZE Mask */ 169 #define MXC_V_UART_CTRL0_SIZE_5BIT_DATA ((uint32_t)0x0UL) /**< CTRL0_SIZE_5BIT_DATA Value */ 170 #define MXC_S_UART_CTRL0_SIZE_5BIT_DATA (MXC_V_UART_CTRL0_SIZE_5BIT_DATA << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_5BIT_DATA Setting */ 171 #define MXC_V_UART_CTRL0_SIZE_6BIT_DATA ((uint32_t)0x1UL) /**< CTRL0_SIZE_6BIT_DATA Value */ 172 #define MXC_S_UART_CTRL0_SIZE_6BIT_DATA (MXC_V_UART_CTRL0_SIZE_6BIT_DATA << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_6BIT_DATA Setting */ 173 #define MXC_V_UART_CTRL0_SIZE_7BIT_DATA ((uint32_t)0x2UL) /**< CTRL0_SIZE_7BIT_DATA Value */ 174 #define MXC_S_UART_CTRL0_SIZE_7BIT_DATA (MXC_V_UART_CTRL0_SIZE_7BIT_DATA << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_7BIT_DATA Setting */ 175 #define MXC_V_UART_CTRL0_SIZE_8BIT_DATA ((uint32_t)0x3UL) /**< CTRL0_SIZE_8BIT_DATA Value */ 176 #define MXC_S_UART_CTRL0_SIZE_8BIT_DATA (MXC_V_UART_CTRL0_SIZE_8BIT_DATA << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_8BIT_DATA Setting */ 177 178 #define MXC_F_UART_CTRL0_STOP_POS 10 /**< CTRL0_STOP Position */ 179 #define MXC_F_UART_CTRL0_STOP ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_STOP_POS)) /**< CTRL0_STOP Mask */ 180 #define MXC_V_UART_CTRL0_STOP_1_STOPBITS ((uint32_t)0x0UL) /**< CTRL0_STOP_1_STOPBITS Value */ 181 #define MXC_S_UART_CTRL0_STOP_1_STOPBITS (MXC_V_UART_CTRL0_STOP_1_STOPBITS << MXC_F_UART_CTRL0_STOP_POS) /**< CTRL0_STOP_1_STOPBITS Setting */ 182 #define MXC_V_UART_CTRL0_STOP_2_STOPBITS ((uint32_t)0x1UL) /**< CTRL0_STOP_2_STOPBITS Value */ 183 #define MXC_S_UART_CTRL0_STOP_2_STOPBITS (MXC_V_UART_CTRL0_STOP_2_STOPBITS << MXC_F_UART_CTRL0_STOP_POS) /**< CTRL0_STOP_2_STOPBITS Setting */ 184 185 #define MXC_F_UART_CTRL0_FLOW_POS 11 /**< CTRL0_FLOW Position */ 186 #define MXC_F_UART_CTRL0_FLOW ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_FLOW_POS)) /**< CTRL0_FLOW Mask */ 187 #define MXC_V_UART_CTRL0_FLOW_DIS ((uint32_t)0x0UL) /**< CTRL0_FLOW_DIS Value */ 188 #define MXC_S_UART_CTRL0_FLOW_DIS (MXC_V_UART_CTRL0_FLOW_DIS << MXC_F_UART_CTRL0_FLOW_POS) /**< CTRL0_FLOW_DIS Setting */ 189 #define MXC_V_UART_CTRL0_FLOW_EN ((uint32_t)0x1UL) /**< CTRL0_FLOW_EN Value */ 190 #define MXC_S_UART_CTRL0_FLOW_EN (MXC_V_UART_CTRL0_FLOW_EN << MXC_F_UART_CTRL0_FLOW_POS) /**< CTRL0_FLOW_EN Setting */ 191 192 #define MXC_F_UART_CTRL0_FLOWPOL_POS 12 /**< CTRL0_FLOWPOL Position */ 193 #define MXC_F_UART_CTRL0_FLOWPOL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_FLOWPOL_POS)) /**< CTRL0_FLOWPOL Mask */ 194 #define MXC_V_UART_CTRL0_FLOWPOL_ACTIVE_LOW ((uint32_t)0x0UL) /**< CTRL0_FLOWPOL_ACTIVE_LOW Value */ 195 #define MXC_S_UART_CTRL0_FLOWPOL_ACTIVE_LOW (MXC_V_UART_CTRL0_FLOWPOL_ACTIVE_LOW << MXC_F_UART_CTRL0_FLOWPOL_POS) /**< CTRL0_FLOWPOL_ACTIVE_LOW Setting */ 196 #define MXC_V_UART_CTRL0_FLOWPOL_ACTIVE_HIGH ((uint32_t)0x1UL) /**< CTRL0_FLOWPOL_ACTIVE_HIGH Value */ 197 #define MXC_S_UART_CTRL0_FLOWPOL_ACTIVE_HIGH (MXC_V_UART_CTRL0_FLOWPOL_ACTIVE_HIGH << MXC_F_UART_CTRL0_FLOWPOL_POS) /**< CTRL0_FLOWPOL_ACTIVE_HIGH Setting */ 198 199 #define MXC_F_UART_CTRL0_NULLMOD_POS 13 /**< CTRL0_NULLMOD Position */ 200 #define MXC_F_UART_CTRL0_NULLMOD ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_NULLMOD_POS)) /**< CTRL0_NULLMOD Mask */ 201 #define MXC_V_UART_CTRL0_NULLMOD_NORMAL ((uint32_t)0x0UL) /**< CTRL0_NULLMOD_NORMAL Value */ 202 #define MXC_S_UART_CTRL0_NULLMOD_NORMAL (MXC_V_UART_CTRL0_NULLMOD_NORMAL << MXC_F_UART_CTRL0_NULLMOD_POS) /**< CTRL0_NULLMOD_NORMAL Setting */ 203 #define MXC_V_UART_CTRL0_NULLMOD_SWAPPED ((uint32_t)0x1UL) /**< CTRL0_NULLMOD_SWAPPED Value */ 204 #define MXC_S_UART_CTRL0_NULLMOD_SWAPPED (MXC_V_UART_CTRL0_NULLMOD_SWAPPED << MXC_F_UART_CTRL0_NULLMOD_POS) /**< CTRL0_NULLMOD_SWAPPED Setting */ 205 206 #define MXC_F_UART_CTRL0_BREAK_POS 14 /**< CTRL0_BREAK Position */ 207 #define MXC_F_UART_CTRL0_BREAK ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_BREAK_POS)) /**< CTRL0_BREAK Mask */ 208 #define MXC_V_UART_CTRL0_BREAK_NORMAL ((uint32_t)0x0UL) /**< CTRL0_BREAK_NORMAL Value */ 209 #define MXC_S_UART_CTRL0_BREAK_NORMAL (MXC_V_UART_CTRL0_BREAK_NORMAL << MXC_F_UART_CTRL0_BREAK_POS) /**< CTRL0_BREAK_NORMAL Setting */ 210 #define MXC_V_UART_CTRL0_BREAK_BREAK ((uint32_t)0x1UL) /**< CTRL0_BREAK_BREAK Value */ 211 #define MXC_S_UART_CTRL0_BREAK_BREAK (MXC_V_UART_CTRL0_BREAK_BREAK << MXC_F_UART_CTRL0_BREAK_POS) /**< CTRL0_BREAK_BREAK Setting */ 212 213 #define MXC_F_UART_CTRL0_CLK_SEL_POS 15 /**< CTRL0_CLK_SEL Position */ 214 #define MXC_F_UART_CTRL0_CLK_SEL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_CLK_SEL_POS)) /**< CTRL0_CLK_SEL Mask */ 215 #define MXC_V_UART_CTRL0_CLK_SEL_PERIPH_CLK ((uint32_t)0x0UL) /**< CTRL0_CLK_SEL_PERIPH_CLK Value */ 216 #define MXC_S_UART_CTRL0_CLK_SEL_PERIPH_CLK (MXC_V_UART_CTRL0_CLK_SEL_PERIPH_CLK << MXC_F_UART_CTRL0_CLK_SEL_POS) /**< CTRL0_CLK_SEL_PERIPH_CLK Setting */ 217 #define MXC_V_UART_CTRL0_CLK_SEL_ALT_CLK ((uint32_t)0x1UL) /**< CTRL0_CLK_SEL_ALT_CLK Value */ 218 #define MXC_S_UART_CTRL0_CLK_SEL_ALT_CLK (MXC_V_UART_CTRL0_CLK_SEL_ALT_CLK << MXC_F_UART_CTRL0_CLK_SEL_POS) /**< CTRL0_CLK_SEL_ALT_CLK Setting */ 219 220 #define MXC_F_UART_CTRL0_TO_CNT_POS 16 /**< CTRL0_TO_CNT Position */ 221 #define MXC_F_UART_CTRL0_TO_CNT ((uint32_t)(0xFFUL << MXC_F_UART_CTRL0_TO_CNT_POS)) /**< CTRL0_TO_CNT Mask */ 222 223 /**@} end of group UART_CTRL0_Register */ 224 225 /** 226 * @ingroup uart_registers 227 * @defgroup UART_CTRL1 UART_CTRL1 228 * @brief Threshold Control register. 229 * @{ 230 */ 231 #define MXC_F_UART_CTRL1_RX_FIFO_LVL_POS 0 /**< CTRL1_RX_FIFO_LVL Position */ 232 #define MXC_F_UART_CTRL1_RX_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_RX_FIFO_LVL_POS)) /**< CTRL1_RX_FIFO_LVL Mask */ 233 234 #define MXC_F_UART_CTRL1_TX_FIFO_LVL_POS 8 /**< CTRL1_TX_FIFO_LVL Position */ 235 #define MXC_F_UART_CTRL1_TX_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_TX_FIFO_LVL_POS)) /**< CTRL1_TX_FIFO_LVL Mask */ 236 237 #define MXC_F_UART_CTRL1_RTS_FIFO_LVL_POS 16 /**< CTRL1_RTS_FIFO_LVL Position */ 238 #define MXC_F_UART_CTRL1_RTS_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_RTS_FIFO_LVL_POS)) /**< CTRL1_RTS_FIFO_LVL Mask */ 239 240 /**@} end of group UART_CTRL1_Register */ 241 242 /** 243 * @ingroup uart_registers 244 * @defgroup UART_STAT UART_STAT 245 * @brief Status Register. 246 * @{ 247 */ 248 #define MXC_F_UART_STAT_TX_BUSY_POS 0 /**< STAT_TX_BUSY Position */ 249 #define MXC_F_UART_STAT_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_BUSY_POS)) /**< STAT_TX_BUSY Mask */ 250 #define MXC_V_UART_STAT_TX_BUSY_IDLE ((uint32_t)0x0UL) /**< STAT_TX_BUSY_IDLE Value */ 251 #define MXC_S_UART_STAT_TX_BUSY_IDLE (MXC_V_UART_STAT_TX_BUSY_IDLE << MXC_F_UART_STAT_TX_BUSY_POS) /**< STAT_TX_BUSY_IDLE Setting */ 252 #define MXC_V_UART_STAT_TX_BUSY_BUSY ((uint32_t)0x1UL) /**< STAT_TX_BUSY_BUSY Value */ 253 #define MXC_S_UART_STAT_TX_BUSY_BUSY (MXC_V_UART_STAT_TX_BUSY_BUSY << MXC_F_UART_STAT_TX_BUSY_POS) /**< STAT_TX_BUSY_BUSY Setting */ 254 255 #define MXC_F_UART_STAT_RX_BUSY_POS 1 /**< STAT_RX_BUSY Position */ 256 #define MXC_F_UART_STAT_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_BUSY_POS)) /**< STAT_RX_BUSY Mask */ 257 #define MXC_V_UART_STAT_RX_BUSY_IDLE ((uint32_t)0x0UL) /**< STAT_RX_BUSY_IDLE Value */ 258 #define MXC_S_UART_STAT_RX_BUSY_IDLE (MXC_V_UART_STAT_RX_BUSY_IDLE << MXC_F_UART_STAT_RX_BUSY_POS) /**< STAT_RX_BUSY_IDLE Setting */ 259 #define MXC_V_UART_STAT_RX_BUSY_BUSY ((uint32_t)0x1UL) /**< STAT_RX_BUSY_BUSY Value */ 260 #define MXC_S_UART_STAT_RX_BUSY_BUSY (MXC_V_UART_STAT_RX_BUSY_BUSY << MXC_F_UART_STAT_RX_BUSY_POS) /**< STAT_RX_BUSY_BUSY Setting */ 261 262 #define MXC_F_UART_STAT_PARITY_POS 2 /**< STAT_PARITY Position */ 263 #define MXC_F_UART_STAT_PARITY ((uint32_t)(0x1UL << MXC_F_UART_STAT_PARITY_POS)) /**< STAT_PARITY Mask */ 264 #define MXC_V_UART_STAT_PARITY_0 ((uint32_t)0x0UL) /**< STAT_PARITY_0 Value */ 265 #define MXC_S_UART_STAT_PARITY_0 (MXC_V_UART_STAT_PARITY_0 << MXC_F_UART_STAT_PARITY_POS) /**< STAT_PARITY_0 Setting */ 266 #define MXC_V_UART_STAT_PARITY_1 ((uint32_t)0x1UL) /**< STAT_PARITY_1 Value */ 267 #define MXC_S_UART_STAT_PARITY_1 (MXC_V_UART_STAT_PARITY_1 << MXC_F_UART_STAT_PARITY_POS) /**< STAT_PARITY_1 Setting */ 268 269 #define MXC_F_UART_STAT_BREAK_POS 3 /**< STAT_BREAK Position */ 270 #define MXC_F_UART_STAT_BREAK ((uint32_t)(0x1UL << MXC_F_UART_STAT_BREAK_POS)) /**< STAT_BREAK Mask */ 271 #define MXC_V_UART_STAT_BREAK_RECV ((uint32_t)0x1UL) /**< STAT_BREAK_RECV Value */ 272 #define MXC_S_UART_STAT_BREAK_RECV (MXC_V_UART_STAT_BREAK_RECV << MXC_F_UART_STAT_BREAK_POS) /**< STAT_BREAK_RECV Setting */ 273 274 #define MXC_F_UART_STAT_RX_EMPTY_POS 4 /**< STAT_RX_EMPTY Position */ 275 #define MXC_F_UART_STAT_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_EMPTY_POS)) /**< STAT_RX_EMPTY Mask */ 276 #define MXC_V_UART_STAT_RX_EMPTY_EMPTY ((uint32_t)0x1UL) /**< STAT_RX_EMPTY_EMPTY Value */ 277 #define MXC_S_UART_STAT_RX_EMPTY_EMPTY (MXC_V_UART_STAT_RX_EMPTY_EMPTY << MXC_F_UART_STAT_RX_EMPTY_POS) /**< STAT_RX_EMPTY_EMPTY Setting */ 278 279 #define MXC_F_UART_STAT_RX_FULL_POS 5 /**< STAT_RX_FULL Position */ 280 #define MXC_F_UART_STAT_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_FULL_POS)) /**< STAT_RX_FULL Mask */ 281 #define MXC_V_UART_STAT_RX_FULL_FULL ((uint32_t)0x1UL) /**< STAT_RX_FULL_FULL Value */ 282 #define MXC_S_UART_STAT_RX_FULL_FULL (MXC_V_UART_STAT_RX_FULL_FULL << MXC_F_UART_STAT_RX_FULL_POS) /**< STAT_RX_FULL_FULL Setting */ 283 284 #define MXC_F_UART_STAT_TX_EMPTY_POS 6 /**< STAT_TX_EMPTY Position */ 285 #define MXC_F_UART_STAT_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_EMPTY_POS)) /**< STAT_TX_EMPTY Mask */ 286 #define MXC_V_UART_STAT_TX_EMPTY_EMPTY ((uint32_t)0x1UL) /**< STAT_TX_EMPTY_EMPTY Value */ 287 #define MXC_S_UART_STAT_TX_EMPTY_EMPTY (MXC_V_UART_STAT_TX_EMPTY_EMPTY << MXC_F_UART_STAT_TX_EMPTY_POS) /**< STAT_TX_EMPTY_EMPTY Setting */ 288 289 #define MXC_F_UART_STAT_TX_FULL_POS 7 /**< STAT_TX_FULL Position */ 290 #define MXC_F_UART_STAT_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_FULL_POS)) /**< STAT_TX_FULL Mask */ 291 #define MXC_V_UART_STAT_TX_FULL_FULL ((uint32_t)0x1UL) /**< STAT_TX_FULL_FULL Value */ 292 #define MXC_S_UART_STAT_TX_FULL_FULL (MXC_V_UART_STAT_TX_FULL_FULL << MXC_F_UART_STAT_TX_FULL_POS) /**< STAT_TX_FULL_FULL Setting */ 293 294 #define MXC_F_UART_STAT_RX_NUM_POS 8 /**< STAT_RX_NUM Position */ 295 #define MXC_F_UART_STAT_RX_NUM ((uint32_t)(0x3FUL << MXC_F_UART_STAT_RX_NUM_POS)) /**< STAT_RX_NUM Mask */ 296 297 #define MXC_F_UART_STAT_TX_NUM_POS 16 /**< STAT_TX_NUM Position */ 298 #define MXC_F_UART_STAT_TX_NUM ((uint32_t)(0x3FUL << MXC_F_UART_STAT_TX_NUM_POS)) /**< STAT_TX_NUM Mask */ 299 300 #define MXC_F_UART_STAT_RX_TO_POS 24 /**< STAT_RX_TO Position */ 301 #define MXC_F_UART_STAT_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_TO_POS)) /**< STAT_RX_TO Mask */ 302 #define MXC_V_UART_STAT_RX_TO_EXPIRED ((uint32_t)0x1UL) /**< STAT_RX_TO_EXPIRED Value */ 303 #define MXC_S_UART_STAT_RX_TO_EXPIRED (MXC_V_UART_STAT_RX_TO_EXPIRED << MXC_F_UART_STAT_RX_TO_POS) /**< STAT_RX_TO_EXPIRED Setting */ 304 305 /**@} end of group UART_STAT_Register */ 306 307 /** 308 * @ingroup uart_registers 309 * @defgroup UART_INT_EN UART_INT_EN 310 * @brief Interrupt Enable Register. 311 * @{ 312 */ 313 #define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS 0 /**< INT_EN_RX_FRAME_ERROR Position */ 314 #define MXC_F_UART_INT_EN_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**< INT_EN_RX_FRAME_ERROR Mask */ 315 #define MXC_V_UART_INT_EN_RX_FRAME_ERROR_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_FRAME_ERROR_DIS Value */ 316 #define MXC_S_UART_INT_EN_RX_FRAME_ERROR_DIS (MXC_V_UART_INT_EN_RX_FRAME_ERROR_DIS << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS) /**< INT_EN_RX_FRAME_ERROR_DIS Setting */ 317 #define MXC_V_UART_INT_EN_RX_FRAME_ERROR_EN ((uint32_t)0x1UL) /**< INT_EN_RX_FRAME_ERROR_EN Value */ 318 #define MXC_S_UART_INT_EN_RX_FRAME_ERROR_EN (MXC_V_UART_INT_EN_RX_FRAME_ERROR_EN << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS) /**< INT_EN_RX_FRAME_ERROR_EN Setting */ 319 320 #define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS 1 /**< INT_EN_RX_PARITY_ERROR Position */ 321 #define MXC_F_UART_INT_EN_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**< INT_EN_RX_PARITY_ERROR Mask */ 322 #define MXC_V_UART_INT_EN_RX_PARITY_ERROR_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_PARITY_ERROR_DIS Value */ 323 #define MXC_S_UART_INT_EN_RX_PARITY_ERROR_DIS (MXC_V_UART_INT_EN_RX_PARITY_ERROR_DIS << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS) /**< INT_EN_RX_PARITY_ERROR_DIS Setting */ 324 #define MXC_V_UART_INT_EN_RX_PARITY_ERROR_EN ((uint32_t)0x1UL) /**< INT_EN_RX_PARITY_ERROR_EN Value */ 325 #define MXC_S_UART_INT_EN_RX_PARITY_ERROR_EN (MXC_V_UART_INT_EN_RX_PARITY_ERROR_EN << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS) /**< INT_EN_RX_PARITY_ERROR_EN Setting */ 326 327 #define MXC_F_UART_INT_EN_CTS_POS 2 /**< INT_EN_CTS Position */ 328 #define MXC_F_UART_INT_EN_CTS ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_CTS_POS)) /**< INT_EN_CTS Mask */ 329 #define MXC_V_UART_INT_EN_CTS_DIS ((uint32_t)0x0UL) /**< INT_EN_CTS_DIS Value */ 330 #define MXC_S_UART_INT_EN_CTS_DIS (MXC_V_UART_INT_EN_CTS_DIS << MXC_F_UART_INT_EN_CTS_POS) /**< INT_EN_CTS_DIS Setting */ 331 #define MXC_V_UART_INT_EN_CTS_EN ((uint32_t)0x1UL) /**< INT_EN_CTS_EN Value */ 332 #define MXC_S_UART_INT_EN_CTS_EN (MXC_V_UART_INT_EN_CTS_EN << MXC_F_UART_INT_EN_CTS_POS) /**< INT_EN_CTS_EN Setting */ 333 334 #define MXC_F_UART_INT_EN_RX_OVERRUN_POS 3 /**< INT_EN_RX_OVERRUN Position */ 335 #define MXC_F_UART_INT_EN_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN Mask */ 336 #define MXC_V_UART_INT_EN_RX_OVERRUN_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_OVERRUN_DIS Value */ 337 #define MXC_S_UART_INT_EN_RX_OVERRUN_DIS (MXC_V_UART_INT_EN_RX_OVERRUN_DIS << MXC_F_UART_INT_EN_RX_OVERRUN_POS) /**< INT_EN_RX_OVERRUN_DIS Setting */ 338 #define MXC_V_UART_INT_EN_RX_OVERRUN_EN ((uint32_t)0x1UL) /**< INT_EN_RX_OVERRUN_EN Value */ 339 #define MXC_S_UART_INT_EN_RX_OVERRUN_EN (MXC_V_UART_INT_EN_RX_OVERRUN_EN << MXC_F_UART_INT_EN_RX_OVERRUN_POS) /**< INT_EN_RX_OVERRUN_EN Setting */ 340 341 #define MXC_F_UART_INT_EN_RX_FIFO_LVL_POS 4 /**< INT_EN_RX_FIFO_LVL Position */ 342 #define MXC_F_UART_INT_EN_RX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FIFO_LVL_POS)) /**< INT_EN_RX_FIFO_LVL Mask */ 343 #define MXC_V_UART_INT_EN_RX_FIFO_LVL_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_FIFO_LVL_DIS Value */ 344 #define MXC_S_UART_INT_EN_RX_FIFO_LVL_DIS (MXC_V_UART_INT_EN_RX_FIFO_LVL_DIS << MXC_F_UART_INT_EN_RX_FIFO_LVL_POS) /**< INT_EN_RX_FIFO_LVL_DIS Setting */ 345 #define MXC_V_UART_INT_EN_RX_FIFO_LVL_EN ((uint32_t)0x1UL) /**< INT_EN_RX_FIFO_LVL_EN Value */ 346 #define MXC_S_UART_INT_EN_RX_FIFO_LVL_EN (MXC_V_UART_INT_EN_RX_FIFO_LVL_EN << MXC_F_UART_INT_EN_RX_FIFO_LVL_POS) /**< INT_EN_RX_FIFO_LVL_EN Setting */ 347 348 #define MXC_F_UART_INT_EN_TX_FIFO_AE_POS 5 /**< INT_EN_TX_FIFO_AE Position */ 349 #define MXC_F_UART_INT_EN_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_AE_POS)) /**< INT_EN_TX_FIFO_AE Mask */ 350 #define MXC_V_UART_INT_EN_TX_FIFO_AE_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_FIFO_AE_DIS Value */ 351 #define MXC_S_UART_INT_EN_TX_FIFO_AE_DIS (MXC_V_UART_INT_EN_TX_FIFO_AE_DIS << MXC_F_UART_INT_EN_TX_FIFO_AE_POS) /**< INT_EN_TX_FIFO_AE_DIS Setting */ 352 #define MXC_V_UART_INT_EN_TX_FIFO_AE_EN ((uint32_t)0x1UL) /**< INT_EN_TX_FIFO_AE_EN Value */ 353 #define MXC_S_UART_INT_EN_TX_FIFO_AE_EN (MXC_V_UART_INT_EN_TX_FIFO_AE_EN << MXC_F_UART_INT_EN_TX_FIFO_AE_POS) /**< INT_EN_TX_FIFO_AE_EN Setting */ 354 355 #define MXC_F_UART_INT_EN_TX_FIFO_LVL_POS 6 /**< INT_EN_TX_FIFO_LVL Position */ 356 #define MXC_F_UART_INT_EN_TX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_LVL_POS)) /**< INT_EN_TX_FIFO_LVL Mask */ 357 #define MXC_V_UART_INT_EN_TX_FIFO_LVL_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_FIFO_LVL_DIS Value */ 358 #define MXC_S_UART_INT_EN_TX_FIFO_LVL_DIS (MXC_V_UART_INT_EN_TX_FIFO_LVL_DIS << MXC_F_UART_INT_EN_TX_FIFO_LVL_POS) /**< INT_EN_TX_FIFO_LVL_DIS Setting */ 359 #define MXC_V_UART_INT_EN_TX_FIFO_LVL_EN ((uint32_t)0x1UL) /**< INT_EN_TX_FIFO_LVL_EN Value */ 360 #define MXC_S_UART_INT_EN_TX_FIFO_LVL_EN (MXC_V_UART_INT_EN_TX_FIFO_LVL_EN << MXC_F_UART_INT_EN_TX_FIFO_LVL_POS) /**< INT_EN_TX_FIFO_LVL_EN Setting */ 361 362 #define MXC_F_UART_INT_EN_BREAK_POS 7 /**< INT_EN_BREAK Position */ 363 #define MXC_F_UART_INT_EN_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK Mask */ 364 #define MXC_V_UART_INT_EN_BREAK_DIS ((uint32_t)0x0UL) /**< INT_EN_BREAK_DIS Value */ 365 #define MXC_S_UART_INT_EN_BREAK_DIS (MXC_V_UART_INT_EN_BREAK_DIS << MXC_F_UART_INT_EN_BREAK_POS) /**< INT_EN_BREAK_DIS Setting */ 366 #define MXC_V_UART_INT_EN_BREAK_EN ((uint32_t)0x1UL) /**< INT_EN_BREAK_EN Value */ 367 #define MXC_S_UART_INT_EN_BREAK_EN (MXC_V_UART_INT_EN_BREAK_EN << MXC_F_UART_INT_EN_BREAK_POS) /**< INT_EN_BREAK_EN Setting */ 368 369 #define MXC_F_UART_INT_EN_RX_TO_POS 8 /**< INT_EN_RX_TO Position */ 370 #define MXC_F_UART_INT_EN_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_TO_POS)) /**< INT_EN_RX_TO Mask */ 371 #define MXC_V_UART_INT_EN_RX_TO_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_TO_DIS Value */ 372 #define MXC_S_UART_INT_EN_RX_TO_DIS (MXC_V_UART_INT_EN_RX_TO_DIS << MXC_F_UART_INT_EN_RX_TO_POS) /**< INT_EN_RX_TO_DIS Setting */ 373 #define MXC_V_UART_INT_EN_RX_TO_EN ((uint32_t)0x1UL) /**< INT_EN_RX_TO_EN Value */ 374 #define MXC_S_UART_INT_EN_RX_TO_EN (MXC_V_UART_INT_EN_RX_TO_EN << MXC_F_UART_INT_EN_RX_TO_POS) /**< INT_EN_RX_TO_EN Setting */ 375 376 #define MXC_F_UART_INT_EN_LAST_BREAK_POS 9 /**< INT_EN_LAST_BREAK Position */ 377 #define MXC_F_UART_INT_EN_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**< INT_EN_LAST_BREAK Mask */ 378 #define MXC_V_UART_INT_EN_LAST_BREAK_DIS ((uint32_t)0x0UL) /**< INT_EN_LAST_BREAK_DIS Value */ 379 #define MXC_S_UART_INT_EN_LAST_BREAK_DIS (MXC_V_UART_INT_EN_LAST_BREAK_DIS << MXC_F_UART_INT_EN_LAST_BREAK_POS) /**< INT_EN_LAST_BREAK_DIS Setting */ 380 #define MXC_V_UART_INT_EN_LAST_BREAK_EN ((uint32_t)0x1UL) /**< INT_EN_LAST_BREAK_EN Value */ 381 #define MXC_S_UART_INT_EN_LAST_BREAK_EN (MXC_V_UART_INT_EN_LAST_BREAK_EN << MXC_F_UART_INT_EN_LAST_BREAK_POS) /**< INT_EN_LAST_BREAK_EN Setting */ 382 383 /**@} end of group UART_INT_EN_Register */ 384 385 /** 386 * @ingroup uart_registers 387 * @defgroup UART_INT_FL UART_INT_FL 388 * @brief Interrupt Status Flags. 389 * @{ 390 */ 391 #define MXC_F_UART_INT_FL_FRAME_POS 0 /**< INT_FL_FRAME Position */ 392 #define MXC_F_UART_INT_FL_FRAME ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_FRAME_POS)) /**< INT_FL_FRAME Mask */ 393 #define MXC_V_UART_INT_FL_FRAME_ACTIVE ((uint32_t)0x1UL) /**< INT_FL_FRAME_ACTIVE Value */ 394 #define MXC_S_UART_INT_FL_FRAME_ACTIVE (MXC_V_UART_INT_FL_FRAME_ACTIVE << MXC_F_UART_INT_FL_FRAME_POS) /**< INT_FL_FRAME_ACTIVE Setting */ 395 396 #define MXC_F_UART_INT_FL_PARITY_POS 1 /**< INT_FL_PARITY Position */ 397 #define MXC_F_UART_INT_FL_PARITY ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_PARITY_POS)) /**< INT_FL_PARITY Mask */ 398 #define MXC_V_UART_INT_FL_PARITY_ACTIVE ((uint32_t)0x1UL) /**< INT_FL_PARITY_ACTIVE Value */ 399 #define MXC_S_UART_INT_FL_PARITY_ACTIVE (MXC_V_UART_INT_FL_PARITY_ACTIVE << MXC_F_UART_INT_FL_PARITY_POS) /**< INT_FL_PARITY_ACTIVE Setting */ 400 401 #define MXC_F_UART_INT_FL_CTS_CHANGE_POS 2 /**< INT_FL_CTS_CHANGE Position */ 402 #define MXC_F_UART_INT_FL_CTS_CHANGE ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_CTS_CHANGE_POS)) /**< INT_FL_CTS_CHANGE Mask */ 403 #define MXC_V_UART_INT_FL_CTS_CHANGE_ACTIVE ((uint32_t)0x1UL) /**< INT_FL_CTS_CHANGE_ACTIVE Value */ 404 #define MXC_S_UART_INT_FL_CTS_CHANGE_ACTIVE (MXC_V_UART_INT_FL_CTS_CHANGE_ACTIVE << MXC_F_UART_INT_FL_CTS_CHANGE_POS) /**< INT_FL_CTS_CHANGE_ACTIVE Setting */ 405 406 #define MXC_F_UART_INT_FL_RX_OVR_POS 3 /**< INT_FL_RX_OVR Position */ 407 #define MXC_F_UART_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */ 408 #define MXC_V_UART_INT_FL_RX_OVR_ACTIVE ((uint32_t)0x1UL) /**< INT_FL_RX_OVR_ACTIVE Value */ 409 #define MXC_S_UART_INT_FL_RX_OVR_ACTIVE (MXC_V_UART_INT_FL_RX_OVR_ACTIVE << MXC_F_UART_INT_FL_RX_OVR_POS) /**< INT_FL_RX_OVR_ACTIVE Setting */ 410 411 #define MXC_F_UART_INT_FL_RX_FIFO_LVL_POS 4 /**< INT_FL_RX_FIFO_LVL Position */ 412 #define MXC_F_UART_INT_FL_RX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FIFO_LVL_POS)) /**< INT_FL_RX_FIFO_LVL Mask */ 413 #define MXC_V_UART_INT_FL_RX_FIFO_LVL_ACTIVE ((uint32_t)0x1UL) /**< INT_FL_RX_FIFO_LVL_ACTIVE Value */ 414 #define MXC_S_UART_INT_FL_RX_FIFO_LVL_ACTIVE (MXC_V_UART_INT_FL_RX_FIFO_LVL_ACTIVE << MXC_F_UART_INT_FL_RX_FIFO_LVL_POS) /**< INT_FL_RX_FIFO_LVL_ACTIVE Setting */ 415 416 #define MXC_F_UART_INT_FL_TX_FIFO_AE_POS 5 /**< INT_FL_TX_FIFO_AE Position */ 417 #define MXC_F_UART_INT_FL_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_AE_POS)) /**< INT_FL_TX_FIFO_AE Mask */ 418 #define MXC_V_UART_INT_FL_TX_FIFO_AE_ACTIVE ((uint32_t)0x1UL) /**< INT_FL_TX_FIFO_AE_ACTIVE Value */ 419 #define MXC_S_UART_INT_FL_TX_FIFO_AE_ACTIVE (MXC_V_UART_INT_FL_TX_FIFO_AE_ACTIVE << MXC_F_UART_INT_FL_TX_FIFO_AE_POS) /**< INT_FL_TX_FIFO_AE_ACTIVE Setting */ 420 421 #define MXC_F_UART_INT_FL_TX_FIFO_LVL_POS 6 /**< INT_FL_TX_FIFO_LVL Position */ 422 #define MXC_F_UART_INT_FL_TX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_LVL_POS)) /**< INT_FL_TX_FIFO_LVL Mask */ 423 #define MXC_V_UART_INT_FL_TX_FIFO_LVL_ACTIVE ((uint32_t)0x1UL) /**< INT_FL_TX_FIFO_LVL_ACTIVE Value */ 424 #define MXC_S_UART_INT_FL_TX_FIFO_LVL_ACTIVE (MXC_V_UART_INT_FL_TX_FIFO_LVL_ACTIVE << MXC_F_UART_INT_FL_TX_FIFO_LVL_POS) /**< INT_FL_TX_FIFO_LVL_ACTIVE Setting */ 425 426 #define MXC_F_UART_INT_FL_BREAK_POS 7 /**< INT_FL_BREAK Position */ 427 #define MXC_F_UART_INT_FL_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK Mask */ 428 #define MXC_V_UART_INT_FL_BREAK_ACTIVE ((uint32_t)0x1UL) /**< INT_FL_BREAK_ACTIVE Value */ 429 #define MXC_S_UART_INT_FL_BREAK_ACTIVE (MXC_V_UART_INT_FL_BREAK_ACTIVE << MXC_F_UART_INT_FL_BREAK_POS) /**< INT_FL_BREAK_ACTIVE Setting */ 430 431 #define MXC_F_UART_INT_FL_RX_TO_POS 8 /**< INT_FL_RX_TO Position */ 432 #define MXC_F_UART_INT_FL_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_TO_POS)) /**< INT_FL_RX_TO Mask */ 433 #define MXC_V_UART_INT_FL_RX_TO_ACTIVE ((uint32_t)0x1UL) /**< INT_FL_RX_TO_ACTIVE Value */ 434 #define MXC_S_UART_INT_FL_RX_TO_ACTIVE (MXC_V_UART_INT_FL_RX_TO_ACTIVE << MXC_F_UART_INT_FL_RX_TO_POS) /**< INT_FL_RX_TO_ACTIVE Setting */ 435 436 #define MXC_F_UART_INT_FL_LAST_BREAK_POS 9 /**< INT_FL_LAST_BREAK Position */ 437 #define MXC_F_UART_INT_FL_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**< INT_FL_LAST_BREAK Mask */ 438 #define MXC_V_UART_INT_FL_LAST_BREAK_ACTIVE ((uint32_t)0x1UL) /**< INT_FL_LAST_BREAK_ACTIVE Value */ 439 #define MXC_S_UART_INT_FL_LAST_BREAK_ACTIVE (MXC_V_UART_INT_FL_LAST_BREAK_ACTIVE << MXC_F_UART_INT_FL_LAST_BREAK_POS) /**< INT_FL_LAST_BREAK_ACTIVE Setting */ 440 441 /**@} end of group UART_INT_FL_Register */ 442 443 /** 444 * @ingroup uart_registers 445 * @defgroup UART_BAUD0 UART_BAUD0 446 * @brief Baud rate register. Integer portion. 447 * @{ 448 */ 449 #define MXC_F_UART_BAUD0_IBAUD_POS 0 /**< BAUD0_IBAUD Position */ 450 #define MXC_F_UART_BAUD0_IBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */ 451 452 #define MXC_F_UART_BAUD0_CLKDIV_POS 16 /**< BAUD0_CLKDIV Position */ 453 #define MXC_F_UART_BAUD0_CLKDIV ((uint32_t)(0x7UL << MXC_F_UART_BAUD0_CLKDIV_POS)) /**< BAUD0_CLKDIV Mask */ 454 #define MXC_V_UART_BAUD0_CLKDIV_DIV128 ((uint32_t)0x0UL) /**< BAUD0_CLKDIV_DIV128 Value */ 455 #define MXC_S_UART_BAUD0_CLKDIV_DIV128 (MXC_V_UART_BAUD0_CLKDIV_DIV128 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_DIV128 Setting */ 456 #define MXC_V_UART_BAUD0_CLKDIV_DIV64 ((uint32_t)0x1UL) /**< BAUD0_CLKDIV_DIV64 Value */ 457 #define MXC_S_UART_BAUD0_CLKDIV_DIV64 (MXC_V_UART_BAUD0_CLKDIV_DIV64 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_DIV64 Setting */ 458 #define MXC_V_UART_BAUD0_CLKDIV_DIV32 ((uint32_t)0x2UL) /**< BAUD0_CLKDIV_DIV32 Value */ 459 #define MXC_S_UART_BAUD0_CLKDIV_DIV32 (MXC_V_UART_BAUD0_CLKDIV_DIV32 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_DIV32 Setting */ 460 #define MXC_V_UART_BAUD0_CLKDIV_DIV16 ((uint32_t)0x3UL) /**< BAUD0_CLKDIV_DIV16 Value */ 461 #define MXC_S_UART_BAUD0_CLKDIV_DIV16 (MXC_V_UART_BAUD0_CLKDIV_DIV16 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_DIV16 Setting */ 462 #define MXC_V_UART_BAUD0_CLKDIV_DIV8 ((uint32_t)0x4UL) /**< BAUD0_CLKDIV_DIV8 Value */ 463 #define MXC_S_UART_BAUD0_CLKDIV_DIV8 (MXC_V_UART_BAUD0_CLKDIV_DIV8 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_DIV8 Setting */ 464 465 /**@} end of group UART_BAUD0_Register */ 466 467 /** 468 * @ingroup uart_registers 469 * @defgroup UART_BAUD1 UART_BAUD1 470 * @brief Baud rate register. Decimal Setting. 471 * @{ 472 */ 473 #define MXC_F_UART_BAUD1_DBAUD_POS 0 /**< BAUD1_DBAUD Position */ 474 #define MXC_F_UART_BAUD1_DBAUD ((uint32_t)(0x7FUL << MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */ 475 476 /**@} end of group UART_BAUD1_Register */ 477 478 /** 479 * @ingroup uart_registers 480 * @defgroup UART_FIFO UART_FIFO 481 * @brief FIFO Data buffer. 482 * @{ 483 */ 484 #define MXC_F_UART_FIFO_FIFO_POS 0 /**< FIFO_FIFO Position */ 485 #define MXC_F_UART_FIFO_FIFO ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask */ 486 487 /**@} end of group UART_FIFO_Register */ 488 489 /** 490 * @ingroup uart_registers 491 * @defgroup UART_DMA UART_DMA 492 * @brief DMA Configuration. 493 * @{ 494 */ 495 #define MXC_F_UART_DMA_TXDMA_EN_POS 0 /**< DMA_TXDMA_EN Position */ 496 #define MXC_F_UART_DMA_TXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TXDMA_EN_POS)) /**< DMA_TXDMA_EN Mask */ 497 #define MXC_V_UART_DMA_TXDMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_TXDMA_EN_DIS Value */ 498 #define MXC_S_UART_DMA_TXDMA_EN_DIS (MXC_V_UART_DMA_TXDMA_EN_DIS << MXC_F_UART_DMA_TXDMA_EN_POS) /**< DMA_TXDMA_EN_DIS Setting */ 499 #define MXC_V_UART_DMA_TXDMA_EN_EN ((uint32_t)0x1UL) /**< DMA_TXDMA_EN_EN Value */ 500 #define MXC_S_UART_DMA_TXDMA_EN_EN (MXC_V_UART_DMA_TXDMA_EN_EN << MXC_F_UART_DMA_TXDMA_EN_POS) /**< DMA_TXDMA_EN_EN Setting */ 501 502 #define MXC_F_UART_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */ 503 #define MXC_F_UART_DMA_RXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */ 504 #define MXC_V_UART_DMA_RXDMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_RXDMA_EN_DIS Value */ 505 #define MXC_S_UART_DMA_RXDMA_EN_DIS (MXC_V_UART_DMA_RXDMA_EN_DIS << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_DIS Setting */ 506 #define MXC_V_UART_DMA_RXDMA_EN_EN ((uint32_t)0x1UL) /**< DMA_RXDMA_EN_EN Value */ 507 #define MXC_S_UART_DMA_RXDMA_EN_EN (MXC_V_UART_DMA_RXDMA_EN_EN << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_EN Setting */ 508 509 #define MXC_F_UART_DMA_TXDMA_LEVEL_POS 8 /**< DMA_TXDMA_LVL Position */ 510 #define MXC_F_UART_DMA_TXDMA_LEVEL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_TXDMA_LEVEL_POS)) /**< DMA_TXDMA_LVL Mask */ 511 512 #define MXC_F_UART_DMA_RXDMA_LEVEL_POS 16 /**< DMA_RXDMA_LVL Position */ 513 #define MXC_F_UART_DMA_RXDMA_LEVEL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_RXDMA_LEVEL_POS)) /**< DMA_RXDMA_LVL Mask */ 514 515 /**@} end of group UART_DMA_Register */ 516 517 /** 518 * @ingroup uart_registers 519 * @defgroup UART_TXFIFO UART_TXFIFO 520 * @brief Transmit FIFO Status register. 521 * @{ 522 */ 523 #define MXC_F_UART_TXFIFO_DATA_POS 0 /**< TXFIFO_DATA Position */ 524 #define MXC_F_UART_TXFIFO_DATA ((uint32_t)(0x7FUL << MXC_F_UART_TXFIFO_DATA_POS)) /**< TXFIFO_DATA Mask */ 525 526 /**@} end of group UART_TXFIFO_Register */ 527 528 #ifdef __cplusplus 529 } 530 #endif 531 532 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_UART_REGS_H_ 533
