1 /** 2 * @file tmr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup tmr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_TMR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_TMR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup tmr 67 * @defgroup tmr_registers TMR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. 69 * @details 32-bit reloadable timer that can be used for timing and event counting. 70 */ 71 72 /** 73 * @ingroup tmr_registers 74 * Structure type to access the TMR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t cnt; /**< <tt>\b 0x00:</tt> TMR CNT Register */ 78 __IO uint32_t cmp; /**< <tt>\b 0x04:</tt> TMR CMP Register */ 79 __IO uint32_t pwm; /**< <tt>\b 0x08:</tt> TMR PWM Register */ 80 __IO uint32_t intr; /**< <tt>\b 0x0C:</tt> TMR INTR Register */ 81 __IO uint32_t cn; /**< <tt>\b 0x10:</tt> TMR CN Register */ 82 __IO uint32_t nolcmp; /**< <tt>\b 0x14:</tt> TMR NOLCMP Register */ 83 } mxc_tmr_regs_t; 84 85 /* Register offsets for module TMR */ 86 /** 87 * @ingroup tmr_registers 88 * @defgroup TMR_Register_Offsets Register Offsets 89 * @brief TMR Peripheral Register Offsets from the TMR Base Peripheral Address. 90 * @{ 91 */ 92 #define MXC_R_TMR_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt> 0x0000</tt> */ 93 #define MXC_R_TMR_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt> 0x0004</tt> */ 94 #define MXC_R_TMR_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt> 0x0008</tt> */ 95 #define MXC_R_TMR_INTR ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt> 0x000C</tt> */ 96 #define MXC_R_TMR_CN ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt> 0x0010</tt> */ 97 #define MXC_R_TMR_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: <tt> 0x0014</tt> */ 98 /**@} end of group tmr_registers */ 99 100 /** 101 * @ingroup tmr_registers 102 * @defgroup TMR_CNT TMR_CNT 103 * @brief Count. This register stores the current timer count. 104 * @{ 105 */ 106 #define MXC_F_TMR_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ 107 #define MXC_F_TMR_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CNT_COUNT_POS)) /**< CNT_COUNT Mask */ 108 109 /**@} end of group TMR_CNT_Register */ 110 111 /** 112 * @ingroup tmr_registers 113 * @defgroup TMR_CMP TMR_CMP 114 * @brief Compare. This register stores the compare value, which is used to set the 115 * maximum count value to initiate a reload of the timer to 0x0001. 116 * @{ 117 */ 118 #define MXC_F_TMR_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */ 119 #define MXC_F_TMR_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */ 120 121 /**@} end of group TMR_CMP_Register */ 122 123 /** 124 * @ingroup tmr_registers 125 * @defgroup TMR_PWM TMR_PWM 126 * @brief PWM. This register stores the value that is compared to the current timer 127 * count. 128 * @{ 129 */ 130 #define MXC_F_TMR_PWM_PWM_POS 0 /**< PWM_PWM Position */ 131 #define MXC_F_TMR_PWM_PWM ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_PWM_PWM_POS)) /**< PWM_PWM Mask */ 132 133 /**@} end of group TMR_PWM_Register */ 134 135 /** 136 * @ingroup tmr_registers 137 * @defgroup TMR_INTR TMR_INTR 138 * @brief Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the 139 * associated interrupt. 140 * @{ 141 */ 142 #define MXC_F_TMR_INTR_IRQ_POS 0 /**< INTR_IRQ Position */ 143 #define MXC_F_TMR_INTR_IRQ ((uint32_t)(0x1UL << MXC_F_TMR_INTR_IRQ_POS)) /**< INTR_IRQ Mask */ 144 145 /**@} end of group TMR_INTR_Register */ 146 147 /** 148 * @ingroup tmr_registers 149 * @defgroup TMR_CN TMR_CN 150 * @brief Timer Control Register. 151 * @{ 152 */ 153 #define MXC_F_TMR_CN_TMODE_POS 0 /**< CN_TMODE Position */ 154 #define MXC_F_TMR_CN_TMODE ((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS)) /**< CN_TMODE Mask */ 155 #define MXC_V_TMR_CN_TMODE_ONESHOT ((uint32_t)0x0UL) /**< CN_TMODE_ONESHOT Value */ 156 #define MXC_S_TMR_CN_TMODE_ONESHOT (MXC_V_TMR_CN_TMODE_ONESHOT << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_ONESHOT Setting */ 157 #define MXC_V_TMR_CN_TMODE_CONTINUOUS ((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */ 158 #define MXC_S_TMR_CN_TMODE_CONTINUOUS (MXC_V_TMR_CN_TMODE_CONTINUOUS << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */ 159 #define MXC_V_TMR_CN_TMODE_COUNTER ((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */ 160 #define MXC_S_TMR_CN_TMODE_COUNTER (MXC_V_TMR_CN_TMODE_COUNTER << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */ 161 #define MXC_V_TMR_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */ 162 #define MXC_S_TMR_CN_TMODE_PWM (MXC_V_TMR_CN_TMODE_PWM << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */ 163 #define MXC_V_TMR_CN_TMODE_CAPTURE ((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */ 164 #define MXC_S_TMR_CN_TMODE_CAPTURE (MXC_V_TMR_CN_TMODE_CAPTURE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */ 165 #define MXC_V_TMR_CN_TMODE_COMPARE ((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */ 166 #define MXC_S_TMR_CN_TMODE_COMPARE (MXC_V_TMR_CN_TMODE_COMPARE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */ 167 #define MXC_V_TMR_CN_TMODE_GATED ((uint32_t)0x6UL) /**< CN_TMODE_GATED Value */ 168 #define MXC_S_TMR_CN_TMODE_GATED (MXC_V_TMR_CN_TMODE_GATED << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */ 169 #define MXC_V_TMR_CN_TMODE_CAPTURECOMPARE ((uint32_t)0x7UL) /**< CN_TMODE_CAPTURECOMPARE Value */ 170 #define MXC_S_TMR_CN_TMODE_CAPTURECOMPARE (MXC_V_TMR_CN_TMODE_CAPTURECOMPARE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURECOMPARE Setting */ 171 172 #define MXC_F_TMR_CN_PRES_POS 3 /**< CN_PRES Position */ 173 #define MXC_F_TMR_CN_PRES ((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS)) /**< CN_PRES Mask */ 174 #define MXC_V_TMR_CN_PRES_DIV1 ((uint32_t)0x0UL) /**< CN_PRES_DIV1 Value */ 175 #define MXC_S_TMR_CN_PRES_DIV1 (MXC_V_TMR_CN_PRES_DIV1 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV1 Setting */ 176 #define MXC_V_TMR_CN_PRES_DIV2 ((uint32_t)0x1UL) /**< CN_PRES_DIV2 Value */ 177 #define MXC_S_TMR_CN_PRES_DIV2 (MXC_V_TMR_CN_PRES_DIV2 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV2 Setting */ 178 #define MXC_V_TMR_CN_PRES_DIV4 ((uint32_t)0x2UL) /**< CN_PRES_DIV4 Value */ 179 #define MXC_S_TMR_CN_PRES_DIV4 (MXC_V_TMR_CN_PRES_DIV4 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV4 Setting */ 180 #define MXC_V_TMR_CN_PRES_DIV8 ((uint32_t)0x3UL) /**< CN_PRES_DIV8 Value */ 181 #define MXC_S_TMR_CN_PRES_DIV8 (MXC_V_TMR_CN_PRES_DIV8 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV8 Setting */ 182 #define MXC_V_TMR_CN_PRES_DIV16 ((uint32_t)0x4UL) /**< CN_PRES_DIV16 Value */ 183 #define MXC_S_TMR_CN_PRES_DIV16 (MXC_V_TMR_CN_PRES_DIV16 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV16 Setting */ 184 #define MXC_V_TMR_CN_PRES_DIV32 ((uint32_t)0x5UL) /**< CN_PRES_DIV32 Value */ 185 #define MXC_S_TMR_CN_PRES_DIV32 (MXC_V_TMR_CN_PRES_DIV32 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV32 Setting */ 186 #define MXC_V_TMR_CN_PRES_DIV64 ((uint32_t)0x6UL) /**< CN_PRES_DIV64 Value */ 187 #define MXC_S_TMR_CN_PRES_DIV64 (MXC_V_TMR_CN_PRES_DIV64 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV64 Setting */ 188 #define MXC_V_TMR_CN_PRES_DIV128 ((uint32_t)0x7UL) /**< CN_PRES_DIV128 Value */ 189 #define MXC_S_TMR_CN_PRES_DIV128 (MXC_V_TMR_CN_PRES_DIV128 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV128 Setting */ 190 #define MXC_V_TMR_CN_PRES_DIV256 ((uint32_t)0x0UL) /**< CN_PRES_DIV256 Value */ 191 #define MXC_S_TMR_CN_PRES_DIV256 (MXC_V_TMR_CN_PRES_DIV256 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV256 Setting */ 192 #define MXC_V_TMR_CN_PRES_DIV512 ((uint32_t)0x2UL) /**< CN_PRES_DIV512 Value */ 193 #define MXC_S_TMR_CN_PRES_DIV512 (MXC_V_TMR_CN_PRES_DIV512 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV512 Setting */ 194 #define MXC_V_TMR_CN_PRES_DIV1024 ((uint32_t)0x3UL) /**< CN_PRES_DIV1024 Value */ 195 #define MXC_S_TMR_CN_PRES_DIV1024 (MXC_V_TMR_CN_PRES_DIV1024 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV1024 Setting */ 196 #define MXC_V_TMR_CN_PRES_DIV2048 ((uint32_t)0x4UL) /**< CN_PRES_DIV2048 Value */ 197 #define MXC_S_TMR_CN_PRES_DIV2048 (MXC_V_TMR_CN_PRES_DIV2048 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV2048 Setting */ 198 #define MXC_V_TMR_CN_PRES_DIV4096 ((uint32_t)0x5UL) /**< CN_PRES_DIV4096 Value */ 199 #define MXC_S_TMR_CN_PRES_DIV4096 (MXC_V_TMR_CN_PRES_DIV4096 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV4096 Setting */ 200 201 #define MXC_F_TMR_CN_TPOL_POS 6 /**< CN_TPOL Position */ 202 #define MXC_F_TMR_CN_TPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS)) /**< CN_TPOL Mask */ 203 #define MXC_V_TMR_CN_TPOL_ACTIVEHI ((uint32_t)0x0UL) /**< CN_TPOL_ACTIVEHI Value */ 204 #define MXC_S_TMR_CN_TPOL_ACTIVEHI (MXC_V_TMR_CN_TPOL_ACTIVEHI << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVEHI Setting */ 205 #define MXC_V_TMR_CN_TPOL_ACTIVELO ((uint32_t)0x1UL) /**< CN_TPOL_ACTIVELO Value */ 206 #define MXC_S_TMR_CN_TPOL_ACTIVELO (MXC_V_TMR_CN_TPOL_ACTIVELO << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVELO Setting */ 207 208 #define MXC_F_TMR_CN_TEN_POS 7 /**< CN_TEN Position */ 209 #define MXC_F_TMR_CN_TEN ((uint32_t)(0x1UL << MXC_F_TMR_CN_TEN_POS)) /**< CN_TEN Mask */ 210 #define MXC_V_TMR_CN_TEN_DIS ((uint32_t)0x0UL) /**< CN_TEN_DIS Value */ 211 #define MXC_S_TMR_CN_TEN_DIS (MXC_V_TMR_CN_TEN_DIS << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_DIS Setting */ 212 #define MXC_V_TMR_CN_TEN_EN ((uint32_t)0x1UL) /**< CN_TEN_EN Value */ 213 #define MXC_S_TMR_CN_TEN_EN (MXC_V_TMR_CN_TEN_EN << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_EN Setting */ 214 215 #define MXC_F_TMR_CN_PRES3_POS 8 /**< CN_PRES3 Position */ 216 #define MXC_F_TMR_CN_PRES3 ((uint32_t)(0x1UL << MXC_F_TMR_CN_PRES3_POS)) /**< CN_PRES3 Mask */ 217 #define MXC_V_TMR_CN_PRES3_DIV1 ((uint32_t)0x0UL) /**< CN_PRES3_DIV1 Value */ 218 #define MXC_S_TMR_CN_PRES3_DIV1 (MXC_V_TMR_CN_PRES3_DIV1 << MXC_F_TMR_CN_PRES3_POS) /**< CN_PRES3_DIV1 Setting */ 219 #define MXC_V_TMR_CN_PRES3_DIV2 ((uint32_t)0x0UL) /**< CN_PRES3_DIV2 Value */ 220 #define MXC_S_TMR_CN_PRES3_DIV2 (MXC_V_TMR_CN_PRES3_DIV2 << MXC_F_TMR_CN_PRES3_POS) /**< CN_PRES3_DIV2 Setting */ 221 #define MXC_V_TMR_CN_PRES3_DIV4 ((uint32_t)0x0UL) /**< CN_PRES3_DIV4 Value */ 222 #define MXC_S_TMR_CN_PRES3_DIV4 (MXC_V_TMR_CN_PRES3_DIV4 << MXC_F_TMR_CN_PRES3_POS) /**< CN_PRES3_DIV4 Setting */ 223 #define MXC_V_TMR_CN_PRES3_DIV8 ((uint32_t)0x0UL) /**< CN_PRES3_DIV8 Value */ 224 #define MXC_S_TMR_CN_PRES3_DIV8 (MXC_V_TMR_CN_PRES3_DIV8 << MXC_F_TMR_CN_PRES3_POS) /**< CN_PRES3_DIV8 Setting */ 225 #define MXC_V_TMR_CN_PRES3_DIV16 ((uint32_t)0x0UL) /**< CN_PRES3_DIV16 Value */ 226 #define MXC_S_TMR_CN_PRES3_DIV16 (MXC_V_TMR_CN_PRES3_DIV16 << MXC_F_TMR_CN_PRES3_POS) /**< CN_PRES3_DIV16 Setting */ 227 #define MXC_V_TMR_CN_PRES3_DIV32 ((uint32_t)0x0UL) /**< CN_PRES3_DIV32 Value */ 228 #define MXC_S_TMR_CN_PRES3_DIV32 (MXC_V_TMR_CN_PRES3_DIV32 << MXC_F_TMR_CN_PRES3_POS) /**< CN_PRES3_DIV32 Setting */ 229 #define MXC_V_TMR_CN_PRES3_DIV64 ((uint32_t)0x0UL) /**< CN_PRES3_DIV64 Value */ 230 #define MXC_S_TMR_CN_PRES3_DIV64 (MXC_V_TMR_CN_PRES3_DIV64 << MXC_F_TMR_CN_PRES3_POS) /**< CN_PRES3_DIV64 Setting */ 231 #define MXC_V_TMR_CN_PRES3_DIV128 ((uint32_t)0x0UL) /**< CN_PRES3_DIV128 Value */ 232 #define MXC_S_TMR_CN_PRES3_DIV128 (MXC_V_TMR_CN_PRES3_DIV128 << MXC_F_TMR_CN_PRES3_POS) /**< CN_PRES3_DIV128 Setting */ 233 #define MXC_V_TMR_CN_PRES3_DIV256 ((uint32_t)0x1UL) /**< CN_PRES3_DIV256 Value */ 234 #define MXC_S_TMR_CN_PRES3_DIV256 (MXC_V_TMR_CN_PRES3_DIV256 << MXC_F_TMR_CN_PRES3_POS) /**< CN_PRES3_DIV256 Setting */ 235 #define MXC_V_TMR_CN_PRES3_DIV512 ((uint32_t)0x1UL) /**< CN_PRES3_DIV512 Value */ 236 #define MXC_S_TMR_CN_PRES3_DIV512 (MXC_V_TMR_CN_PRES3_DIV512 << MXC_F_TMR_CN_PRES3_POS) /**< CN_PRES3_DIV512 Setting */ 237 #define MXC_V_TMR_CN_PRES3_DIV1024 ((uint32_t)0x1UL) /**< CN_PRES3_DIV1024 Value */ 238 #define MXC_S_TMR_CN_PRES3_DIV1024 (MXC_V_TMR_CN_PRES3_DIV1024 << MXC_F_TMR_CN_PRES3_POS) /**< CN_PRES3_DIV1024 Setting */ 239 #define MXC_V_TMR_CN_PRES3_DIV2048 ((uint32_t)0x1UL) /**< CN_PRES3_DIV2048 Value */ 240 #define MXC_S_TMR_CN_PRES3_DIV2048 (MXC_V_TMR_CN_PRES3_DIV2048 << MXC_F_TMR_CN_PRES3_POS) /**< CN_PRES3_DIV2048 Setting */ 241 #define MXC_V_TMR_CN_PRES3_DIV4096 ((uint32_t)0x1UL) /**< CN_PRES3_DIV4096 Value */ 242 #define MXC_S_TMR_CN_PRES3_DIV4096 (MXC_V_TMR_CN_PRES3_DIV4096 << MXC_F_TMR_CN_PRES3_POS) /**< CN_PRES3_DIV4096 Setting */ 243 244 #define MXC_F_TMR_CN_PWMSYNC_POS 9 /**< CN_PWMSYNC Position */ 245 #define MXC_F_TMR_CN_PWMSYNC ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask */ 246 #define MXC_V_TMR_CN_PWMSYNC_DIS ((uint32_t)0x0UL) /**< CN_PWMSYNC_DIS Value */ 247 #define MXC_S_TMR_CN_PWMSYNC_DIS (MXC_V_TMR_CN_PWMSYNC_DIS << MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_DIS Setting */ 248 #define MXC_V_TMR_CN_PWMSYNC_EN ((uint32_t)0x1UL) /**< CN_PWMSYNC_EN Value */ 249 #define MXC_S_TMR_CN_PWMSYNC_EN (MXC_V_TMR_CN_PWMSYNC_EN << MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_EN Setting */ 250 251 #define MXC_F_TMR_CN_NOLHPOL_POS 10 /**< CN_NOLHPOL Position */ 252 #define MXC_F_TMR_CN_NOLHPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask */ 253 #define MXC_V_TMR_CN_NOLHPOL_NORMAL ((uint32_t)0x0UL) /**< CN_NOLHPOL_NORMAL Value */ 254 #define MXC_S_TMR_CN_NOLHPOL_NORMAL (MXC_V_TMR_CN_NOLHPOL_NORMAL << MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_NORMAL Setting */ 255 #define MXC_V_TMR_CN_NOLHPOL_INVERT ((uint32_t)0x1UL) /**< CN_NOLHPOL_INVERT Value */ 256 #define MXC_S_TMR_CN_NOLHPOL_INVERT (MXC_V_TMR_CN_NOLHPOL_INVERT << MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_INVERT Setting */ 257 258 #define MXC_F_TMR_CN_NOLLPOL_POS 11 /**< CN_NOLLPOL Position */ 259 #define MXC_F_TMR_CN_NOLLPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask */ 260 #define MXC_V_TMR_CN_NOLLPOL_NORMAL ((uint32_t)0x0UL) /**< CN_NOLLPOL_NORMAL Value */ 261 #define MXC_S_TMR_CN_NOLLPOL_NORMAL (MXC_V_TMR_CN_NOLLPOL_NORMAL << MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_NORMAL Setting */ 262 #define MXC_V_TMR_CN_NOLLPOL_INVERT ((uint32_t)0x1UL) /**< CN_NOLLPOL_INVERT Value */ 263 #define MXC_S_TMR_CN_NOLLPOL_INVERT (MXC_V_TMR_CN_NOLLPOL_INVERT << MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_INVERT Setting */ 264 265 #define MXC_F_TMR_CN_PWMCKBD_POS 12 /**< CN_PWMCKBD Position */ 266 #define MXC_F_TMR_CN_PWMCKBD ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask */ 267 #define MXC_V_TMR_CN_PWMCKBD_DIS ((uint32_t)0x1UL) /**< CN_PWMCKBD_DIS Value */ 268 #define MXC_S_TMR_CN_PWMCKBD_DIS (MXC_V_TMR_CN_PWMCKBD_DIS << MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_DIS Setting */ 269 #define MXC_V_TMR_CN_PWMCKBD_EN ((uint32_t)0x0UL) /**< CN_PWMCKBD_EN Value */ 270 #define MXC_S_TMR_CN_PWMCKBD_EN (MXC_V_TMR_CN_PWMCKBD_EN << MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_EN Setting */ 271 272 /**@} end of group TMR_CN_Register */ 273 274 /** 275 * @ingroup tmr_registers 276 * @defgroup TMR_NOLCMP TMR_NOLCMP 277 * @brief Timer Non-Overlapping Compare Register. 278 * @{ 279 */ 280 #define MXC_F_TMR_NOLCMP_NOLLCMP_POS 0 /**< NOLCMP_NOLLCMP Position */ 281 #define MXC_F_TMR_NOLCMP_NOLLCMP ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_NOLLCMP_POS)) /**< NOLCMP_NOLLCMP Mask */ 282 283 #define MXC_F_TMR_NOLCMP_NOLHCMP_POS 8 /**< NOLCMP_NOLHCMP Position */ 284 #define MXC_F_TMR_NOLCMP_NOLHCMP ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_NOLHCMP_POS)) /**< NOLCMP_NOLHCMP Mask */ 285 286 /**@} end of group TMR_NOLCMP_Register */ 287 288 #ifdef __cplusplus 289 } 290 #endif 291 292 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_TMR_REGS_H_ 293
