1 /** 2 * @file spixr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPIXR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup spixr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SPIXR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SPIXR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup spixr 67 * @defgroup spixr_registers SPIXR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SPIXR Peripheral Module. 69 * @details SPIXR peripheral. 70 */ 71 72 /** 73 * @ingroup spixr_registers 74 * Structure type to access the SPIXR Registers. 75 */ 76 typedef struct { 77 union { 78 __IO uint32_t data32; /**< <tt>\b 0x00:</tt> SPIXR DATA32 Register */ 79 __IO uint16_t data16[2]; /**< <tt>\b 0x00:</tt> SPIXR DATA16 Register */ 80 __IO uint8_t data8[4]; /**< <tt>\b 0x00:</tt> SPIXR DATA8 Register */ 81 }; 82 __IO uint32_t ctrl1; /**< <tt>\b 0x04:</tt> SPIXR CTRL1 Register */ 83 __IO uint32_t ctrl2; /**< <tt>\b 0x08:</tt> SPIXR CTRL2 Register */ 84 __IO uint32_t ctrl3; /**< <tt>\b 0x0C:</tt> SPIXR CTRL3 Register */ 85 __IO uint32_t ss_time; /**< <tt>\b 0x10:</tt> SPIXR SS_TIME Register */ 86 __IO uint32_t brg_ctrl; /**< <tt>\b 0x14:</tt> SPIXR BRG_CTRL Register */ 87 __R uint32_t rsv_0x18; 88 __IO uint32_t dma; /**< <tt>\b 0x1C:</tt> SPIXR DMA Register */ 89 __IO uint32_t int_fl; /**< <tt>\b 0x20:</tt> SPIXR INT_FL Register */ 90 __IO uint32_t int_en; /**< <tt>\b 0x24:</tt> SPIXR INT_EN Register */ 91 __IO uint32_t wake_fl; /**< <tt>\b 0x28:</tt> SPIXR WAKE_FL Register */ 92 __IO uint32_t wake_en; /**< <tt>\b 0x2C:</tt> SPIXR WAKE_EN Register */ 93 __I uint32_t stat; /**< <tt>\b 0x30:</tt> SPIXR STAT Register */ 94 __IO uint32_t xmem_ctrl; /**< <tt>\b 0x34:</tt> SPIXR XMEM_CTRL Register */ 95 } mxc_spixr_regs_t; 96 97 /* Register offsets for module SPIXR */ 98 /** 99 * @ingroup spixr_registers 100 * @defgroup SPIXR_Register_Offsets Register Offsets 101 * @brief SPIXR Peripheral Register Offsets from the SPIXR Base Peripheral Address. 102 * @{ 103 */ 104 #define MXC_R_SPIXR_DATA32 ((uint32_t)0x00000000UL) /**< Offset from SPIXR Base Address: <tt> 0x0000</tt> */ 105 #define MXC_R_SPIXR_DATA16 ((uint32_t)0x00000000UL) /**< Offset from SPIXR Base Address: <tt> 0x0000</tt> */ 106 #define MXC_R_SPIXR_DATA8 ((uint32_t)0x00000000UL) /**< Offset from SPIXR Base Address: <tt> 0x0000</tt> */ 107 #define MXC_R_SPIXR_CTRL1 ((uint32_t)0x00000004UL) /**< Offset from SPIXR Base Address: <tt> 0x0004</tt> */ 108 #define MXC_R_SPIXR_CTRL2 ((uint32_t)0x00000008UL) /**< Offset from SPIXR Base Address: <tt> 0x0008</tt> */ 109 #define MXC_R_SPIXR_CTRL3 ((uint32_t)0x0000000CUL) /**< Offset from SPIXR Base Address: <tt> 0x000C</tt> */ 110 #define MXC_R_SPIXR_SS_TIME ((uint32_t)0x00000010UL) /**< Offset from SPIXR Base Address: <tt> 0x0010</tt> */ 111 #define MXC_R_SPIXR_BRG_CTRL ((uint32_t)0x00000014UL) /**< Offset from SPIXR Base Address: <tt> 0x0014</tt> */ 112 #define MXC_R_SPIXR_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPIXR Base Address: <tt> 0x001C</tt> */ 113 #define MXC_R_SPIXR_INT_FL ((uint32_t)0x00000020UL) /**< Offset from SPIXR Base Address: <tt> 0x0020</tt> */ 114 #define MXC_R_SPIXR_INT_EN ((uint32_t)0x00000024UL) /**< Offset from SPIXR Base Address: <tt> 0x0024</tt> */ 115 #define MXC_R_SPIXR_WAKE_FL ((uint32_t)0x00000028UL) /**< Offset from SPIXR Base Address: <tt> 0x0028</tt> */ 116 #define MXC_R_SPIXR_WAKE_EN ((uint32_t)0x0000002CUL) /**< Offset from SPIXR Base Address: <tt> 0x002C</tt> */ 117 #define MXC_R_SPIXR_STAT ((uint32_t)0x00000030UL) /**< Offset from SPIXR Base Address: <tt> 0x0030</tt> */ 118 #define MXC_R_SPIXR_XMEM_CTRL ((uint32_t)0x00000034UL) /**< Offset from SPIXR Base Address: <tt> 0x0034</tt> */ 119 /**@} end of group spixr_registers */ 120 121 /** 122 * @ingroup spixr_registers 123 * @defgroup SPIXR_DATA32 SPIXR_DATA32 124 * @brief Register for reading and writing the FIFO. 125 * @{ 126 */ 127 #define MXC_F_SPIXR_DATA32_DATA_POS 0 /**< DATA32_DATA Position */ 128 #define MXC_F_SPIXR_DATA32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPIXR_DATA32_DATA_POS)) /**< DATA32_DATA Mask */ 129 130 /**@} end of group SPIXR_DATA32_Register */ 131 132 /** 133 * @ingroup spixr_registers 134 * @defgroup SPIXR_DATA16 SPIXR_DATA16 135 * @brief Register for reading and writing the FIFO. 136 * @{ 137 */ 138 #define MXC_F_SPIXR_DATA16_DATA_POS 0 /**< DATA16_DATA Position */ 139 #define MXC_F_SPIXR_DATA16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPIXR_DATA16_DATA_POS)) /**< DATA16_DATA Mask */ 140 141 /**@} end of group SPIXR_DATA16_Register */ 142 143 /** 144 * @ingroup spixr_registers 145 * @defgroup SPIXR_DATA8 SPIXR_DATA8 146 * @brief Register for reading and writing the FIFO. 147 * @{ 148 */ 149 #define MXC_F_SPIXR_DATA8_DATA_POS 0 /**< DATA8_DATA Position */ 150 #define MXC_F_SPIXR_DATA8_DATA ((uint8_t)(0xFFUL << MXC_F_SPIXR_DATA8_DATA_POS)) /**< DATA8_DATA Mask */ 151 152 /**@} end of group SPIXR_DATA8_Register */ 153 154 /** 155 * @ingroup spixr_registers 156 * @defgroup SPIXR_CTRL1 SPIXR_CTRL1 157 * @brief Register for controlling SPI peripheral. 158 * @{ 159 */ 160 #define MXC_F_SPIXR_CTRL1_ENABLE_POS 0 /**< CTRL1_ENABLE Position */ 161 #define MXC_F_SPIXR_CTRL1_ENABLE ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_ENABLE_POS)) /**< CTRL1_ENABLE Mask */ 162 #define MXC_V_SPIXR_CTRL1_ENABLE_DIS ((uint32_t)0x0UL) /**< CTRL1_ENABLE_DIS Value */ 163 #define MXC_S_SPIXR_CTRL1_ENABLE_DIS (MXC_V_SPIXR_CTRL1_ENABLE_DIS << MXC_F_SPIXR_CTRL1_ENABLE_POS) /**< CTRL1_ENABLE_DIS Setting */ 164 #define MXC_V_SPIXR_CTRL1_ENABLE_EN ((uint32_t)0x1UL) /**< CTRL1_ENABLE_EN Value */ 165 #define MXC_S_SPIXR_CTRL1_ENABLE_EN (MXC_V_SPIXR_CTRL1_ENABLE_EN << MXC_F_SPIXR_CTRL1_ENABLE_POS) /**< CTRL1_ENABLE_EN Setting */ 166 167 #define MXC_F_SPIXR_CTRL1_MASTER_POS 1 /**< CTRL1_MASTER Position */ 168 #define MXC_F_SPIXR_CTRL1_MASTER ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_MASTER_POS)) /**< CTRL1_MASTER Mask */ 169 #define MXC_V_SPIXR_CTRL1_MASTER_DIS ((uint32_t)0x0UL) /**< CTRL1_MASTER_DIS Value */ 170 #define MXC_S_SPIXR_CTRL1_MASTER_DIS (MXC_V_SPIXR_CTRL1_MASTER_DIS << MXC_F_SPIXR_CTRL1_MASTER_POS) /**< CTRL1_MASTER_DIS Setting */ 171 #define MXC_V_SPIXR_CTRL1_MASTER_EN ((uint32_t)0x1UL) /**< CTRL1_MASTER_EN Value */ 172 #define MXC_S_SPIXR_CTRL1_MASTER_EN (MXC_V_SPIXR_CTRL1_MASTER_EN << MXC_F_SPIXR_CTRL1_MASTER_POS) /**< CTRL1_MASTER_EN Setting */ 173 174 #define MXC_F_SPIXR_CTRL1_SS_IO_POS 4 /**< CTRL1_SS_IO Position */ 175 #define MXC_F_SPIXR_CTRL1_SS_IO ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_SS_IO_POS)) /**< CTRL1_SS_IO Mask */ 176 #define MXC_V_SPIXR_CTRL1_SS_IO_OUTPUT ((uint32_t)0x0UL) /**< CTRL1_SS_IO_OUTPUT Value */ 177 #define MXC_S_SPIXR_CTRL1_SS_IO_OUTPUT (MXC_V_SPIXR_CTRL1_SS_IO_OUTPUT << MXC_F_SPIXR_CTRL1_SS_IO_POS) /**< CTRL1_SS_IO_OUTPUT Setting */ 178 #define MXC_V_SPIXR_CTRL1_SS_IO_INPUT ((uint32_t)0x1UL) /**< CTRL1_SS_IO_INPUT Value */ 179 #define MXC_S_SPIXR_CTRL1_SS_IO_INPUT (MXC_V_SPIXR_CTRL1_SS_IO_INPUT << MXC_F_SPIXR_CTRL1_SS_IO_POS) /**< CTRL1_SS_IO_INPUT Setting */ 180 181 #define MXC_F_SPIXR_CTRL1_START_POS 5 /**< CTRL1_START Position */ 182 #define MXC_F_SPIXR_CTRL1_START ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_START_POS)) /**< CTRL1_START Mask */ 183 #define MXC_V_SPIXR_CTRL1_START_START ((uint32_t)0x1UL) /**< CTRL1_START_START Value */ 184 #define MXC_S_SPIXR_CTRL1_START_START (MXC_V_SPIXR_CTRL1_START_START << MXC_F_SPIXR_CTRL1_START_POS) /**< CTRL1_START_START Setting */ 185 186 #define MXC_F_SPIXR_CTRL1_SS_CTRL_POS 8 /**< CTRL1_SS_CTRL Position */ 187 #define MXC_F_SPIXR_CTRL1_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_SS_CTRL_POS)) /**< CTRL1_SS_CTRL Mask */ 188 #define MXC_V_SPIXR_CTRL1_SS_CTRL_DEASSERT ((uint32_t)0x0UL) /**< CTRL1_SS_CTRL_DEASSERT Value */ 189 #define MXC_S_SPIXR_CTRL1_SS_CTRL_DEASSERT (MXC_V_SPIXR_CTRL1_SS_CTRL_DEASSERT << MXC_F_SPIXR_CTRL1_SS_CTRL_POS) /**< CTRL1_SS_CTRL_DEASSERT Setting */ 190 #define MXC_V_SPIXR_CTRL1_SS_CTRL_ASSERT ((uint32_t)0x1UL) /**< CTRL1_SS_CTRL_ASSERT Value */ 191 #define MXC_S_SPIXR_CTRL1_SS_CTRL_ASSERT (MXC_V_SPIXR_CTRL1_SS_CTRL_ASSERT << MXC_F_SPIXR_CTRL1_SS_CTRL_POS) /**< CTRL1_SS_CTRL_ASSERT Setting */ 192 193 #define MXC_F_SPIXR_CTRL1_SS_POS 16 /**< CTRL1_SS Position */ 194 #define MXC_F_SPIXR_CTRL1_SS ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_SS_POS)) /**< CTRL1_SS Mask */ 195 196 /**@} end of group SPIXR_CTRL1_Register */ 197 198 /** 199 * @ingroup spixr_registers 200 * @defgroup SPIXR_CTRL2 SPIXR_CTRL2 201 * @brief Register for controlling SPI peripheral. 202 * @{ 203 */ 204 #define MXC_F_SPIXR_CTRL2_TX_NUM_CHAR_POS 0 /**< CTRL2_TX_NUM_CHAR Position */ 205 #define MXC_F_SPIXR_CTRL2_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPIXR_CTRL2_TX_NUM_CHAR_POS)) /**< CTRL2_TX_NUM_CHAR Mask */ 206 207 #define MXC_F_SPIXR_CTRL2_RX_NUM_CHAR_POS 16 /**< CTRL2_RX_NUM_CHAR Position */ 208 #define MXC_F_SPIXR_CTRL2_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPIXR_CTRL2_RX_NUM_CHAR_POS)) /**< CTRL2_RX_NUM_CHAR Mask */ 209 210 /**@} end of group SPIXR_CTRL2_Register */ 211 212 /** 213 * @ingroup spixr_registers 214 * @defgroup SPIXR_CTRL3 SPIXR_CTRL3 215 * @brief Register for controlling SPI peripheral. 216 * @{ 217 */ 218 #define MXC_F_SPIXR_CTRL3_CPHA_POS 0 /**< CTRL3_CPHA Position */ 219 #define MXC_F_SPIXR_CTRL3_CPHA ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL3_CPHA_POS)) /**< CTRL3_CPHA Mask */ 220 #define MXC_V_SPIXR_CTRL3_CPHA_RISINGEDGE ((uint32_t)0x0UL) /**< CTRL3_CPHA_RISINGEDGE Value */ 221 #define MXC_S_SPIXR_CTRL3_CPHA_RISINGEDGE (MXC_V_SPIXR_CTRL3_CPHA_RISINGEDGE << MXC_F_SPIXR_CTRL3_CPHA_POS) /**< CTRL3_CPHA_RISINGEDGE Setting */ 222 #define MXC_V_SPIXR_CTRL3_CPHA_FALLINGEDGE ((uint32_t)0x1UL) /**< CTRL3_CPHA_FALLINGEDGE Value */ 223 #define MXC_S_SPIXR_CTRL3_CPHA_FALLINGEDGE (MXC_V_SPIXR_CTRL3_CPHA_FALLINGEDGE << MXC_F_SPIXR_CTRL3_CPHA_POS) /**< CTRL3_CPHA_FALLINGEDGE Setting */ 224 225 #define MXC_F_SPIXR_CTRL3_CPOL_POS 1 /**< CTRL3_CPOL Position */ 226 #define MXC_F_SPIXR_CTRL3_CPOL ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL3_CPOL_POS)) /**< CTRL3_CPOL Mask */ 227 #define MXC_V_SPIXR_CTRL3_CPOL_NORMAL ((uint32_t)0x0UL) /**< CTRL3_CPOL_NORMAL Value */ 228 #define MXC_S_SPIXR_CTRL3_CPOL_NORMAL (MXC_V_SPIXR_CTRL3_CPOL_NORMAL << MXC_F_SPIXR_CTRL3_CPOL_POS) /**< CTRL3_CPOL_NORMAL Setting */ 229 #define MXC_V_SPIXR_CTRL3_CPOL_INVERTED ((uint32_t)0x1UL) /**< CTRL3_CPOL_INVERTED Value */ 230 #define MXC_S_SPIXR_CTRL3_CPOL_INVERTED (MXC_V_SPIXR_CTRL3_CPOL_INVERTED << MXC_F_SPIXR_CTRL3_CPOL_POS) /**< CTRL3_CPOL_INVERTED Setting */ 231 232 #define MXC_F_SPIXR_CTRL3_SCLK_INV_POS 4 /**< CTRL3_SCLK_INV Position */ 233 #define MXC_F_SPIXR_CTRL3_SCLK_INV ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL3_SCLK_INV_POS)) /**< CTRL3_SCLK_INV Mask */ 234 #define MXC_V_SPIXR_CTRL3_SCLK_INV_NORMAL ((uint32_t)0x0UL) /**< CTRL3_SCLK_INV_NORMAL Value */ 235 #define MXC_S_SPIXR_CTRL3_SCLK_INV_NORMAL (MXC_V_SPIXR_CTRL3_SCLK_INV_NORMAL << MXC_F_SPIXR_CTRL3_SCLK_INV_POS) /**< CTRL3_SCLK_INV_NORMAL Setting */ 236 237 #define MXC_F_SPIXR_CTRL3_NUMBITS_POS 8 /**< CTRL3_NUMBITS Position */ 238 #define MXC_F_SPIXR_CTRL3_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPIXR_CTRL3_NUMBITS_POS)) /**< CTRL3_NUMBITS Mask */ 239 #define MXC_V_SPIXR_CTRL3_NUMBITS_16BITS ((uint32_t)0x0UL) /**< CTRL3_NUMBITS_16BITS Value */ 240 #define MXC_S_SPIXR_CTRL3_NUMBITS_16BITS (MXC_V_SPIXR_CTRL3_NUMBITS_16BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) /**< CTRL3_NUMBITS_16BITS Setting */ 241 #define MXC_V_SPIXR_CTRL3_NUMBITS_1BITS ((uint32_t)0x1UL) /**< CTRL3_NUMBITS_1BITS Value */ 242 #define MXC_S_SPIXR_CTRL3_NUMBITS_1BITS (MXC_V_SPIXR_CTRL3_NUMBITS_1BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) /**< CTRL3_NUMBITS_1BITS Setting */ 243 #define MXC_V_SPIXR_CTRL3_NUMBITS_2BITS ((uint32_t)0x2UL) /**< CTRL3_NUMBITS_2BITS Value */ 244 #define MXC_S_SPIXR_CTRL3_NUMBITS_2BITS (MXC_V_SPIXR_CTRL3_NUMBITS_2BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) /**< CTRL3_NUMBITS_2BITS Setting */ 245 #define MXC_V_SPIXR_CTRL3_NUMBITS_3BITS ((uint32_t)0x3UL) /**< CTRL3_NUMBITS_3BITS Value */ 246 #define MXC_S_SPIXR_CTRL3_NUMBITS_3BITS (MXC_V_SPIXR_CTRL3_NUMBITS_3BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) /**< CTRL3_NUMBITS_3BITS Setting */ 247 #define MXC_V_SPIXR_CTRL3_NUMBITS_4BITS ((uint32_t)0x4UL) /**< CTRL3_NUMBITS_4BITS Value */ 248 #define MXC_S_SPIXR_CTRL3_NUMBITS_4BITS (MXC_V_SPIXR_CTRL3_NUMBITS_4BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) /**< CTRL3_NUMBITS_4BITS Setting */ 249 #define MXC_V_SPIXR_CTRL3_NUMBITS_5BITS ((uint32_t)0x5UL) /**< CTRL3_NUMBITS_5BITS Value */ 250 #define MXC_S_SPIXR_CTRL3_NUMBITS_5BITS (MXC_V_SPIXR_CTRL3_NUMBITS_5BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) /**< CTRL3_NUMBITS_5BITS Setting */ 251 #define MXC_V_SPIXR_CTRL3_NUMBITS_6BITS ((uint32_t)0x6UL) /**< CTRL3_NUMBITS_6BITS Value */ 252 #define MXC_S_SPIXR_CTRL3_NUMBITS_6BITS (MXC_V_SPIXR_CTRL3_NUMBITS_6BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) /**< CTRL3_NUMBITS_6BITS Setting */ 253 #define MXC_V_SPIXR_CTRL3_NUMBITS_7BITS ((uint32_t)0x7UL) /**< CTRL3_NUMBITS_7BITS Value */ 254 #define MXC_S_SPIXR_CTRL3_NUMBITS_7BITS (MXC_V_SPIXR_CTRL3_NUMBITS_7BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) /**< CTRL3_NUMBITS_7BITS Setting */ 255 #define MXC_V_SPIXR_CTRL3_NUMBITS_8BITS ((uint32_t)0x8UL) /**< CTRL3_NUMBITS_8BITS Value */ 256 #define MXC_S_SPIXR_CTRL3_NUMBITS_8BITS (MXC_V_SPIXR_CTRL3_NUMBITS_8BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) /**< CTRL3_NUMBITS_8BITS Setting */ 257 #define MXC_V_SPIXR_CTRL3_NUMBITS_9BITS ((uint32_t)0x9UL) /**< CTRL3_NUMBITS_9BITS Value */ 258 #define MXC_S_SPIXR_CTRL3_NUMBITS_9BITS (MXC_V_SPIXR_CTRL3_NUMBITS_9BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) /**< CTRL3_NUMBITS_9BITS Setting */ 259 #define MXC_V_SPIXR_CTRL3_NUMBITS_10BITS ((uint32_t)0xAUL) /**< CTRL3_NUMBITS_10BITS Value */ 260 #define MXC_S_SPIXR_CTRL3_NUMBITS_10BITS (MXC_V_SPIXR_CTRL3_NUMBITS_10BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) /**< CTRL3_NUMBITS_10BITS Setting */ 261 #define MXC_V_SPIXR_CTRL3_NUMBITS_11BITS ((uint32_t)0xBUL) /**< CTRL3_NUMBITS_11BITS Value */ 262 #define MXC_S_SPIXR_CTRL3_NUMBITS_11BITS (MXC_V_SPIXR_CTRL3_NUMBITS_11BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) /**< CTRL3_NUMBITS_11BITS Setting */ 263 #define MXC_V_SPIXR_CTRL3_NUMBITS_12BITS ((uint32_t)0xCUL) /**< CTRL3_NUMBITS_12BITS Value */ 264 #define MXC_S_SPIXR_CTRL3_NUMBITS_12BITS (MXC_V_SPIXR_CTRL3_NUMBITS_12BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) /**< CTRL3_NUMBITS_12BITS Setting */ 265 #define MXC_V_SPIXR_CTRL3_NUMBITS_13BITS ((uint32_t)0xDUL) /**< CTRL3_NUMBITS_13BITS Value */ 266 #define MXC_S_SPIXR_CTRL3_NUMBITS_13BITS (MXC_V_SPIXR_CTRL3_NUMBITS_13BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) /**< CTRL3_NUMBITS_13BITS Setting */ 267 #define MXC_V_SPIXR_CTRL3_NUMBITS_14BITS ((uint32_t)0xEUL) /**< CTRL3_NUMBITS_14BITS Value */ 268 #define MXC_S_SPIXR_CTRL3_NUMBITS_14BITS (MXC_V_SPIXR_CTRL3_NUMBITS_14BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) /**< CTRL3_NUMBITS_14BITS Setting */ 269 #define MXC_V_SPIXR_CTRL3_NUMBITS_15BITS ((uint32_t)0xFUL) /**< CTRL3_NUMBITS_15BITS Value */ 270 #define MXC_S_SPIXR_CTRL3_NUMBITS_15BITS (MXC_V_SPIXR_CTRL3_NUMBITS_15BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) /**< CTRL3_NUMBITS_15BITS Setting */ 271 272 #define MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS 12 /**< CTRL3_DATA_WIDTH Position */ 273 #define MXC_F_SPIXR_CTRL3_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS)) /**< CTRL3_DATA_WIDTH Mask */ 274 #define MXC_V_SPIXR_CTRL3_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL3_DATA_WIDTH_MONO Value */ 275 #define MXC_S_SPIXR_CTRL3_DATA_WIDTH_MONO (MXC_V_SPIXR_CTRL3_DATA_WIDTH_MONO << MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS) /**< CTRL3_DATA_WIDTH_MONO Setting */ 276 #define MXC_V_SPIXR_CTRL3_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL3_DATA_WIDTH_DUAL Value */ 277 #define MXC_S_SPIXR_CTRL3_DATA_WIDTH_DUAL (MXC_V_SPIXR_CTRL3_DATA_WIDTH_DUAL << MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS) /**< CTRL3_DATA_WIDTH_DUAL Setting */ 278 #define MXC_V_SPIXR_CTRL3_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL3_DATA_WIDTH_QUAD Value */ 279 #define MXC_S_SPIXR_CTRL3_DATA_WIDTH_QUAD (MXC_V_SPIXR_CTRL3_DATA_WIDTH_QUAD << MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS) /**< CTRL3_DATA_WIDTH_QUAD Setting */ 280 281 #define MXC_F_SPIXR_CTRL3_THREE_WIRE_POS 15 /**< CTRL3_THREE_WIRE Position */ 282 #define MXC_F_SPIXR_CTRL3_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL3_THREE_WIRE_POS)) /**< CTRL3_THREE_WIRE Mask */ 283 #define MXC_V_SPIXR_CTRL3_THREE_WIRE_4WIRE ((uint32_t)0x0UL) /**< CTRL3_THREE_WIRE_4WIRE Value */ 284 #define MXC_S_SPIXR_CTRL3_THREE_WIRE_4WIRE (MXC_V_SPIXR_CTRL3_THREE_WIRE_4WIRE << MXC_F_SPIXR_CTRL3_THREE_WIRE_POS) /**< CTRL3_THREE_WIRE_4WIRE Setting */ 285 #define MXC_V_SPIXR_CTRL3_THREE_WIRE_3WIRE ((uint32_t)0x1UL) /**< CTRL3_THREE_WIRE_3WIRE Value */ 286 #define MXC_S_SPIXR_CTRL3_THREE_WIRE_3WIRE (MXC_V_SPIXR_CTRL3_THREE_WIRE_3WIRE << MXC_F_SPIXR_CTRL3_THREE_WIRE_POS) /**< CTRL3_THREE_WIRE_3WIRE Setting */ 287 288 #define MXC_F_SPIXR_CTRL3_SSPOL_POS 16 /**< CTRL3_SSPOL Position */ 289 #define MXC_F_SPIXR_CTRL3_SSPOL ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL3_SSPOL_POS)) /**< CTRL3_SSPOL Mask */ 290 #define MXC_V_SPIXR_CTRL3_SSPOL_ACTIVELOW ((uint32_t)0x0UL) /**< CTRL3_SSPOL_ACTIVELOW Value */ 291 #define MXC_S_SPIXR_CTRL3_SSPOL_ACTIVELOW (MXC_V_SPIXR_CTRL3_SSPOL_ACTIVELOW << MXC_F_SPIXR_CTRL3_SSPOL_POS) /**< CTRL3_SSPOL_ACTIVELOW Setting */ 292 #define MXC_V_SPIXR_CTRL3_SSPOL_ACTIVEHIGH ((uint32_t)0x1UL) /**< CTRL3_SSPOL_ACTIVEHIGH Value */ 293 #define MXC_S_SPIXR_CTRL3_SSPOL_ACTIVEHIGH (MXC_V_SPIXR_CTRL3_SSPOL_ACTIVEHIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) /**< CTRL3_SSPOL_ACTIVEHIGH Setting */ 294 295 /**@} end of group SPIXR_CTRL3_Register */ 296 297 /** 298 * @ingroup spixr_registers 299 * @defgroup SPIXR_SS_TIME SPIXR_SS_TIME 300 * @brief Register for controlling SPI peripheral. 301 * @{ 302 */ 303 #define MXC_F_SPIXR_SS_TIME_SSACT1_POS 0 /**< SS_TIME_SSACT1 Position */ 304 #define MXC_F_SPIXR_SS_TIME_SSACT1 ((uint32_t)(0xFFUL << MXC_F_SPIXR_SS_TIME_SSACT1_POS)) /**< SS_TIME_SSACT1 Mask */ 305 306 #define MXC_F_SPIXR_SS_TIME_SSACT2_POS 8 /**< SS_TIME_SSACT2 Position */ 307 #define MXC_F_SPIXR_SS_TIME_SSACT2 ((uint32_t)(0xFFUL << MXC_F_SPIXR_SS_TIME_SSACT2_POS)) /**< SS_TIME_SSACT2 Mask */ 308 309 #define MXC_F_SPIXR_SS_TIME_SSINACT_POS 16 /**< SS_TIME_SSINACT Position */ 310 #define MXC_F_SPIXR_SS_TIME_SSINACT ((uint32_t)(0xFFUL << MXC_F_SPIXR_SS_TIME_SSINACT_POS)) /**< SS_TIME_SSINACT Mask */ 311 312 /**@} end of group SPIXR_SS_TIME_Register */ 313 314 /** 315 * @ingroup spixr_registers 316 * @defgroup SPIXR_BRG_CTRL SPIXR_BRG_CTRL 317 * @brief Register for controlling SPI clock rate. 318 * @{ 319 */ 320 #define MXC_F_SPIXR_BRG_CTRL_LO_POS 0 /**< BRG_CTRL_LO Position */ 321 #define MXC_F_SPIXR_BRG_CTRL_LO ((uint32_t)(0xFFUL << MXC_F_SPIXR_BRG_CTRL_LO_POS)) /**< BRG_CTRL_LO Mask */ 322 323 #define MXC_F_SPIXR_BRG_CTRL_HI_POS 8 /**< BRG_CTRL_HI Position */ 324 #define MXC_F_SPIXR_BRG_CTRL_HI ((uint32_t)(0xFFUL << MXC_F_SPIXR_BRG_CTRL_HI_POS)) /**< BRG_CTRL_HI Mask */ 325 326 #define MXC_F_SPIXR_BRG_CTRL_SCALE_POS 16 /**< BRG_CTRL_SCALE Position */ 327 #define MXC_F_SPIXR_BRG_CTRL_SCALE ((uint32_t)(0xFUL << MXC_F_SPIXR_BRG_CTRL_SCALE_POS)) /**< BRG_CTRL_SCALE Mask */ 328 #define MXC_V_SPIXR_BRG_CTRL_SCALE_DIV1 ((uint32_t)0x0UL) /**< BRG_CTRL_SCALE_DIV1 Value */ 329 #define MXC_S_SPIXR_BRG_CTRL_SCALE_DIV1 (MXC_V_SPIXR_BRG_CTRL_SCALE_DIV1 << MXC_F_SPIXR_BRG_CTRL_SCALE_POS) /**< BRG_CTRL_SCALE_DIV1 Setting */ 330 #define MXC_V_SPIXR_BRG_CTRL_SCALE_DIV2 ((uint32_t)0x1UL) /**< BRG_CTRL_SCALE_DIV2 Value */ 331 #define MXC_S_SPIXR_BRG_CTRL_SCALE_DIV2 (MXC_V_SPIXR_BRG_CTRL_SCALE_DIV2 << MXC_F_SPIXR_BRG_CTRL_SCALE_POS) /**< BRG_CTRL_SCALE_DIV2 Setting */ 332 #define MXC_V_SPIXR_BRG_CTRL_SCALE_DIV4 ((uint32_t)0x2UL) /**< BRG_CTRL_SCALE_DIV4 Value */ 333 #define MXC_S_SPIXR_BRG_CTRL_SCALE_DIV4 (MXC_V_SPIXR_BRG_CTRL_SCALE_DIV4 << MXC_F_SPIXR_BRG_CTRL_SCALE_POS) /**< BRG_CTRL_SCALE_DIV4 Setting */ 334 #define MXC_V_SPIXR_BRG_CTRL_SCALE_DIV8 ((uint32_t)0x3UL) /**< BRG_CTRL_SCALE_DIV8 Value */ 335 #define MXC_S_SPIXR_BRG_CTRL_SCALE_DIV8 (MXC_V_SPIXR_BRG_CTRL_SCALE_DIV8 << MXC_F_SPIXR_BRG_CTRL_SCALE_POS) /**< BRG_CTRL_SCALE_DIV8 Setting */ 336 #define MXC_V_SPIXR_BRG_CTRL_SCALE_DIV16 ((uint32_t)0x4UL) /**< BRG_CTRL_SCALE_DIV16 Value */ 337 #define MXC_S_SPIXR_BRG_CTRL_SCALE_DIV16 (MXC_V_SPIXR_BRG_CTRL_SCALE_DIV16 << MXC_F_SPIXR_BRG_CTRL_SCALE_POS) /**< BRG_CTRL_SCALE_DIV16 Setting */ 338 #define MXC_V_SPIXR_BRG_CTRL_SCALE_DIV32 ((uint32_t)0x5UL) /**< BRG_CTRL_SCALE_DIV32 Value */ 339 #define MXC_S_SPIXR_BRG_CTRL_SCALE_DIV32 (MXC_V_SPIXR_BRG_CTRL_SCALE_DIV32 << MXC_F_SPIXR_BRG_CTRL_SCALE_POS) /**< BRG_CTRL_SCALE_DIV32 Setting */ 340 #define MXC_V_SPIXR_BRG_CTRL_SCALE_DIV64 ((uint32_t)0x6UL) /**< BRG_CTRL_SCALE_DIV64 Value */ 341 #define MXC_S_SPIXR_BRG_CTRL_SCALE_DIV64 (MXC_V_SPIXR_BRG_CTRL_SCALE_DIV64 << MXC_F_SPIXR_BRG_CTRL_SCALE_POS) /**< BRG_CTRL_SCALE_DIV64 Setting */ 342 #define MXC_V_SPIXR_BRG_CTRL_SCALE_DIV128 ((uint32_t)0x7UL) /**< BRG_CTRL_SCALE_DIV128 Value */ 343 #define MXC_S_SPIXR_BRG_CTRL_SCALE_DIV128 (MXC_V_SPIXR_BRG_CTRL_SCALE_DIV128 << MXC_F_SPIXR_BRG_CTRL_SCALE_POS) /**< BRG_CTRL_SCALE_DIV128 Setting */ 344 #define MXC_V_SPIXR_BRG_CTRL_SCALE_DIV256 ((uint32_t)0x8UL) /**< BRG_CTRL_SCALE_DIV256 Value */ 345 #define MXC_S_SPIXR_BRG_CTRL_SCALE_DIV256 (MXC_V_SPIXR_BRG_CTRL_SCALE_DIV256 << MXC_F_SPIXR_BRG_CTRL_SCALE_POS) /**< BRG_CTRL_SCALE_DIV256 Setting */ 346 347 /**@} end of group SPIXR_BRG_CTRL_Register */ 348 349 /** 350 * @ingroup spixr_registers 351 * @defgroup SPIXR_DMA SPIXR_DMA 352 * @brief Register for controlling DMA. 353 * @{ 354 */ 355 #define MXC_F_SPIXR_DMA_TX_FIFO_LEVEL_POS 0 /**< DMA_TX_FIFO_LEVEL Position */ 356 #define MXC_F_SPIXR_DMA_TX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPIXR_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */ 357 358 #define MXC_F_SPIXR_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */ 359 #define MXC_F_SPIXR_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */ 360 #define MXC_V_SPIXR_DMA_TX_FIFO_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_FIFO_EN_DIS Value */ 361 #define MXC_S_SPIXR_DMA_TX_FIFO_EN_DIS (MXC_V_SPIXR_DMA_TX_FIFO_EN_DIS << MXC_F_SPIXR_DMA_TX_FIFO_EN_POS) /**< DMA_TX_FIFO_EN_DIS Setting */ 362 #define MXC_V_SPIXR_DMA_TX_FIFO_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_FIFO_EN_EN Value */ 363 #define MXC_S_SPIXR_DMA_TX_FIFO_EN_EN (MXC_V_SPIXR_DMA_TX_FIFO_EN_EN << MXC_F_SPIXR_DMA_TX_FIFO_EN_POS) /**< DMA_TX_FIFO_EN_EN Setting */ 364 365 #define MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS 7 /**< DMA_TX_FIFO_CLEAR Position */ 366 #define MXC_F_SPIXR_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */ 367 #define MXC_V_SPIXR_DMA_TX_FIFO_CLEAR_CLEAR ((uint32_t)0x1UL) /**< DMA_TX_FIFO_CLEAR_CLEAR Value */ 368 #define MXC_S_SPIXR_DMA_TX_FIFO_CLEAR_CLEAR (MXC_V_SPIXR_DMA_TX_FIFO_CLEAR_CLEAR << MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS) /**< DMA_TX_FIFO_CLEAR_CLEAR Setting */ 369 370 #define MXC_F_SPIXR_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */ 371 #define MXC_F_SPIXR_DMA_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPIXR_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */ 372 373 #define MXC_F_SPIXR_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */ 374 #define MXC_F_SPIXR_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */ 375 #define MXC_V_SPIXR_DMA_TX_DMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_DMA_EN_DIS Value */ 376 #define MXC_S_SPIXR_DMA_TX_DMA_EN_DIS (MXC_V_SPIXR_DMA_TX_DMA_EN_DIS << MXC_F_SPIXR_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_DIS Setting */ 377 #define MXC_V_SPIXR_DMA_TX_DMA_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_DMA_EN_EN Value */ 378 #define MXC_S_SPIXR_DMA_TX_DMA_EN_EN (MXC_V_SPIXR_DMA_TX_DMA_EN_EN << MXC_F_SPIXR_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_EN Setting */ 379 380 #define MXC_F_SPIXR_DMA_RX_FIFO_LEVEL_POS 16 /**< DMA_RX_FIFO_LEVEL Position */ 381 #define MXC_F_SPIXR_DMA_RX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPIXR_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */ 382 383 #define MXC_F_SPIXR_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */ 384 #define MXC_F_SPIXR_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */ 385 #define MXC_V_SPIXR_DMA_RX_FIFO_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_FIFO_EN_DIS Value */ 386 #define MXC_S_SPIXR_DMA_RX_FIFO_EN_DIS (MXC_V_SPIXR_DMA_RX_FIFO_EN_DIS << MXC_F_SPIXR_DMA_RX_FIFO_EN_POS) /**< DMA_RX_FIFO_EN_DIS Setting */ 387 #define MXC_V_SPIXR_DMA_RX_FIFO_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_FIFO_EN_EN Value */ 388 #define MXC_S_SPIXR_DMA_RX_FIFO_EN_EN (MXC_V_SPIXR_DMA_RX_FIFO_EN_EN << MXC_F_SPIXR_DMA_RX_FIFO_EN_POS) /**< DMA_RX_FIFO_EN_EN Setting */ 389 390 #define MXC_F_SPIXR_DMA_RX_FIFO_CLEAR_POS 23 /**< DMA_RX_FIFO_CLEAR Position */ 391 #define MXC_F_SPIXR_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */ 392 #define MXC_V_SPIXR_DMA_RX_FIFO_CLEAR_CLEAR ((uint32_t)0x1UL) /**< DMA_RX_FIFO_CLEAR_CLEAR Value */ 393 #define MXC_S_SPIXR_DMA_RX_FIFO_CLEAR_CLEAR (MXC_V_SPIXR_DMA_RX_FIFO_CLEAR_CLEAR << MXC_F_SPIXR_DMA_RX_FIFO_CLEAR_POS) /**< DMA_RX_FIFO_CLEAR_CLEAR Setting */ 394 395 #define MXC_F_SPIXR_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */ 396 #define MXC_F_SPIXR_DMA_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPIXR_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */ 397 398 #define MXC_F_SPIXR_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */ 399 #define MXC_F_SPIXR_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */ 400 #define MXC_V_SPIXR_DMA_RX_DMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_DMA_EN_DIS Value */ 401 #define MXC_S_SPIXR_DMA_RX_DMA_EN_DIS (MXC_V_SPIXR_DMA_RX_DMA_EN_DIS << MXC_F_SPIXR_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_DIS Setting */ 402 #define MXC_V_SPIXR_DMA_RX_DMA_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_DMA_EN_EN Value */ 403 #define MXC_S_SPIXR_DMA_RX_DMA_EN_EN (MXC_V_SPIXR_DMA_RX_DMA_EN_EN << MXC_F_SPIXR_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_EN Setting */ 404 405 /**@} end of group SPIXR_DMA_Register */ 406 407 /** 408 * @ingroup spixr_registers 409 * @defgroup SPIXR_INT_FL SPIXR_INT_FL 410 * @brief Register for reading and clearing interrupt flags. All bits are write 1 to 411 * clear. 412 * @{ 413 */ 414 #define MXC_F_SPIXR_INT_FL_TX_LEVEL_POS 0 /**< INT_FL_TX_LEVEL Position */ 415 #define MXC_F_SPIXR_INT_FL_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_TX_LEVEL_POS)) /**< INT_FL_TX_LEVEL Mask */ 416 #define MXC_V_SPIXR_INT_FL_TX_LEVEL_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_LEVEL_CLEAR Value */ 417 #define MXC_S_SPIXR_INT_FL_TX_LEVEL_CLEAR (MXC_V_SPIXR_INT_FL_TX_LEVEL_CLEAR << MXC_F_SPIXR_INT_FL_TX_LEVEL_POS) /**< INT_FL_TX_LEVEL_CLEAR Setting */ 418 419 #define MXC_F_SPIXR_INT_FL_TX_EMPTY_POS 1 /**< INT_FL_TX_EMPTY Position */ 420 #define MXC_F_SPIXR_INT_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_TX_EMPTY_POS)) /**< INT_FL_TX_EMPTY Mask */ 421 #define MXC_V_SPIXR_INT_FL_TX_EMPTY_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_EMPTY_CLEAR Value */ 422 #define MXC_S_SPIXR_INT_FL_TX_EMPTY_CLEAR (MXC_V_SPIXR_INT_FL_TX_EMPTY_CLEAR << MXC_F_SPIXR_INT_FL_TX_EMPTY_POS) /**< INT_FL_TX_EMPTY_CLEAR Setting */ 423 424 #define MXC_F_SPIXR_INT_FL_RX_LEVEL_POS 2 /**< INT_FL_RX_LEVEL Position */ 425 #define MXC_F_SPIXR_INT_FL_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_RX_LEVEL_POS)) /**< INT_FL_RX_LEVEL Mask */ 426 #define MXC_V_SPIXR_INT_FL_RX_LEVEL_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_LEVEL_CLEAR Value */ 427 #define MXC_S_SPIXR_INT_FL_RX_LEVEL_CLEAR (MXC_V_SPIXR_INT_FL_RX_LEVEL_CLEAR << MXC_F_SPIXR_INT_FL_RX_LEVEL_POS) /**< INT_FL_RX_LEVEL_CLEAR Setting */ 428 429 #define MXC_F_SPIXR_INT_FL_RX_FULL_POS 3 /**< INT_FL_RX_FULL Position */ 430 #define MXC_F_SPIXR_INT_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_RX_FULL_POS)) /**< INT_FL_RX_FULL Mask */ 431 #define MXC_V_SPIXR_INT_FL_RX_FULL_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_FULL_CLEAR Value */ 432 #define MXC_S_SPIXR_INT_FL_RX_FULL_CLEAR (MXC_V_SPIXR_INT_FL_RX_FULL_CLEAR << MXC_F_SPIXR_INT_FL_RX_FULL_POS) /**< INT_FL_RX_FULL_CLEAR Setting */ 433 434 #define MXC_F_SPIXR_INT_FL_SSA_POS 4 /**< INT_FL_SSA Position */ 435 #define MXC_F_SPIXR_INT_FL_SSA ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_SSA_POS)) /**< INT_FL_SSA Mask */ 436 #define MXC_V_SPIXR_INT_FL_SSA_CLEAR ((uint32_t)0x1UL) /**< INT_FL_SSA_CLEAR Value */ 437 #define MXC_S_SPIXR_INT_FL_SSA_CLEAR (MXC_V_SPIXR_INT_FL_SSA_CLEAR << MXC_F_SPIXR_INT_FL_SSA_POS) /**< INT_FL_SSA_CLEAR Setting */ 438 439 #define MXC_F_SPIXR_INT_FL_SSD_POS 5 /**< INT_FL_SSD Position */ 440 #define MXC_F_SPIXR_INT_FL_SSD ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_SSD_POS)) /**< INT_FL_SSD Mask */ 441 #define MXC_V_SPIXR_INT_FL_SSD_CLEAR ((uint32_t)0x1UL) /**< INT_FL_SSD_CLEAR Value */ 442 #define MXC_S_SPIXR_INT_FL_SSD_CLEAR (MXC_V_SPIXR_INT_FL_SSD_CLEAR << MXC_F_SPIXR_INT_FL_SSD_POS) /**< INT_FL_SSD_CLEAR Setting */ 443 444 #define MXC_F_SPIXR_INT_FL_FAULT_POS 8 /**< INT_FL_FAULT Position */ 445 #define MXC_F_SPIXR_INT_FL_FAULT ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_FAULT_POS)) /**< INT_FL_FAULT Mask */ 446 #define MXC_V_SPIXR_INT_FL_FAULT_CLEAR ((uint32_t)0x1UL) /**< INT_FL_FAULT_CLEAR Value */ 447 #define MXC_S_SPIXR_INT_FL_FAULT_CLEAR (MXC_V_SPIXR_INT_FL_FAULT_CLEAR << MXC_F_SPIXR_INT_FL_FAULT_POS) /**< INT_FL_FAULT_CLEAR Setting */ 448 449 #define MXC_F_SPIXR_INT_FL_ABORT_POS 9 /**< INT_FL_ABORT Position */ 450 #define MXC_F_SPIXR_INT_FL_ABORT ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_ABORT_POS)) /**< INT_FL_ABORT Mask */ 451 #define MXC_V_SPIXR_INT_FL_ABORT_CLEAR ((uint32_t)0x1UL) /**< INT_FL_ABORT_CLEAR Value */ 452 #define MXC_S_SPIXR_INT_FL_ABORT_CLEAR (MXC_V_SPIXR_INT_FL_ABORT_CLEAR << MXC_F_SPIXR_INT_FL_ABORT_POS) /**< INT_FL_ABORT_CLEAR Setting */ 453 454 #define MXC_F_SPIXR_INT_FL_M_DONE_POS 11 /**< INT_FL_M_DONE Position */ 455 #define MXC_F_SPIXR_INT_FL_M_DONE ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_M_DONE_POS)) /**< INT_FL_M_DONE Mask */ 456 #define MXC_V_SPIXR_INT_FL_M_DONE_CLEAR ((uint32_t)0x1UL) /**< INT_FL_M_DONE_CLEAR Value */ 457 #define MXC_S_SPIXR_INT_FL_M_DONE_CLEAR (MXC_V_SPIXR_INT_FL_M_DONE_CLEAR << MXC_F_SPIXR_INT_FL_M_DONE_POS) /**< INT_FL_M_DONE_CLEAR Setting */ 458 459 #define MXC_F_SPIXR_INT_FL_TX_OVR_POS 12 /**< INT_FL_TX_OVR Position */ 460 #define MXC_F_SPIXR_INT_FL_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_TX_OVR_POS)) /**< INT_FL_TX_OVR Mask */ 461 #define MXC_V_SPIXR_INT_FL_TX_OVR_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_OVR_CLEAR Value */ 462 #define MXC_S_SPIXR_INT_FL_TX_OVR_CLEAR (MXC_V_SPIXR_INT_FL_TX_OVR_CLEAR << MXC_F_SPIXR_INT_FL_TX_OVR_POS) /**< INT_FL_TX_OVR_CLEAR Setting */ 463 464 #define MXC_F_SPIXR_INT_FL_TX_UND_POS 13 /**< INT_FL_TX_UND Position */ 465 #define MXC_F_SPIXR_INT_FL_TX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_TX_UND_POS)) /**< INT_FL_TX_UND Mask */ 466 #define MXC_V_SPIXR_INT_FL_TX_UND_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_UND_CLEAR Value */ 467 #define MXC_S_SPIXR_INT_FL_TX_UND_CLEAR (MXC_V_SPIXR_INT_FL_TX_UND_CLEAR << MXC_F_SPIXR_INT_FL_TX_UND_POS) /**< INT_FL_TX_UND_CLEAR Setting */ 468 469 #define MXC_F_SPIXR_INT_FL_RX_OVR_POS 14 /**< INT_FL_RX_OVR Position */ 470 #define MXC_F_SPIXR_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */ 471 #define MXC_V_SPIXR_INT_FL_RX_OVR_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_OVR_CLEAR Value */ 472 #define MXC_S_SPIXR_INT_FL_RX_OVR_CLEAR (MXC_V_SPIXR_INT_FL_RX_OVR_CLEAR << MXC_F_SPIXR_INT_FL_RX_OVR_POS) /**< INT_FL_RX_OVR_CLEAR Setting */ 473 474 #define MXC_F_SPIXR_INT_FL_RX_UND_POS 15 /**< INT_FL_RX_UND Position */ 475 #define MXC_F_SPIXR_INT_FL_RX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_RX_UND_POS)) /**< INT_FL_RX_UND Mask */ 476 #define MXC_V_SPIXR_INT_FL_RX_UND_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_UND_CLEAR Value */ 477 #define MXC_S_SPIXR_INT_FL_RX_UND_CLEAR (MXC_V_SPIXR_INT_FL_RX_UND_CLEAR << MXC_F_SPIXR_INT_FL_RX_UND_POS) /**< INT_FL_RX_UND_CLEAR Setting */ 478 479 /**@} end of group SPIXR_INT_FL_Register */ 480 481 /** 482 * @ingroup spixr_registers 483 * @defgroup SPIXR_INT_EN SPIXR_INT_EN 484 * @brief Register for enabling interrupts. 485 * @{ 486 */ 487 #define MXC_F_SPIXR_INT_EN_TX_LEVEL_POS 0 /**< INT_EN_TX_LEVEL Position */ 488 #define MXC_F_SPIXR_INT_EN_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_TX_LEVEL_POS)) /**< INT_EN_TX_LEVEL Mask */ 489 #define MXC_V_SPIXR_INT_EN_TX_LEVEL_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_LEVEL_DIS Value */ 490 #define MXC_S_SPIXR_INT_EN_TX_LEVEL_DIS (MXC_V_SPIXR_INT_EN_TX_LEVEL_DIS << MXC_F_SPIXR_INT_EN_TX_LEVEL_POS) /**< INT_EN_TX_LEVEL_DIS Setting */ 491 #define MXC_V_SPIXR_INT_EN_TX_LEVEL_EN ((uint32_t)0x1UL) /**< INT_EN_TX_LEVEL_EN Value */ 492 #define MXC_S_SPIXR_INT_EN_TX_LEVEL_EN (MXC_V_SPIXR_INT_EN_TX_LEVEL_EN << MXC_F_SPIXR_INT_EN_TX_LEVEL_POS) /**< INT_EN_TX_LEVEL_EN Setting */ 493 494 #define MXC_F_SPIXR_INT_EN_TX_EMPTY_POS 1 /**< INT_EN_TX_EMPTY Position */ 495 #define MXC_F_SPIXR_INT_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_TX_EMPTY_POS)) /**< INT_EN_TX_EMPTY Mask */ 496 #define MXC_V_SPIXR_INT_EN_TX_EMPTY_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_EMPTY_DIS Value */ 497 #define MXC_S_SPIXR_INT_EN_TX_EMPTY_DIS (MXC_V_SPIXR_INT_EN_TX_EMPTY_DIS << MXC_F_SPIXR_INT_EN_TX_EMPTY_POS) /**< INT_EN_TX_EMPTY_DIS Setting */ 498 #define MXC_V_SPIXR_INT_EN_TX_EMPTY_EN ((uint32_t)0x1UL) /**< INT_EN_TX_EMPTY_EN Value */ 499 #define MXC_S_SPIXR_INT_EN_TX_EMPTY_EN (MXC_V_SPIXR_INT_EN_TX_EMPTY_EN << MXC_F_SPIXR_INT_EN_TX_EMPTY_POS) /**< INT_EN_TX_EMPTY_EN Setting */ 500 501 #define MXC_F_SPIXR_INT_EN_RX_LEVEL_POS 2 /**< INT_EN_RX_LEVEL Position */ 502 #define MXC_F_SPIXR_INT_EN_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_RX_LEVEL_POS)) /**< INT_EN_RX_LEVEL Mask */ 503 #define MXC_V_SPIXR_INT_EN_RX_LEVEL_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_LEVEL_DIS Value */ 504 #define MXC_S_SPIXR_INT_EN_RX_LEVEL_DIS (MXC_V_SPIXR_INT_EN_RX_LEVEL_DIS << MXC_F_SPIXR_INT_EN_RX_LEVEL_POS) /**< INT_EN_RX_LEVEL_DIS Setting */ 505 #define MXC_V_SPIXR_INT_EN_RX_LEVEL_EN ((uint32_t)0x1UL) /**< INT_EN_RX_LEVEL_EN Value */ 506 #define MXC_S_SPIXR_INT_EN_RX_LEVEL_EN (MXC_V_SPIXR_INT_EN_RX_LEVEL_EN << MXC_F_SPIXR_INT_EN_RX_LEVEL_POS) /**< INT_EN_RX_LEVEL_EN Setting */ 507 508 #define MXC_F_SPIXR_INT_EN_RX_FULL_POS 3 /**< INT_EN_RX_FULL Position */ 509 #define MXC_F_SPIXR_INT_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_RX_FULL_POS)) /**< INT_EN_RX_FULL Mask */ 510 #define MXC_V_SPIXR_INT_EN_RX_FULL_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_FULL_DIS Value */ 511 #define MXC_S_SPIXR_INT_EN_RX_FULL_DIS (MXC_V_SPIXR_INT_EN_RX_FULL_DIS << MXC_F_SPIXR_INT_EN_RX_FULL_POS) /**< INT_EN_RX_FULL_DIS Setting */ 512 #define MXC_V_SPIXR_INT_EN_RX_FULL_EN ((uint32_t)0x1UL) /**< INT_EN_RX_FULL_EN Value */ 513 #define MXC_S_SPIXR_INT_EN_RX_FULL_EN (MXC_V_SPIXR_INT_EN_RX_FULL_EN << MXC_F_SPIXR_INT_EN_RX_FULL_POS) /**< INT_EN_RX_FULL_EN Setting */ 514 515 #define MXC_F_SPIXR_INT_EN_SSA_POS 4 /**< INT_EN_SSA Position */ 516 #define MXC_F_SPIXR_INT_EN_SSA ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_SSA_POS)) /**< INT_EN_SSA Mask */ 517 #define MXC_V_SPIXR_INT_EN_SSA_DIS ((uint32_t)0x0UL) /**< INT_EN_SSA_DIS Value */ 518 #define MXC_S_SPIXR_INT_EN_SSA_DIS (MXC_V_SPIXR_INT_EN_SSA_DIS << MXC_F_SPIXR_INT_EN_SSA_POS) /**< INT_EN_SSA_DIS Setting */ 519 #define MXC_V_SPIXR_INT_EN_SSA_EN ((uint32_t)0x1UL) /**< INT_EN_SSA_EN Value */ 520 #define MXC_S_SPIXR_INT_EN_SSA_EN (MXC_V_SPIXR_INT_EN_SSA_EN << MXC_F_SPIXR_INT_EN_SSA_POS) /**< INT_EN_SSA_EN Setting */ 521 522 #define MXC_F_SPIXR_INT_EN_SSD_POS 5 /**< INT_EN_SSD Position */ 523 #define MXC_F_SPIXR_INT_EN_SSD ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_SSD_POS)) /**< INT_EN_SSD Mask */ 524 #define MXC_V_SPIXR_INT_EN_SSD_DIS ((uint32_t)0x0UL) /**< INT_EN_SSD_DIS Value */ 525 #define MXC_S_SPIXR_INT_EN_SSD_DIS (MXC_V_SPIXR_INT_EN_SSD_DIS << MXC_F_SPIXR_INT_EN_SSD_POS) /**< INT_EN_SSD_DIS Setting */ 526 #define MXC_V_SPIXR_INT_EN_SSD_EN ((uint32_t)0x1UL) /**< INT_EN_SSD_EN Value */ 527 #define MXC_S_SPIXR_INT_EN_SSD_EN (MXC_V_SPIXR_INT_EN_SSD_EN << MXC_F_SPIXR_INT_EN_SSD_POS) /**< INT_EN_SSD_EN Setting */ 528 529 #define MXC_F_SPIXR_INT_EN_FAULT_POS 8 /**< INT_EN_FAULT Position */ 530 #define MXC_F_SPIXR_INT_EN_FAULT ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_FAULT_POS)) /**< INT_EN_FAULT Mask */ 531 #define MXC_V_SPIXR_INT_EN_FAULT_DIS ((uint32_t)0x0UL) /**< INT_EN_FAULT_DIS Value */ 532 #define MXC_S_SPIXR_INT_EN_FAULT_DIS (MXC_V_SPIXR_INT_EN_FAULT_DIS << MXC_F_SPIXR_INT_EN_FAULT_POS) /**< INT_EN_FAULT_DIS Setting */ 533 #define MXC_V_SPIXR_INT_EN_FAULT_EN ((uint32_t)0x1UL) /**< INT_EN_FAULT_EN Value */ 534 #define MXC_S_SPIXR_INT_EN_FAULT_EN (MXC_V_SPIXR_INT_EN_FAULT_EN << MXC_F_SPIXR_INT_EN_FAULT_POS) /**< INT_EN_FAULT_EN Setting */ 535 536 #define MXC_F_SPIXR_INT_EN_ABORT_POS 9 /**< INT_EN_ABORT Position */ 537 #define MXC_F_SPIXR_INT_EN_ABORT ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_ABORT_POS)) /**< INT_EN_ABORT Mask */ 538 #define MXC_V_SPIXR_INT_EN_ABORT_DIS ((uint32_t)0x0UL) /**< INT_EN_ABORT_DIS Value */ 539 #define MXC_S_SPIXR_INT_EN_ABORT_DIS (MXC_V_SPIXR_INT_EN_ABORT_DIS << MXC_F_SPIXR_INT_EN_ABORT_POS) /**< INT_EN_ABORT_DIS Setting */ 540 #define MXC_V_SPIXR_INT_EN_ABORT_EN ((uint32_t)0x1UL) /**< INT_EN_ABORT_EN Value */ 541 #define MXC_S_SPIXR_INT_EN_ABORT_EN (MXC_V_SPIXR_INT_EN_ABORT_EN << MXC_F_SPIXR_INT_EN_ABORT_POS) /**< INT_EN_ABORT_EN Setting */ 542 543 #define MXC_F_SPIXR_INT_EN_M_DONE_POS 11 /**< INT_EN_M_DONE Position */ 544 #define MXC_F_SPIXR_INT_EN_M_DONE ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_M_DONE_POS)) /**< INT_EN_M_DONE Mask */ 545 #define MXC_V_SPIXR_INT_EN_M_DONE_DIS ((uint32_t)0x0UL) /**< INT_EN_M_DONE_DIS Value */ 546 #define MXC_S_SPIXR_INT_EN_M_DONE_DIS (MXC_V_SPIXR_INT_EN_M_DONE_DIS << MXC_F_SPIXR_INT_EN_M_DONE_POS) /**< INT_EN_M_DONE_DIS Setting */ 547 #define MXC_V_SPIXR_INT_EN_M_DONE_EN ((uint32_t)0x1UL) /**< INT_EN_M_DONE_EN Value */ 548 #define MXC_S_SPIXR_INT_EN_M_DONE_EN (MXC_V_SPIXR_INT_EN_M_DONE_EN << MXC_F_SPIXR_INT_EN_M_DONE_POS) /**< INT_EN_M_DONE_EN Setting */ 549 550 #define MXC_F_SPIXR_INT_EN_TX_OVR_POS 12 /**< INT_EN_TX_OVR Position */ 551 #define MXC_F_SPIXR_INT_EN_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_TX_OVR_POS)) /**< INT_EN_TX_OVR Mask */ 552 #define MXC_V_SPIXR_INT_EN_TX_OVR_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_OVR_DIS Value */ 553 #define MXC_S_SPIXR_INT_EN_TX_OVR_DIS (MXC_V_SPIXR_INT_EN_TX_OVR_DIS << MXC_F_SPIXR_INT_EN_TX_OVR_POS) /**< INT_EN_TX_OVR_DIS Setting */ 554 #define MXC_V_SPIXR_INT_EN_TX_OVR_EN ((uint32_t)0x1UL) /**< INT_EN_TX_OVR_EN Value */ 555 #define MXC_S_SPIXR_INT_EN_TX_OVR_EN (MXC_V_SPIXR_INT_EN_TX_OVR_EN << MXC_F_SPIXR_INT_EN_TX_OVR_POS) /**< INT_EN_TX_OVR_EN Setting */ 556 557 #define MXC_F_SPIXR_INT_EN_TX_UND_POS 13 /**< INT_EN_TX_UND Position */ 558 #define MXC_F_SPIXR_INT_EN_TX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_TX_UND_POS)) /**< INT_EN_TX_UND Mask */ 559 #define MXC_V_SPIXR_INT_EN_TX_UND_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_UND_DIS Value */ 560 #define MXC_S_SPIXR_INT_EN_TX_UND_DIS (MXC_V_SPIXR_INT_EN_TX_UND_DIS << MXC_F_SPIXR_INT_EN_TX_UND_POS) /**< INT_EN_TX_UND_DIS Setting */ 561 #define MXC_V_SPIXR_INT_EN_TX_UND_EN ((uint32_t)0x1UL) /**< INT_EN_TX_UND_EN Value */ 562 #define MXC_S_SPIXR_INT_EN_TX_UND_EN (MXC_V_SPIXR_INT_EN_TX_UND_EN << MXC_F_SPIXR_INT_EN_TX_UND_POS) /**< INT_EN_TX_UND_EN Setting */ 563 564 #define MXC_F_SPIXR_INT_EN_RX_OVR_POS 14 /**< INT_EN_RX_OVR Position */ 565 #define MXC_F_SPIXR_INT_EN_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_RX_OVR_POS)) /**< INT_EN_RX_OVR Mask */ 566 #define MXC_V_SPIXR_INT_EN_RX_OVR_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_OVR_DIS Value */ 567 #define MXC_S_SPIXR_INT_EN_RX_OVR_DIS (MXC_V_SPIXR_INT_EN_RX_OVR_DIS << MXC_F_SPIXR_INT_EN_RX_OVR_POS) /**< INT_EN_RX_OVR_DIS Setting */ 568 #define MXC_V_SPIXR_INT_EN_RX_OVR_EN ((uint32_t)0x1UL) /**< INT_EN_RX_OVR_EN Value */ 569 #define MXC_S_SPIXR_INT_EN_RX_OVR_EN (MXC_V_SPIXR_INT_EN_RX_OVR_EN << MXC_F_SPIXR_INT_EN_RX_OVR_POS) /**< INT_EN_RX_OVR_EN Setting */ 570 571 #define MXC_F_SPIXR_INT_EN_RX_UND_POS 15 /**< INT_EN_RX_UND Position */ 572 #define MXC_F_SPIXR_INT_EN_RX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_RX_UND_POS)) /**< INT_EN_RX_UND Mask */ 573 #define MXC_V_SPIXR_INT_EN_RX_UND_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_UND_DIS Value */ 574 #define MXC_S_SPIXR_INT_EN_RX_UND_DIS (MXC_V_SPIXR_INT_EN_RX_UND_DIS << MXC_F_SPIXR_INT_EN_RX_UND_POS) /**< INT_EN_RX_UND_DIS Setting */ 575 #define MXC_V_SPIXR_INT_EN_RX_UND_EN ((uint32_t)0x1UL) /**< INT_EN_RX_UND_EN Value */ 576 #define MXC_S_SPIXR_INT_EN_RX_UND_EN (MXC_V_SPIXR_INT_EN_RX_UND_EN << MXC_F_SPIXR_INT_EN_RX_UND_POS) /**< INT_EN_RX_UND_EN Setting */ 577 578 /**@} end of group SPIXR_INT_EN_Register */ 579 580 /** 581 * @ingroup spixr_registers 582 * @defgroup SPIXR_WAKE_FL SPIXR_WAKE_FL 583 * @brief Register for wake up flags. All bits in this register are write 1 to clear. 584 * @{ 585 */ 586 #define MXC_F_SPIXR_WAKE_FL_TX_LEVEL_POS 0 /**< WAKE_FL_TX_LEVEL Position */ 587 #define MXC_F_SPIXR_WAKE_FL_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_FL_TX_LEVEL_POS)) /**< WAKE_FL_TX_LEVEL Mask */ 588 #define MXC_V_SPIXR_WAKE_FL_TX_LEVEL_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_TX_LEVEL_CLEAR Value */ 589 #define MXC_S_SPIXR_WAKE_FL_TX_LEVEL_CLEAR (MXC_V_SPIXR_WAKE_FL_TX_LEVEL_CLEAR << MXC_F_SPIXR_WAKE_FL_TX_LEVEL_POS) /**< WAKE_FL_TX_LEVEL_CLEAR Setting */ 590 591 #define MXC_F_SPIXR_WAKE_FL_TX_EMPTY_POS 1 /**< WAKE_FL_TX_EMPTY Position */ 592 #define MXC_F_SPIXR_WAKE_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_FL_TX_EMPTY_POS)) /**< WAKE_FL_TX_EMPTY Mask */ 593 #define MXC_V_SPIXR_WAKE_FL_TX_EMPTY_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_TX_EMPTY_CLEAR Value */ 594 #define MXC_S_SPIXR_WAKE_FL_TX_EMPTY_CLEAR (MXC_V_SPIXR_WAKE_FL_TX_EMPTY_CLEAR << MXC_F_SPIXR_WAKE_FL_TX_EMPTY_POS) /**< WAKE_FL_TX_EMPTY_CLEAR Setting */ 595 596 #define MXC_F_SPIXR_WAKE_FL_RX_LEVEL_POS 2 /**< WAKE_FL_RX_LEVEL Position */ 597 #define MXC_F_SPIXR_WAKE_FL_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_FL_RX_LEVEL_POS)) /**< WAKE_FL_RX_LEVEL Mask */ 598 #define MXC_V_SPIXR_WAKE_FL_RX_LEVEL_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_RX_LEVEL_CLEAR Value */ 599 #define MXC_S_SPIXR_WAKE_FL_RX_LEVEL_CLEAR (MXC_V_SPIXR_WAKE_FL_RX_LEVEL_CLEAR << MXC_F_SPIXR_WAKE_FL_RX_LEVEL_POS) /**< WAKE_FL_RX_LEVEL_CLEAR Setting */ 600 601 #define MXC_F_SPIXR_WAKE_FL_RX_FULL_POS 3 /**< WAKE_FL_RX_FULL Position */ 602 #define MXC_F_SPIXR_WAKE_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_FL_RX_FULL_POS)) /**< WAKE_FL_RX_FULL Mask */ 603 #define MXC_V_SPIXR_WAKE_FL_RX_FULL_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_RX_FULL_CLEAR Value */ 604 #define MXC_S_SPIXR_WAKE_FL_RX_FULL_CLEAR (MXC_V_SPIXR_WAKE_FL_RX_FULL_CLEAR << MXC_F_SPIXR_WAKE_FL_RX_FULL_POS) /**< WAKE_FL_RX_FULL_CLEAR Setting */ 605 606 /**@} end of group SPIXR_WAKE_FL_Register */ 607 608 /** 609 * @ingroup spixr_registers 610 * @defgroup SPIXR_WAKE_EN SPIXR_WAKE_EN 611 * @brief Register for wake up enable. 612 * @{ 613 */ 614 #define MXC_F_SPIXR_WAKE_EN_TX_LEVEL_POS 0 /**< WAKE_EN_TX_LEVEL Position */ 615 #define MXC_F_SPIXR_WAKE_EN_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_EN_TX_LEVEL_POS)) /**< WAKE_EN_TX_LEVEL Mask */ 616 #define MXC_V_SPIXR_WAKE_EN_TX_LEVEL_DIS ((uint32_t)0x0UL) /**< WAKE_EN_TX_LEVEL_DIS Value */ 617 #define MXC_S_SPIXR_WAKE_EN_TX_LEVEL_DIS (MXC_V_SPIXR_WAKE_EN_TX_LEVEL_DIS << MXC_F_SPIXR_WAKE_EN_TX_LEVEL_POS) /**< WAKE_EN_TX_LEVEL_DIS Setting */ 618 #define MXC_V_SPIXR_WAKE_EN_TX_LEVEL_EN ((uint32_t)0x1UL) /**< WAKE_EN_TX_LEVEL_EN Value */ 619 #define MXC_S_SPIXR_WAKE_EN_TX_LEVEL_EN (MXC_V_SPIXR_WAKE_EN_TX_LEVEL_EN << MXC_F_SPIXR_WAKE_EN_TX_LEVEL_POS) /**< WAKE_EN_TX_LEVEL_EN Setting */ 620 621 #define MXC_F_SPIXR_WAKE_EN_TX_EMPTY_POS 1 /**< WAKE_EN_TX_EMPTY Position */ 622 #define MXC_F_SPIXR_WAKE_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_EN_TX_EMPTY_POS)) /**< WAKE_EN_TX_EMPTY Mask */ 623 #define MXC_V_SPIXR_WAKE_EN_TX_EMPTY_DIS ((uint32_t)0x0UL) /**< WAKE_EN_TX_EMPTY_DIS Value */ 624 #define MXC_S_SPIXR_WAKE_EN_TX_EMPTY_DIS (MXC_V_SPIXR_WAKE_EN_TX_EMPTY_DIS << MXC_F_SPIXR_WAKE_EN_TX_EMPTY_POS) /**< WAKE_EN_TX_EMPTY_DIS Setting */ 625 #define MXC_V_SPIXR_WAKE_EN_TX_EMPTY_EN ((uint32_t)0x1UL) /**< WAKE_EN_TX_EMPTY_EN Value */ 626 #define MXC_S_SPIXR_WAKE_EN_TX_EMPTY_EN (MXC_V_SPIXR_WAKE_EN_TX_EMPTY_EN << MXC_F_SPIXR_WAKE_EN_TX_EMPTY_POS) /**< WAKE_EN_TX_EMPTY_EN Setting */ 627 628 #define MXC_F_SPIXR_WAKE_EN_RX_LEVEL_POS 2 /**< WAKE_EN_RX_LEVEL Position */ 629 #define MXC_F_SPIXR_WAKE_EN_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_EN_RX_LEVEL_POS)) /**< WAKE_EN_RX_LEVEL Mask */ 630 #define MXC_V_SPIXR_WAKE_EN_RX_LEVEL_DIS ((uint32_t)0x0UL) /**< WAKE_EN_RX_LEVEL_DIS Value */ 631 #define MXC_S_SPIXR_WAKE_EN_RX_LEVEL_DIS (MXC_V_SPIXR_WAKE_EN_RX_LEVEL_DIS << MXC_F_SPIXR_WAKE_EN_RX_LEVEL_POS) /**< WAKE_EN_RX_LEVEL_DIS Setting */ 632 #define MXC_V_SPIXR_WAKE_EN_RX_LEVEL_EN ((uint32_t)0x1UL) /**< WAKE_EN_RX_LEVEL_EN Value */ 633 #define MXC_S_SPIXR_WAKE_EN_RX_LEVEL_EN (MXC_V_SPIXR_WAKE_EN_RX_LEVEL_EN << MXC_F_SPIXR_WAKE_EN_RX_LEVEL_POS) /**< WAKE_EN_RX_LEVEL_EN Setting */ 634 635 #define MXC_F_SPIXR_WAKE_EN_RX_FULL_POS 3 /**< WAKE_EN_RX_FULL Position */ 636 #define MXC_F_SPIXR_WAKE_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_EN_RX_FULL_POS)) /**< WAKE_EN_RX_FULL Mask */ 637 #define MXC_V_SPIXR_WAKE_EN_RX_FULL_DIS ((uint32_t)0x0UL) /**< WAKE_EN_RX_FULL_DIS Value */ 638 #define MXC_S_SPIXR_WAKE_EN_RX_FULL_DIS (MXC_V_SPIXR_WAKE_EN_RX_FULL_DIS << MXC_F_SPIXR_WAKE_EN_RX_FULL_POS) /**< WAKE_EN_RX_FULL_DIS Setting */ 639 #define MXC_V_SPIXR_WAKE_EN_RX_FULL_EN ((uint32_t)0x1UL) /**< WAKE_EN_RX_FULL_EN Value */ 640 #define MXC_S_SPIXR_WAKE_EN_RX_FULL_EN (MXC_V_SPIXR_WAKE_EN_RX_FULL_EN << MXC_F_SPIXR_WAKE_EN_RX_FULL_POS) /**< WAKE_EN_RX_FULL_EN Setting */ 641 642 /**@} end of group SPIXR_WAKE_EN_Register */ 643 644 /** 645 * @ingroup spixr_registers 646 * @defgroup SPIXR_STAT SPIXR_STAT 647 * @brief SPI Status register. 648 * @{ 649 */ 650 #define MXC_F_SPIXR_STAT_BUSY_POS 0 /**< STAT_BUSY Position */ 651 #define MXC_F_SPIXR_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPIXR_STAT_BUSY_POS)) /**< STAT_BUSY Mask */ 652 #define MXC_V_SPIXR_STAT_BUSY_NOTACTIVE ((uint32_t)0x0UL) /**< STAT_BUSY_NOTACTIVE Value */ 653 #define MXC_S_SPIXR_STAT_BUSY_NOTACTIVE (MXC_V_SPIXR_STAT_BUSY_NOTACTIVE << MXC_F_SPIXR_STAT_BUSY_POS) /**< STAT_BUSY_NOTACTIVE Setting */ 654 #define MXC_V_SPIXR_STAT_BUSY_ACTIVE ((uint32_t)0x1UL) /**< STAT_BUSY_ACTIVE Value */ 655 #define MXC_S_SPIXR_STAT_BUSY_ACTIVE (MXC_V_SPIXR_STAT_BUSY_ACTIVE << MXC_F_SPIXR_STAT_BUSY_POS) /**< STAT_BUSY_ACTIVE Setting */ 656 657 /**@} end of group SPIXR_STAT_Register */ 658 659 /** 660 * @ingroup spixr_registers 661 * @defgroup SPIXR_XMEM_CTRL SPIXR_XMEM_CTRL 662 * @brief Register to control external memory. 663 * @{ 664 */ 665 #define MXC_F_SPIXR_XMEM_CTRL_XMEM_RD_CMD_POS 0 /**< XMEM_CTRL_XMEM_RD_CMD Position */ 666 #define MXC_F_SPIXR_XMEM_CTRL_XMEM_RD_CMD ((uint32_t)(0xFFUL << MXC_F_SPIXR_XMEM_CTRL_XMEM_RD_CMD_POS)) /**< XMEM_CTRL_XMEM_RD_CMD Mask */ 667 668 #define MXC_F_SPIXR_XMEM_CTRL_XMEM_WR_CMD_POS 8 /**< XMEM_CTRL_XMEM_WR_CMD Position */ 669 #define MXC_F_SPIXR_XMEM_CTRL_XMEM_WR_CMD ((uint32_t)(0xFFUL << MXC_F_SPIXR_XMEM_CTRL_XMEM_WR_CMD_POS)) /**< XMEM_CTRL_XMEM_WR_CMD Mask */ 670 671 #define MXC_F_SPIXR_XMEM_CTRL_XMEM_DCLKS_POS 16 /**< XMEM_CTRL_XMEM_DCLKS Position */ 672 #define MXC_F_SPIXR_XMEM_CTRL_XMEM_DCLKS ((uint32_t)(0xFFUL << MXC_F_SPIXR_XMEM_CTRL_XMEM_DCLKS_POS)) /**< XMEM_CTRL_XMEM_DCLKS Mask */ 673 674 #define MXC_F_SPIXR_XMEM_CTRL_XMEM_EN_POS 31 /**< XMEM_CTRL_XMEM_EN Position */ 675 #define MXC_F_SPIXR_XMEM_CTRL_XMEM_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_XMEM_CTRL_XMEM_EN_POS)) /**< XMEM_CTRL_XMEM_EN Mask */ 676 #define MXC_V_SPIXR_XMEM_CTRL_XMEM_EN_DIS ((uint32_t)0x0UL) /**< XMEM_CTRL_XMEM_EN_DIS Value */ 677 #define MXC_S_SPIXR_XMEM_CTRL_XMEM_EN_DIS (MXC_V_SPIXR_XMEM_CTRL_XMEM_EN_DIS << MXC_F_SPIXR_XMEM_CTRL_XMEM_EN_POS) /**< XMEM_CTRL_XMEM_EN_DIS Setting */ 678 #define MXC_V_SPIXR_XMEM_CTRL_XMEM_EN_EN ((uint32_t)0x1UL) /**< XMEM_CTRL_XMEM_EN_EN Value */ 679 #define MXC_S_SPIXR_XMEM_CTRL_XMEM_EN_EN (MXC_V_SPIXR_XMEM_CTRL_XMEM_EN_EN << MXC_F_SPIXR_XMEM_CTRL_XMEM_EN_POS) /**< XMEM_CTRL_XMEM_EN_EN Setting */ 680 681 /**@} end of group SPIXR_XMEM_CTRL_Register */ 682 683 #ifdef __cplusplus 684 } 685 #endif 686 687 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SPIXR_REGS_H_ 688
