1 /** 2 * @file spixfc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPIXFC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup spixfc_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SPIXFC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SPIXFC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup spixfc 67 * @defgroup spixfc_registers SPIXFC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SPIXFC Peripheral Module. 69 * @details SPI XiP Flash Configuration Controller 70 */ 71 72 /** 73 * @ingroup spixfc_registers 74 * Structure type to access the SPIXFC Registers. 75 */ 76 typedef struct { 77 __IO uint32_t cfg; /**< <tt>\b 0x00:</tt> SPIXFC CFG Register */ 78 __IO uint32_t ss_pol; /**< <tt>\b 0x04:</tt> SPIXFC SS_POL Register */ 79 __IO uint32_t gen_ctrl; /**< <tt>\b 0x08:</tt> SPIXFC GEN_CTRL Register */ 80 __IO uint32_t fifo_ctrl; /**< <tt>\b 0x0C:</tt> SPIXFC FIFO_CTRL Register */ 81 __IO uint32_t sp_ctrl; /**< <tt>\b 0x10:</tt> SPIXFC SP_CTRL Register */ 82 __IO uint32_t int_fl; /**< <tt>\b 0x14:</tt> SPIXFC INT_FL Register */ 83 __IO uint32_t int_en; /**< <tt>\b 0x18:</tt> SPIXFC INT_EN Register */ 84 } mxc_spixfc_regs_t; 85 86 /* Register offsets for module SPIXFC */ 87 /** 88 * @ingroup spixfc_registers 89 * @defgroup SPIXFC_Register_Offsets Register Offsets 90 * @brief SPIXFC Peripheral Register Offsets from the SPIXFC Base Peripheral Address. 91 * @{ 92 */ 93 #define MXC_R_SPIXFC_CFG ((uint32_t)0x00000000UL) /**< Offset from SPIXFC Base Address: <tt> 0x0000</tt> */ 94 #define MXC_R_SPIXFC_SS_POL ((uint32_t)0x00000004UL) /**< Offset from SPIXFC Base Address: <tt> 0x0004</tt> */ 95 #define MXC_R_SPIXFC_GEN_CTRL ((uint32_t)0x00000008UL) /**< Offset from SPIXFC Base Address: <tt> 0x0008</tt> */ 96 #define MXC_R_SPIXFC_FIFO_CTRL ((uint32_t)0x0000000CUL) /**< Offset from SPIXFC Base Address: <tt> 0x000C</tt> */ 97 #define MXC_R_SPIXFC_SP_CTRL ((uint32_t)0x00000010UL) /**< Offset from SPIXFC Base Address: <tt> 0x0010</tt> */ 98 #define MXC_R_SPIXFC_INT_FL ((uint32_t)0x00000014UL) /**< Offset from SPIXFC Base Address: <tt> 0x0014</tt> */ 99 #define MXC_R_SPIXFC_INT_EN ((uint32_t)0x00000018UL) /**< Offset from SPIXFC Base Address: <tt> 0x0018</tt> */ 100 /**@} end of group spixfc_registers */ 101 102 /** 103 * @ingroup spixfc_registers 104 * @defgroup SPIXFC_CFG SPIXFC_CFG 105 * @brief Configuration Register. 106 * @{ 107 */ 108 #define MXC_F_SPIXFC_CFG_SSEL_POS 0 /**< CFG_SSEL Position */ 109 #define MXC_F_SPIXFC_CFG_SSEL ((uint32_t)(0x7UL << MXC_F_SPIXFC_CFG_SSEL_POS)) /**< CFG_SSEL Mask */ 110 #define MXC_V_SPIXFC_CFG_SSEL_SLAVE0 ((uint32_t)0x0UL) /**< CFG_SSEL_SLAVE0 Value */ 111 #define MXC_S_SPIXFC_CFG_SSEL_SLAVE0 (MXC_V_SPIXFC_CFG_SSEL_SLAVE0 << MXC_F_SPIXFC_CFG_SSEL_POS) /**< CFG_SSEL_SLAVE0 Setting */ 112 113 #define MXC_F_SPIXFC_CFG_MODE_POS 4 /**< CFG_MODE Position */ 114 #define MXC_F_SPIXFC_CFG_MODE ((uint32_t)(0x3UL << MXC_F_SPIXFC_CFG_MODE_POS)) /**< CFG_MODE Mask */ 115 #define MXC_V_SPIXFC_CFG_MODE_MODE0 ((uint32_t)0x0UL) /**< CFG_MODE_MODE0 Value */ 116 #define MXC_S_SPIXFC_CFG_MODE_MODE0 (MXC_V_SPIXFC_CFG_MODE_MODE0 << MXC_F_SPIXFC_CFG_MODE_POS) /**< CFG_MODE_MODE0 Setting */ 117 #define MXC_V_SPIXFC_CFG_MODE_MODE3 ((uint32_t)0x3UL) /**< CFG_MODE_MODE3 Value */ 118 #define MXC_S_SPIXFC_CFG_MODE_MODE3 (MXC_V_SPIXFC_CFG_MODE_MODE3 << MXC_F_SPIXFC_CFG_MODE_POS) /**< CFG_MODE_MODE3 Setting */ 119 120 #define MXC_F_SPIXFC_CFG_PGSZ_POS 6 /**< CFG_PGSZ Position */ 121 #define MXC_F_SPIXFC_CFG_PGSZ ((uint32_t)(0x3UL << MXC_F_SPIXFC_CFG_PGSZ_POS)) /**< CFG_PGSZ Mask */ 122 #define MXC_V_SPIXFC_CFG_PGSZ_4BYTES ((uint32_t)0x0UL) /**< CFG_PGSZ_4BYTES Value */ 123 #define MXC_S_SPIXFC_CFG_PGSZ_4BYTES (MXC_V_SPIXFC_CFG_PGSZ_4BYTES << MXC_F_SPIXFC_CFG_PGSZ_POS) /**< CFG_PGSZ_4BYTES Setting */ 124 #define MXC_V_SPIXFC_CFG_PGSZ_8BYTES ((uint32_t)0x1UL) /**< CFG_PGSZ_8BYTES Value */ 125 #define MXC_S_SPIXFC_CFG_PGSZ_8BYTES (MXC_V_SPIXFC_CFG_PGSZ_8BYTES << MXC_F_SPIXFC_CFG_PGSZ_POS) /**< CFG_PGSZ_8BYTES Setting */ 126 #define MXC_V_SPIXFC_CFG_PGSZ_16BYTES ((uint32_t)0x2UL) /**< CFG_PGSZ_16BYTES Value */ 127 #define MXC_S_SPIXFC_CFG_PGSZ_16BYTES (MXC_V_SPIXFC_CFG_PGSZ_16BYTES << MXC_F_SPIXFC_CFG_PGSZ_POS) /**< CFG_PGSZ_16BYTES Setting */ 128 #define MXC_V_SPIXFC_CFG_PGSZ_32BYTES ((uint32_t)0x3UL) /**< CFG_PGSZ_32BYTES Value */ 129 #define MXC_S_SPIXFC_CFG_PGSZ_32BYTES (MXC_V_SPIXFC_CFG_PGSZ_32BYTES << MXC_F_SPIXFC_CFG_PGSZ_POS) /**< CFG_PGSZ_32BYTES Setting */ 130 131 #define MXC_F_SPIXFC_CFG_HICLK_POS 8 /**< CFG_HICLK Position */ 132 #define MXC_F_SPIXFC_CFG_HICLK ((uint32_t)(0xFUL << MXC_F_SPIXFC_CFG_HICLK_POS)) /**< CFG_HICLK Mask */ 133 #define MXC_V_SPIXFC_CFG_HICLK_16CLK ((uint32_t)0x0UL) /**< CFG_HICLK_16CLK Value */ 134 #define MXC_S_SPIXFC_CFG_HICLK_16CLK (MXC_V_SPIXFC_CFG_HICLK_16CLK << MXC_F_SPIXFC_CFG_HICLK_POS) /**< CFG_HICLK_16CLK Setting */ 135 #define MXC_V_SPIXFC_CFG_HICLK_1CLK ((uint32_t)0x1UL) /**< CFG_HICLK_1CLK Value */ 136 #define MXC_S_SPIXFC_CFG_HICLK_1CLK (MXC_V_SPIXFC_CFG_HICLK_1CLK << MXC_F_SPIXFC_CFG_HICLK_POS) /**< CFG_HICLK_1CLK Setting */ 137 #define MXC_V_SPIXFC_CFG_HICLK_2CLK ((uint32_t)0x2UL) /**< CFG_HICLK_2CLK Value */ 138 #define MXC_S_SPIXFC_CFG_HICLK_2CLK (MXC_V_SPIXFC_CFG_HICLK_2CLK << MXC_F_SPIXFC_CFG_HICLK_POS) /**< CFG_HICLK_2CLK Setting */ 139 #define MXC_V_SPIXFC_CFG_HICLK_3CLK ((uint32_t)0x3UL) /**< CFG_HICLK_3CLK Value */ 140 #define MXC_S_SPIXFC_CFG_HICLK_3CLK (MXC_V_SPIXFC_CFG_HICLK_3CLK << MXC_F_SPIXFC_CFG_HICLK_POS) /**< CFG_HICLK_3CLK Setting */ 141 #define MXC_V_SPIXFC_CFG_HICLK_4CLK ((uint32_t)0x4UL) /**< CFG_HICLK_4CLK Value */ 142 #define MXC_S_SPIXFC_CFG_HICLK_4CLK (MXC_V_SPIXFC_CFG_HICLK_4CLK << MXC_F_SPIXFC_CFG_HICLK_POS) /**< CFG_HICLK_4CLK Setting */ 143 #define MXC_V_SPIXFC_CFG_HICLK_5CLK ((uint32_t)0x5UL) /**< CFG_HICLK_5CLK Value */ 144 #define MXC_S_SPIXFC_CFG_HICLK_5CLK (MXC_V_SPIXFC_CFG_HICLK_5CLK << MXC_F_SPIXFC_CFG_HICLK_POS) /**< CFG_HICLK_5CLK Setting */ 145 #define MXC_V_SPIXFC_CFG_HICLK_6CLK ((uint32_t)0x6UL) /**< CFG_HICLK_6CLK Value */ 146 #define MXC_S_SPIXFC_CFG_HICLK_6CLK (MXC_V_SPIXFC_CFG_HICLK_6CLK << MXC_F_SPIXFC_CFG_HICLK_POS) /**< CFG_HICLK_6CLK Setting */ 147 #define MXC_V_SPIXFC_CFG_HICLK_7CLK ((uint32_t)0x7UL) /**< CFG_HICLK_7CLK Value */ 148 #define MXC_S_SPIXFC_CFG_HICLK_7CLK (MXC_V_SPIXFC_CFG_HICLK_7CLK << MXC_F_SPIXFC_CFG_HICLK_POS) /**< CFG_HICLK_7CLK Setting */ 149 #define MXC_V_SPIXFC_CFG_HICLK_8CLK ((uint32_t)0x8UL) /**< CFG_HICLK_8CLK Value */ 150 #define MXC_S_SPIXFC_CFG_HICLK_8CLK (MXC_V_SPIXFC_CFG_HICLK_8CLK << MXC_F_SPIXFC_CFG_HICLK_POS) /**< CFG_HICLK_8CLK Setting */ 151 #define MXC_V_SPIXFC_CFG_HICLK_9CLK ((uint32_t)0x9UL) /**< CFG_HICLK_9CLK Value */ 152 #define MXC_S_SPIXFC_CFG_HICLK_9CLK (MXC_V_SPIXFC_CFG_HICLK_9CLK << MXC_F_SPIXFC_CFG_HICLK_POS) /**< CFG_HICLK_9CLK Setting */ 153 #define MXC_V_SPIXFC_CFG_HICLK_10CLK ((uint32_t)0xAUL) /**< CFG_HICLK_10CLK Value */ 154 #define MXC_S_SPIXFC_CFG_HICLK_10CLK (MXC_V_SPIXFC_CFG_HICLK_10CLK << MXC_F_SPIXFC_CFG_HICLK_POS) /**< CFG_HICLK_10CLK Setting */ 155 #define MXC_V_SPIXFC_CFG_HICLK_11CLK ((uint32_t)0xBUL) /**< CFG_HICLK_11CLK Value */ 156 #define MXC_S_SPIXFC_CFG_HICLK_11CLK (MXC_V_SPIXFC_CFG_HICLK_11CLK << MXC_F_SPIXFC_CFG_HICLK_POS) /**< CFG_HICLK_11CLK Setting */ 157 #define MXC_V_SPIXFC_CFG_HICLK_12CLK ((uint32_t)0xCUL) /**< CFG_HICLK_12CLK Value */ 158 #define MXC_S_SPIXFC_CFG_HICLK_12CLK (MXC_V_SPIXFC_CFG_HICLK_12CLK << MXC_F_SPIXFC_CFG_HICLK_POS) /**< CFG_HICLK_12CLK Setting */ 159 #define MXC_V_SPIXFC_CFG_HICLK_13CLK ((uint32_t)0xDUL) /**< CFG_HICLK_13CLK Value */ 160 #define MXC_S_SPIXFC_CFG_HICLK_13CLK (MXC_V_SPIXFC_CFG_HICLK_13CLK << MXC_F_SPIXFC_CFG_HICLK_POS) /**< CFG_HICLK_13CLK Setting */ 161 #define MXC_V_SPIXFC_CFG_HICLK_14CLK ((uint32_t)0xEUL) /**< CFG_HICLK_14CLK Value */ 162 #define MXC_S_SPIXFC_CFG_HICLK_14CLK (MXC_V_SPIXFC_CFG_HICLK_14CLK << MXC_F_SPIXFC_CFG_HICLK_POS) /**< CFG_HICLK_14CLK Setting */ 163 #define MXC_V_SPIXFC_CFG_HICLK_15CLK ((uint32_t)0xFUL) /**< CFG_HICLK_15CLK Value */ 164 #define MXC_S_SPIXFC_CFG_HICLK_15CLK (MXC_V_SPIXFC_CFG_HICLK_15CLK << MXC_F_SPIXFC_CFG_HICLK_POS) /**< CFG_HICLK_15CLK Setting */ 165 166 #define MXC_F_SPIXFC_CFG_LOCLK_POS 12 /**< CFG_LOCLK Position */ 167 #define MXC_F_SPIXFC_CFG_LOCLK ((uint32_t)(0xFUL << MXC_F_SPIXFC_CFG_LOCLK_POS)) /**< CFG_LOCLK Mask */ 168 #define MXC_V_SPIXFC_CFG_LOCLK_16CLK ((uint32_t)0x0UL) /**< CFG_LOCLK_16CLK Value */ 169 #define MXC_S_SPIXFC_CFG_LOCLK_16CLK (MXC_V_SPIXFC_CFG_LOCLK_16CLK << MXC_F_SPIXFC_CFG_LOCLK_POS) /**< CFG_LOCLK_16CLK Setting */ 170 #define MXC_V_SPIXFC_CFG_LOCLK_1CLK ((uint32_t)0x1UL) /**< CFG_LOCLK_1CLK Value */ 171 #define MXC_S_SPIXFC_CFG_LOCLK_1CLK (MXC_V_SPIXFC_CFG_LOCLK_1CLK << MXC_F_SPIXFC_CFG_LOCLK_POS) /**< CFG_LOCLK_1CLK Setting */ 172 #define MXC_V_SPIXFC_CFG_LOCLK_2CLK ((uint32_t)0x2UL) /**< CFG_LOCLK_2CLK Value */ 173 #define MXC_S_SPIXFC_CFG_LOCLK_2CLK (MXC_V_SPIXFC_CFG_LOCLK_2CLK << MXC_F_SPIXFC_CFG_LOCLK_POS) /**< CFG_LOCLK_2CLK Setting */ 174 #define MXC_V_SPIXFC_CFG_LOCLK_3CLK ((uint32_t)0x3UL) /**< CFG_LOCLK_3CLK Value */ 175 #define MXC_S_SPIXFC_CFG_LOCLK_3CLK (MXC_V_SPIXFC_CFG_LOCLK_3CLK << MXC_F_SPIXFC_CFG_LOCLK_POS) /**< CFG_LOCLK_3CLK Setting */ 176 #define MXC_V_SPIXFC_CFG_LOCLK_4CLK ((uint32_t)0x4UL) /**< CFG_LOCLK_4CLK Value */ 177 #define MXC_S_SPIXFC_CFG_LOCLK_4CLK (MXC_V_SPIXFC_CFG_LOCLK_4CLK << MXC_F_SPIXFC_CFG_LOCLK_POS) /**< CFG_LOCLK_4CLK Setting */ 178 #define MXC_V_SPIXFC_CFG_LOCLK_5CLK ((uint32_t)0x5UL) /**< CFG_LOCLK_5CLK Value */ 179 #define MXC_S_SPIXFC_CFG_LOCLK_5CLK (MXC_V_SPIXFC_CFG_LOCLK_5CLK << MXC_F_SPIXFC_CFG_LOCLK_POS) /**< CFG_LOCLK_5CLK Setting */ 180 #define MXC_V_SPIXFC_CFG_LOCLK_6CLK ((uint32_t)0x6UL) /**< CFG_LOCLK_6CLK Value */ 181 #define MXC_S_SPIXFC_CFG_LOCLK_6CLK (MXC_V_SPIXFC_CFG_LOCLK_6CLK << MXC_F_SPIXFC_CFG_LOCLK_POS) /**< CFG_LOCLK_6CLK Setting */ 182 #define MXC_V_SPIXFC_CFG_LOCLK_7CLK ((uint32_t)0x7UL) /**< CFG_LOCLK_7CLK Value */ 183 #define MXC_S_SPIXFC_CFG_LOCLK_7CLK (MXC_V_SPIXFC_CFG_LOCLK_7CLK << MXC_F_SPIXFC_CFG_LOCLK_POS) /**< CFG_LOCLK_7CLK Setting */ 184 #define MXC_V_SPIXFC_CFG_LOCLK_8CLK ((uint32_t)0x8UL) /**< CFG_LOCLK_8CLK Value */ 185 #define MXC_S_SPIXFC_CFG_LOCLK_8CLK (MXC_V_SPIXFC_CFG_LOCLK_8CLK << MXC_F_SPIXFC_CFG_LOCLK_POS) /**< CFG_LOCLK_8CLK Setting */ 186 #define MXC_V_SPIXFC_CFG_LOCLK_9CLK ((uint32_t)0x9UL) /**< CFG_LOCLK_9CLK Value */ 187 #define MXC_S_SPIXFC_CFG_LOCLK_9CLK (MXC_V_SPIXFC_CFG_LOCLK_9CLK << MXC_F_SPIXFC_CFG_LOCLK_POS) /**< CFG_LOCLK_9CLK Setting */ 188 #define MXC_V_SPIXFC_CFG_LOCLK_10CLK ((uint32_t)0xAUL) /**< CFG_LOCLK_10CLK Value */ 189 #define MXC_S_SPIXFC_CFG_LOCLK_10CLK (MXC_V_SPIXFC_CFG_LOCLK_10CLK << MXC_F_SPIXFC_CFG_LOCLK_POS) /**< CFG_LOCLK_10CLK Setting */ 190 #define MXC_V_SPIXFC_CFG_LOCLK_11CLK ((uint32_t)0xBUL) /**< CFG_LOCLK_11CLK Value */ 191 #define MXC_S_SPIXFC_CFG_LOCLK_11CLK (MXC_V_SPIXFC_CFG_LOCLK_11CLK << MXC_F_SPIXFC_CFG_LOCLK_POS) /**< CFG_LOCLK_11CLK Setting */ 192 #define MXC_V_SPIXFC_CFG_LOCLK_12CLK ((uint32_t)0xCUL) /**< CFG_LOCLK_12CLK Value */ 193 #define MXC_S_SPIXFC_CFG_LOCLK_12CLK (MXC_V_SPIXFC_CFG_LOCLK_12CLK << MXC_F_SPIXFC_CFG_LOCLK_POS) /**< CFG_LOCLK_12CLK Setting */ 194 #define MXC_V_SPIXFC_CFG_LOCLK_13CLK ((uint32_t)0xDUL) /**< CFG_LOCLK_13CLK Value */ 195 #define MXC_S_SPIXFC_CFG_LOCLK_13CLK (MXC_V_SPIXFC_CFG_LOCLK_13CLK << MXC_F_SPIXFC_CFG_LOCLK_POS) /**< CFG_LOCLK_13CLK Setting */ 196 #define MXC_V_SPIXFC_CFG_LOCLK_14CLK ((uint32_t)0xEUL) /**< CFG_LOCLK_14CLK Value */ 197 #define MXC_S_SPIXFC_CFG_LOCLK_14CLK (MXC_V_SPIXFC_CFG_LOCLK_14CLK << MXC_F_SPIXFC_CFG_LOCLK_POS) /**< CFG_LOCLK_14CLK Setting */ 198 #define MXC_V_SPIXFC_CFG_LOCLK_15CLK ((uint32_t)0xFUL) /**< CFG_LOCLK_15CLK Value */ 199 #define MXC_S_SPIXFC_CFG_LOCLK_15CLK (MXC_V_SPIXFC_CFG_LOCLK_15CLK << MXC_F_SPIXFC_CFG_LOCLK_POS) /**< CFG_LOCLK_15CLK Setting */ 200 201 #define MXC_F_SPIXFC_CFG_SSACT_POS 16 /**< CFG_SSACT Position */ 202 #define MXC_F_SPIXFC_CFG_SSACT ((uint32_t)(0x3UL << MXC_F_SPIXFC_CFG_SSACT_POS)) /**< CFG_SSACT Mask */ 203 #define MXC_V_SPIXFC_CFG_SSACT_0CLK ((uint32_t)0x0UL) /**< CFG_SSACT_0CLK Value */ 204 #define MXC_S_SPIXFC_CFG_SSACT_0CLK (MXC_V_SPIXFC_CFG_SSACT_0CLK << MXC_F_SPIXFC_CFG_SSACT_POS) /**< CFG_SSACT_0CLK Setting */ 205 #define MXC_V_SPIXFC_CFG_SSACT_2CLK ((uint32_t)0x1UL) /**< CFG_SSACT_2CLK Value */ 206 #define MXC_S_SPIXFC_CFG_SSACT_2CLK (MXC_V_SPIXFC_CFG_SSACT_2CLK << MXC_F_SPIXFC_CFG_SSACT_POS) /**< CFG_SSACT_2CLK Setting */ 207 #define MXC_V_SPIXFC_CFG_SSACT_4CLK ((uint32_t)0x2UL) /**< CFG_SSACT_4CLK Value */ 208 #define MXC_S_SPIXFC_CFG_SSACT_4CLK (MXC_V_SPIXFC_CFG_SSACT_4CLK << MXC_F_SPIXFC_CFG_SSACT_POS) /**< CFG_SSACT_4CLK Setting */ 209 #define MXC_V_SPIXFC_CFG_SSACT_8CLK ((uint32_t)0x3UL) /**< CFG_SSACT_8CLK Value */ 210 #define MXC_S_SPIXFC_CFG_SSACT_8CLK (MXC_V_SPIXFC_CFG_SSACT_8CLK << MXC_F_SPIXFC_CFG_SSACT_POS) /**< CFG_SSACT_8CLK Setting */ 211 212 #define MXC_F_SPIXFC_CFG_INACT_POS 18 /**< CFG_INACT Position */ 213 #define MXC_F_SPIXFC_CFG_INACT ((uint32_t)(0x3UL << MXC_F_SPIXFC_CFG_INACT_POS)) /**< CFG_INACT Mask */ 214 #define MXC_V_SPIXFC_CFG_INACT_4CLK ((uint32_t)0x0UL) /**< CFG_INACT_4CLK Value */ 215 #define MXC_S_SPIXFC_CFG_INACT_4CLK (MXC_V_SPIXFC_CFG_INACT_4CLK << MXC_F_SPIXFC_CFG_INACT_POS) /**< CFG_INACT_4CLK Setting */ 216 #define MXC_V_SPIXFC_CFG_INACT_6CLK ((uint32_t)0x1UL) /**< CFG_INACT_6CLK Value */ 217 #define MXC_S_SPIXFC_CFG_INACT_6CLK (MXC_V_SPIXFC_CFG_INACT_6CLK << MXC_F_SPIXFC_CFG_INACT_POS) /**< CFG_INACT_6CLK Setting */ 218 #define MXC_V_SPIXFC_CFG_INACT_8CLK ((uint32_t)0x2UL) /**< CFG_INACT_8CLK Value */ 219 #define MXC_S_SPIXFC_CFG_INACT_8CLK (MXC_V_SPIXFC_CFG_INACT_8CLK << MXC_F_SPIXFC_CFG_INACT_POS) /**< CFG_INACT_8CLK Setting */ 220 #define MXC_V_SPIXFC_CFG_INACT_12CLK ((uint32_t)0x3UL) /**< CFG_INACT_12CLK Value */ 221 #define MXC_S_SPIXFC_CFG_INACT_12CLK (MXC_V_SPIXFC_CFG_INACT_12CLK << MXC_F_SPIXFC_CFG_INACT_POS) /**< CFG_INACT_12CLK Setting */ 222 223 #define MXC_F_SPIXFC_CFG_IOSMPL_POS 20 /**< CFG_IOSMPL Position */ 224 #define MXC_F_SPIXFC_CFG_IOSMPL ((uint32_t)(0xFUL << MXC_F_SPIXFC_CFG_IOSMPL_POS)) /**< CFG_IOSMPL Mask */ 225 #define MXC_V_SPIXFC_CFG_IOSMPL_NODLY ((uint32_t)0x0UL) /**< CFG_IOSMPL_NODLY Value */ 226 #define MXC_S_SPIXFC_CFG_IOSMPL_NODLY (MXC_V_SPIXFC_CFG_IOSMPL_NODLY << MXC_F_SPIXFC_CFG_IOSMPL_POS) /**< CFG_IOSMPL_NODLY Setting */ 227 #define MXC_V_SPIXFC_CFG_IOSMPL_1CLK ((uint32_t)0x1UL) /**< CFG_IOSMPL_1CLK Value */ 228 #define MXC_S_SPIXFC_CFG_IOSMPL_1CLK (MXC_V_SPIXFC_CFG_IOSMPL_1CLK << MXC_F_SPIXFC_CFG_IOSMPL_POS) /**< CFG_IOSMPL_1CLK Setting */ 229 #define MXC_V_SPIXFC_CFG_IOSMPL_2CLK ((uint32_t)0x2UL) /**< CFG_IOSMPL_2CLK Value */ 230 #define MXC_S_SPIXFC_CFG_IOSMPL_2CLK (MXC_V_SPIXFC_CFG_IOSMPL_2CLK << MXC_F_SPIXFC_CFG_IOSMPL_POS) /**< CFG_IOSMPL_2CLK Setting */ 231 #define MXC_V_SPIXFC_CFG_IOSMPL_3CLK ((uint32_t)0x3UL) /**< CFG_IOSMPL_3CLK Value */ 232 #define MXC_S_SPIXFC_CFG_IOSMPL_3CLK (MXC_V_SPIXFC_CFG_IOSMPL_3CLK << MXC_F_SPIXFC_CFG_IOSMPL_POS) /**< CFG_IOSMPL_3CLK Setting */ 233 #define MXC_V_SPIXFC_CFG_IOSMPL_4CLK ((uint32_t)0x4UL) /**< CFG_IOSMPL_4CLK Value */ 234 #define MXC_S_SPIXFC_CFG_IOSMPL_4CLK (MXC_V_SPIXFC_CFG_IOSMPL_4CLK << MXC_F_SPIXFC_CFG_IOSMPL_POS) /**< CFG_IOSMPL_4CLK Setting */ 235 #define MXC_V_SPIXFC_CFG_IOSMPL_5CLK ((uint32_t)0x5UL) /**< CFG_IOSMPL_5CLK Value */ 236 #define MXC_S_SPIXFC_CFG_IOSMPL_5CLK (MXC_V_SPIXFC_CFG_IOSMPL_5CLK << MXC_F_SPIXFC_CFG_IOSMPL_POS) /**< CFG_IOSMPL_5CLK Setting */ 237 #define MXC_V_SPIXFC_CFG_IOSMPL_6CLK ((uint32_t)0x6UL) /**< CFG_IOSMPL_6CLK Value */ 238 #define MXC_S_SPIXFC_CFG_IOSMPL_6CLK (MXC_V_SPIXFC_CFG_IOSMPL_6CLK << MXC_F_SPIXFC_CFG_IOSMPL_POS) /**< CFG_IOSMPL_6CLK Setting */ 239 #define MXC_V_SPIXFC_CFG_IOSMPL_7CLK ((uint32_t)0x7UL) /**< CFG_IOSMPL_7CLK Value */ 240 #define MXC_S_SPIXFC_CFG_IOSMPL_7CLK (MXC_V_SPIXFC_CFG_IOSMPL_7CLK << MXC_F_SPIXFC_CFG_IOSMPL_POS) /**< CFG_IOSMPL_7CLK Setting */ 241 #define MXC_V_SPIXFC_CFG_IOSMPL_8CLK ((uint32_t)0x8UL) /**< CFG_IOSMPL_8CLK Value */ 242 #define MXC_S_SPIXFC_CFG_IOSMPL_8CLK (MXC_V_SPIXFC_CFG_IOSMPL_8CLK << MXC_F_SPIXFC_CFG_IOSMPL_POS) /**< CFG_IOSMPL_8CLK Setting */ 243 #define MXC_V_SPIXFC_CFG_IOSMPL_9CLK ((uint32_t)0x9UL) /**< CFG_IOSMPL_9CLK Value */ 244 #define MXC_S_SPIXFC_CFG_IOSMPL_9CLK (MXC_V_SPIXFC_CFG_IOSMPL_9CLK << MXC_F_SPIXFC_CFG_IOSMPL_POS) /**< CFG_IOSMPL_9CLK Setting */ 245 #define MXC_V_SPIXFC_CFG_IOSMPL_10CLK ((uint32_t)0xAUL) /**< CFG_IOSMPL_10CLK Value */ 246 #define MXC_S_SPIXFC_CFG_IOSMPL_10CLK (MXC_V_SPIXFC_CFG_IOSMPL_10CLK << MXC_F_SPIXFC_CFG_IOSMPL_POS) /**< CFG_IOSMPL_10CLK Setting */ 247 #define MXC_V_SPIXFC_CFG_IOSMPL_11CLK ((uint32_t)0xBUL) /**< CFG_IOSMPL_11CLK Value */ 248 #define MXC_S_SPIXFC_CFG_IOSMPL_11CLK (MXC_V_SPIXFC_CFG_IOSMPL_11CLK << MXC_F_SPIXFC_CFG_IOSMPL_POS) /**< CFG_IOSMPL_11CLK Setting */ 249 #define MXC_V_SPIXFC_CFG_IOSMPL_12CLK ((uint32_t)0xCUL) /**< CFG_IOSMPL_12CLK Value */ 250 #define MXC_S_SPIXFC_CFG_IOSMPL_12CLK (MXC_V_SPIXFC_CFG_IOSMPL_12CLK << MXC_F_SPIXFC_CFG_IOSMPL_POS) /**< CFG_IOSMPL_12CLK Setting */ 251 #define MXC_V_SPIXFC_CFG_IOSMPL_13CLK ((uint32_t)0xDUL) /**< CFG_IOSMPL_13CLK Value */ 252 #define MXC_S_SPIXFC_CFG_IOSMPL_13CLK (MXC_V_SPIXFC_CFG_IOSMPL_13CLK << MXC_F_SPIXFC_CFG_IOSMPL_POS) /**< CFG_IOSMPL_13CLK Setting */ 253 #define MXC_V_SPIXFC_CFG_IOSMPL_14CLK ((uint32_t)0xEUL) /**< CFG_IOSMPL_14CLK Value */ 254 #define MXC_S_SPIXFC_CFG_IOSMPL_14CLK (MXC_V_SPIXFC_CFG_IOSMPL_14CLK << MXC_F_SPIXFC_CFG_IOSMPL_POS) /**< CFG_IOSMPL_14CLK Setting */ 255 #define MXC_V_SPIXFC_CFG_IOSMPL_15CLK ((uint32_t)0xFUL) /**< CFG_IOSMPL_15CLK Value */ 256 #define MXC_S_SPIXFC_CFG_IOSMPL_15CLK (MXC_V_SPIXFC_CFG_IOSMPL_15CLK << MXC_F_SPIXFC_CFG_IOSMPL_POS) /**< CFG_IOSMPL_15CLK Setting */ 257 258 /**@} end of group SPIXFC_CFG_Register */ 259 260 /** 261 * @ingroup spixfc_registers 262 * @defgroup SPIXFC_SS_POL SPIXFC_SS_POL 263 * @brief SPIX Controller Slave Select Polarity Register. 264 * @{ 265 */ 266 #define MXC_F_SPIXFC_SS_POL_SSPOL_0_POS 0 /**< SS_POL_SSPOL_0 Position */ 267 #define MXC_F_SPIXFC_SS_POL_SSPOL_0 ((uint32_t)(0x1UL << MXC_F_SPIXFC_SS_POL_SSPOL_0_POS)) /**< SS_POL_SSPOL_0 Mask */ 268 #define MXC_V_SPIXFC_SS_POL_SSPOL_0_ACTIVELO ((uint32_t)0x0UL) /**< SS_POL_SSPOL_0_ACTIVELO Value */ 269 #define MXC_S_SPIXFC_SS_POL_SSPOL_0_ACTIVELO (MXC_V_SPIXFC_SS_POL_SSPOL_0_ACTIVELO << MXC_F_SPIXFC_SS_POL_SSPOL_0_POS) /**< SS_POL_SSPOL_0_ACTIVELO Setting */ 270 #define MXC_V_SPIXFC_SS_POL_SSPOL_0_ACTIVEHI ((uint32_t)0x1UL) /**< SS_POL_SSPOL_0_ACTIVEHI Value */ 271 #define MXC_S_SPIXFC_SS_POL_SSPOL_0_ACTIVEHI (MXC_V_SPIXFC_SS_POL_SSPOL_0_ACTIVEHI << MXC_F_SPIXFC_SS_POL_SSPOL_0_POS) /**< SS_POL_SSPOL_0_ACTIVEHI Setting */ 272 273 /**@} end of group SPIXFC_SS_POL_Register */ 274 275 /** 276 * @ingroup spixfc_registers 277 * @defgroup SPIXFC_GEN_CTRL SPIXFC_GEN_CTRL 278 * @brief SPIX Controller General Controller Register. 279 * @{ 280 */ 281 #define MXC_F_SPIXFC_GEN_CTRL_ENABLE_POS 0 /**< GEN_CTRL_ENABLE Position */ 282 #define MXC_F_SPIXFC_GEN_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_ENABLE_POS)) /**< GEN_CTRL_ENABLE Mask */ 283 #define MXC_V_SPIXFC_GEN_CTRL_ENABLE_DIS ((uint32_t)0x0UL) /**< GEN_CTRL_ENABLE_DIS Value */ 284 #define MXC_S_SPIXFC_GEN_CTRL_ENABLE_DIS (MXC_V_SPIXFC_GEN_CTRL_ENABLE_DIS << MXC_F_SPIXFC_GEN_CTRL_ENABLE_POS) /**< GEN_CTRL_ENABLE_DIS Setting */ 285 #define MXC_V_SPIXFC_GEN_CTRL_ENABLE_EN ((uint32_t)0x1UL) /**< GEN_CTRL_ENABLE_EN Value */ 286 #define MXC_S_SPIXFC_GEN_CTRL_ENABLE_EN (MXC_V_SPIXFC_GEN_CTRL_ENABLE_EN << MXC_F_SPIXFC_GEN_CTRL_ENABLE_POS) /**< GEN_CTRL_ENABLE_EN Setting */ 287 288 #define MXC_F_SPIXFC_GEN_CTRL_TFIFOEN_POS 1 /**< GEN_CTRL_TFIFOEN Position */ 289 #define MXC_F_SPIXFC_GEN_CTRL_TFIFOEN ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_TFIFOEN_POS)) /**< GEN_CTRL_TFIFOEN Mask */ 290 #define MXC_V_SPIXFC_GEN_CTRL_TFIFOEN_DIS ((uint32_t)0x0UL) /**< GEN_CTRL_TFIFOEN_DIS Value */ 291 #define MXC_S_SPIXFC_GEN_CTRL_TFIFOEN_DIS (MXC_V_SPIXFC_GEN_CTRL_TFIFOEN_DIS << MXC_F_SPIXFC_GEN_CTRL_TFIFOEN_POS) /**< GEN_CTRL_TFIFOEN_DIS Setting */ 292 #define MXC_V_SPIXFC_GEN_CTRL_TFIFOEN_EN ((uint32_t)0x1UL) /**< GEN_CTRL_TFIFOEN_EN Value */ 293 #define MXC_S_SPIXFC_GEN_CTRL_TFIFOEN_EN (MXC_V_SPIXFC_GEN_CTRL_TFIFOEN_EN << MXC_F_SPIXFC_GEN_CTRL_TFIFOEN_POS) /**< GEN_CTRL_TFIFOEN_EN Setting */ 294 295 #define MXC_F_SPIXFC_GEN_CTRL_RFIFOEN_POS 2 /**< GEN_CTRL_RFIFOEN Position */ 296 #define MXC_F_SPIXFC_GEN_CTRL_RFIFOEN ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_RFIFOEN_POS)) /**< GEN_CTRL_RFIFOEN Mask */ 297 #define MXC_V_SPIXFC_GEN_CTRL_RFIFOEN_DIS ((uint32_t)0x0UL) /**< GEN_CTRL_RFIFOEN_DIS Value */ 298 #define MXC_S_SPIXFC_GEN_CTRL_RFIFOEN_DIS (MXC_V_SPIXFC_GEN_CTRL_RFIFOEN_DIS << MXC_F_SPIXFC_GEN_CTRL_RFIFOEN_POS) /**< GEN_CTRL_RFIFOEN_DIS Setting */ 299 #define MXC_V_SPIXFC_GEN_CTRL_RFIFOEN_EN ((uint32_t)0x1UL) /**< GEN_CTRL_RFIFOEN_EN Value */ 300 #define MXC_S_SPIXFC_GEN_CTRL_RFIFOEN_EN (MXC_V_SPIXFC_GEN_CTRL_RFIFOEN_EN << MXC_F_SPIXFC_GEN_CTRL_RFIFOEN_POS) /**< GEN_CTRL_RFIFOEN_EN Setting */ 301 302 #define MXC_F_SPIXFC_GEN_CTRL_BBMODE_POS 3 /**< GEN_CTRL_BBMODE Position */ 303 #define MXC_F_SPIXFC_GEN_CTRL_BBMODE ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_BBMODE_POS)) /**< GEN_CTRL_BBMODE Mask */ 304 #define MXC_V_SPIXFC_GEN_CTRL_BBMODE_DIS ((uint32_t)0x0UL) /**< GEN_CTRL_BBMODE_DIS Value */ 305 #define MXC_S_SPIXFC_GEN_CTRL_BBMODE_DIS (MXC_V_SPIXFC_GEN_CTRL_BBMODE_DIS << MXC_F_SPIXFC_GEN_CTRL_BBMODE_POS) /**< GEN_CTRL_BBMODE_DIS Setting */ 306 #define MXC_V_SPIXFC_GEN_CTRL_BBMODE_EN ((uint32_t)0x1UL) /**< GEN_CTRL_BBMODE_EN Value */ 307 #define MXC_S_SPIXFC_GEN_CTRL_BBMODE_EN (MXC_V_SPIXFC_GEN_CTRL_BBMODE_EN << MXC_F_SPIXFC_GEN_CTRL_BBMODE_POS) /**< GEN_CTRL_BBMODE_EN Setting */ 308 309 #define MXC_F_SPIXFC_GEN_CTRL_SSDR_POS 4 /**< GEN_CTRL_SSDR Position */ 310 #define MXC_F_SPIXFC_GEN_CTRL_SSDR ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SSDR_POS)) /**< GEN_CTRL_SSDR Mask */ 311 #define MXC_V_SPIXFC_GEN_CTRL_SSDR_OUTPUT0 ((uint32_t)0x0UL) /**< GEN_CTRL_SSDR_OUTPUT0 Value */ 312 #define MXC_S_SPIXFC_GEN_CTRL_SSDR_OUTPUT0 (MXC_V_SPIXFC_GEN_CTRL_SSDR_OUTPUT0 << MXC_F_SPIXFC_GEN_CTRL_SSDR_POS) /**< GEN_CTRL_SSDR_OUTPUT0 Setting */ 313 #define MXC_V_SPIXFC_GEN_CTRL_SSDR_OUTPUT1 ((uint32_t)0x1UL) /**< GEN_CTRL_SSDR_OUTPUT1 Value */ 314 #define MXC_S_SPIXFC_GEN_CTRL_SSDR_OUTPUT1 (MXC_V_SPIXFC_GEN_CTRL_SSDR_OUTPUT1 << MXC_F_SPIXFC_GEN_CTRL_SSDR_POS) /**< GEN_CTRL_SSDR_OUTPUT1 Setting */ 315 316 #define MXC_F_SPIXFC_GEN_CTRL_SCKDR_POS 6 /**< GEN_CTRL_SCKDR Position */ 317 #define MXC_F_SPIXFC_GEN_CTRL_SCKDR ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SCKDR_POS)) /**< GEN_CTRL_SCKDR Mask */ 318 #define MXC_V_SPIXFC_GEN_CTRL_SCKDR_SCK0 ((uint32_t)0x0UL) /**< GEN_CTRL_SCKDR_SCK0 Value */ 319 #define MXC_S_SPIXFC_GEN_CTRL_SCKDR_SCK0 (MXC_V_SPIXFC_GEN_CTRL_SCKDR_SCK0 << MXC_F_SPIXFC_GEN_CTRL_SCKDR_POS) /**< GEN_CTRL_SCKDR_SCK0 Setting */ 320 #define MXC_V_SPIXFC_GEN_CTRL_SCKDR_SCK1 ((uint32_t)0x1UL) /**< GEN_CTRL_SCKDR_SCK1 Value */ 321 #define MXC_S_SPIXFC_GEN_CTRL_SCKDR_SCK1 (MXC_V_SPIXFC_GEN_CTRL_SCKDR_SCK1 << MXC_F_SPIXFC_GEN_CTRL_SCKDR_POS) /**< GEN_CTRL_SCKDR_SCK1 Setting */ 322 323 #define MXC_F_SPIXFC_GEN_CTRL_SDATAIN_POS 8 /**< GEN_CTRL_SDATAIN Position */ 324 #define MXC_F_SPIXFC_GEN_CTRL_SDATAIN ((uint32_t)(0xFUL << MXC_F_SPIXFC_GEN_CTRL_SDATAIN_POS)) /**< GEN_CTRL_SDATAIN Mask */ 325 #define MXC_V_SPIXFC_GEN_CTRL_SDATAIN_SDIO0 ((uint32_t)0x1UL) /**< GEN_CTRL_SDATAIN_SDIO0 Value */ 326 #define MXC_S_SPIXFC_GEN_CTRL_SDATAIN_SDIO0 (MXC_V_SPIXFC_GEN_CTRL_SDATAIN_SDIO0 << MXC_F_SPIXFC_GEN_CTRL_SDATAIN_POS) /**< GEN_CTRL_SDATAIN_SDIO0 Setting */ 327 #define MXC_V_SPIXFC_GEN_CTRL_SDATAIN_SDIO1 ((uint32_t)0x2UL) /**< GEN_CTRL_SDATAIN_SDIO1 Value */ 328 #define MXC_S_SPIXFC_GEN_CTRL_SDATAIN_SDIO1 (MXC_V_SPIXFC_GEN_CTRL_SDATAIN_SDIO1 << MXC_F_SPIXFC_GEN_CTRL_SDATAIN_POS) /**< GEN_CTRL_SDATAIN_SDIO1 Setting */ 329 #define MXC_V_SPIXFC_GEN_CTRL_SDATAIN_SDIO2 ((uint32_t)0x4UL) /**< GEN_CTRL_SDATAIN_SDIO2 Value */ 330 #define MXC_S_SPIXFC_GEN_CTRL_SDATAIN_SDIO2 (MXC_V_SPIXFC_GEN_CTRL_SDATAIN_SDIO2 << MXC_F_SPIXFC_GEN_CTRL_SDATAIN_POS) /**< GEN_CTRL_SDATAIN_SDIO2 Setting */ 331 #define MXC_V_SPIXFC_GEN_CTRL_SDATAIN_SDIO3 ((uint32_t)0x8UL) /**< GEN_CTRL_SDATAIN_SDIO3 Value */ 332 #define MXC_S_SPIXFC_GEN_CTRL_SDATAIN_SDIO3 (MXC_V_SPIXFC_GEN_CTRL_SDATAIN_SDIO3 << MXC_F_SPIXFC_GEN_CTRL_SDATAIN_POS) /**< GEN_CTRL_SDATAIN_SDIO3 Setting */ 333 334 #define MXC_F_SPIXFC_GEN_CTRL_BBDAT_POS 12 /**< GEN_CTRL_BBDAT Position */ 335 #define MXC_F_SPIXFC_GEN_CTRL_BBDAT ((uint32_t)(0xFUL << MXC_F_SPIXFC_GEN_CTRL_BBDAT_POS)) /**< GEN_CTRL_BBDAT Mask */ 336 #define MXC_V_SPIXFC_GEN_CTRL_BBDAT_SDIO0 ((uint32_t)0x1UL) /**< GEN_CTRL_BBDAT_SDIO0 Value */ 337 #define MXC_S_SPIXFC_GEN_CTRL_BBDAT_SDIO0 (MXC_V_SPIXFC_GEN_CTRL_BBDAT_SDIO0 << MXC_F_SPIXFC_GEN_CTRL_BBDAT_POS) /**< GEN_CTRL_BBDAT_SDIO0 Setting */ 338 #define MXC_V_SPIXFC_GEN_CTRL_BBDAT_SDIO1 ((uint32_t)0x2UL) /**< GEN_CTRL_BBDAT_SDIO1 Value */ 339 #define MXC_S_SPIXFC_GEN_CTRL_BBDAT_SDIO1 (MXC_V_SPIXFC_GEN_CTRL_BBDAT_SDIO1 << MXC_F_SPIXFC_GEN_CTRL_BBDAT_POS) /**< GEN_CTRL_BBDAT_SDIO1 Setting */ 340 #define MXC_V_SPIXFC_GEN_CTRL_BBDAT_SDIO2 ((uint32_t)0x4UL) /**< GEN_CTRL_BBDAT_SDIO2 Value */ 341 #define MXC_S_SPIXFC_GEN_CTRL_BBDAT_SDIO2 (MXC_V_SPIXFC_GEN_CTRL_BBDAT_SDIO2 << MXC_F_SPIXFC_GEN_CTRL_BBDAT_POS) /**< GEN_CTRL_BBDAT_SDIO2 Setting */ 342 #define MXC_V_SPIXFC_GEN_CTRL_BBDAT_SDIO3 ((uint32_t)0x8UL) /**< GEN_CTRL_BBDAT_SDIO3 Value */ 343 #define MXC_S_SPIXFC_GEN_CTRL_BBDAT_SDIO3 (MXC_V_SPIXFC_GEN_CTRL_BBDAT_SDIO3 << MXC_F_SPIXFC_GEN_CTRL_BBDAT_POS) /**< GEN_CTRL_BBDAT_SDIO3 Setting */ 344 345 #define MXC_F_SPIXFC_GEN_CTRL_BBDATOEN_POS 16 /**< GEN_CTRL_BBDATOEN Position */ 346 #define MXC_F_SPIXFC_GEN_CTRL_BBDATOEN ((uint32_t)(0xFUL << MXC_F_SPIXFC_GEN_CTRL_BBDATOEN_POS)) /**< GEN_CTRL_BBDATOEN Mask */ 347 #define MXC_V_SPIXFC_GEN_CTRL_BBDATOEN_SDIO0 ((uint32_t)0x1UL) /**< GEN_CTRL_BBDATOEN_SDIO0 Value */ 348 #define MXC_S_SPIXFC_GEN_CTRL_BBDATOEN_SDIO0 (MXC_V_SPIXFC_GEN_CTRL_BBDATOEN_SDIO0 << MXC_F_SPIXFC_GEN_CTRL_BBDATOEN_POS) /**< GEN_CTRL_BBDATOEN_SDIO0 Setting */ 349 #define MXC_V_SPIXFC_GEN_CTRL_BBDATOEN_SDIO1 ((uint32_t)0x2UL) /**< GEN_CTRL_BBDATOEN_SDIO1 Value */ 350 #define MXC_S_SPIXFC_GEN_CTRL_BBDATOEN_SDIO1 (MXC_V_SPIXFC_GEN_CTRL_BBDATOEN_SDIO1 << MXC_F_SPIXFC_GEN_CTRL_BBDATOEN_POS) /**< GEN_CTRL_BBDATOEN_SDIO1 Setting */ 351 #define MXC_V_SPIXFC_GEN_CTRL_BBDATOEN_SDIO2 ((uint32_t)0x4UL) /**< GEN_CTRL_BBDATOEN_SDIO2 Value */ 352 #define MXC_S_SPIXFC_GEN_CTRL_BBDATOEN_SDIO2 (MXC_V_SPIXFC_GEN_CTRL_BBDATOEN_SDIO2 << MXC_F_SPIXFC_GEN_CTRL_BBDATOEN_POS) /**< GEN_CTRL_BBDATOEN_SDIO2 Setting */ 353 #define MXC_V_SPIXFC_GEN_CTRL_BBDATOEN_SDIO3 ((uint32_t)0x8UL) /**< GEN_CTRL_BBDATOEN_SDIO3 Value */ 354 #define MXC_S_SPIXFC_GEN_CTRL_BBDATOEN_SDIO3 (MXC_V_SPIXFC_GEN_CTRL_BBDATOEN_SDIO3 << MXC_F_SPIXFC_GEN_CTRL_BBDATOEN_POS) /**< GEN_CTRL_BBDATOEN_SDIO3 Setting */ 355 356 #define MXC_F_SPIXFC_GEN_CTRL_SIMPLE_POS 20 /**< GEN_CTRL_SIMPLE Position */ 357 #define MXC_F_SPIXFC_GEN_CTRL_SIMPLE ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SIMPLE_POS)) /**< GEN_CTRL_SIMPLE Mask */ 358 #define MXC_V_SPIXFC_GEN_CTRL_SIMPLE_DIS ((uint32_t)0x0UL) /**< GEN_CTRL_SIMPLE_DIS Value */ 359 #define MXC_S_SPIXFC_GEN_CTRL_SIMPLE_DIS (MXC_V_SPIXFC_GEN_CTRL_SIMPLE_DIS << MXC_F_SPIXFC_GEN_CTRL_SIMPLE_POS) /**< GEN_CTRL_SIMPLE_DIS Setting */ 360 #define MXC_V_SPIXFC_GEN_CTRL_SIMPLE_EN ((uint32_t)0x1UL) /**< GEN_CTRL_SIMPLE_EN Value */ 361 #define MXC_S_SPIXFC_GEN_CTRL_SIMPLE_EN (MXC_V_SPIXFC_GEN_CTRL_SIMPLE_EN << MXC_F_SPIXFC_GEN_CTRL_SIMPLE_POS) /**< GEN_CTRL_SIMPLE_EN Setting */ 362 363 #define MXC_F_SPIXFC_GEN_CTRL_SIMPLERX_POS 21 /**< GEN_CTRL_SIMPLERX Position */ 364 #define MXC_F_SPIXFC_GEN_CTRL_SIMPLERX ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SIMPLERX_POS)) /**< GEN_CTRL_SIMPLERX Mask */ 365 #define MXC_V_SPIXFC_GEN_CTRL_SIMPLERX_INITSPI ((uint32_t)0x1UL) /**< GEN_CTRL_SIMPLERX_INITSPI Value */ 366 #define MXC_S_SPIXFC_GEN_CTRL_SIMPLERX_INITSPI (MXC_V_SPIXFC_GEN_CTRL_SIMPLERX_INITSPI << MXC_F_SPIXFC_GEN_CTRL_SIMPLERX_POS) /**< GEN_CTRL_SIMPLERX_INITSPI Setting */ 367 368 #define MXC_F_SPIXFC_GEN_CTRL_SMPLSS_POS 22 /**< GEN_CTRL_SMPLSS Position */ 369 #define MXC_F_SPIXFC_GEN_CTRL_SMPLSS ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SMPLSS_POS)) /**< GEN_CTRL_SMPLSS Mask */ 370 #define MXC_V_SPIXFC_GEN_CTRL_SMPLSS_DEASSERTSS ((uint32_t)0x1UL) /**< GEN_CTRL_SMPLSS_DEASSERTSS Value */ 371 #define MXC_S_SPIXFC_GEN_CTRL_SMPLSS_DEASSERTSS (MXC_V_SPIXFC_GEN_CTRL_SMPLSS_DEASSERTSS << MXC_F_SPIXFC_GEN_CTRL_SMPLSS_POS) /**< GEN_CTRL_SMPLSS_DEASSERTSS Setting */ 372 373 #define MXC_F_SPIXFC_GEN_CTRL_SCKFB_POS 24 /**< GEN_CTRL_SCKFB Position */ 374 #define MXC_F_SPIXFC_GEN_CTRL_SCKFB ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SCKFB_POS)) /**< GEN_CTRL_SCKFB Mask */ 375 #define MXC_V_SPIXFC_GEN_CTRL_SCKFB_DIS ((uint32_t)0x0UL) /**< GEN_CTRL_SCKFB_DIS Value */ 376 #define MXC_S_SPIXFC_GEN_CTRL_SCKFB_DIS (MXC_V_SPIXFC_GEN_CTRL_SCKFB_DIS << MXC_F_SPIXFC_GEN_CTRL_SCKFB_POS) /**< GEN_CTRL_SCKFB_DIS Setting */ 377 #define MXC_V_SPIXFC_GEN_CTRL_SCKFB_EN ((uint32_t)0x1UL) /**< GEN_CTRL_SCKFB_EN Value */ 378 #define MXC_S_SPIXFC_GEN_CTRL_SCKFB_EN (MXC_V_SPIXFC_GEN_CTRL_SCKFB_EN << MXC_F_SPIXFC_GEN_CTRL_SCKFB_POS) /**< GEN_CTRL_SCKFB_EN Setting */ 379 380 #define MXC_F_SPIXFC_GEN_CTRL_SCKFBINV_POS 25 /**< GEN_CTRL_SCKFBINV Position */ 381 #define MXC_F_SPIXFC_GEN_CTRL_SCKFBINV ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SCKFBINV_POS)) /**< GEN_CTRL_SCKFBINV Mask */ 382 #define MXC_V_SPIXFC_GEN_CTRL_SCKFBINV_NORMAL ((uint32_t)0x0UL) /**< GEN_CTRL_SCKFBINV_NORMAL Value */ 383 #define MXC_S_SPIXFC_GEN_CTRL_SCKFBINV_NORMAL (MXC_V_SPIXFC_GEN_CTRL_SCKFBINV_NORMAL << MXC_F_SPIXFC_GEN_CTRL_SCKFBINV_POS) /**< GEN_CTRL_SCKFBINV_NORMAL Setting */ 384 #define MXC_V_SPIXFC_GEN_CTRL_SCKFBINV_INVERT ((uint32_t)0x1UL) /**< GEN_CTRL_SCKFBINV_INVERT Value */ 385 #define MXC_S_SPIXFC_GEN_CTRL_SCKFBINV_INVERT (MXC_V_SPIXFC_GEN_CTRL_SCKFBINV_INVERT << MXC_F_SPIXFC_GEN_CTRL_SCKFBINV_POS) /**< GEN_CTRL_SCKFBINV_INVERT Setting */ 386 387 /**@} end of group SPIXFC_GEN_CTRL_Register */ 388 389 /** 390 * @ingroup spixfc_registers 391 * @defgroup SPIXFC_FIFO_CTRL SPIXFC_FIFO_CTRL 392 * @brief SPIX Controller FIFO Control and Status Register. 393 * @{ 394 */ 395 #define MXC_F_SPIXFC_FIFO_CTRL_TFIFOLVL_POS 0 /**< FIFO_CTRL_TFIFOLVL Position */ 396 #define MXC_F_SPIXFC_FIFO_CTRL_TFIFOLVL ((uint32_t)(0xFUL << MXC_F_SPIXFC_FIFO_CTRL_TFIFOLVL_POS)) /**< FIFO_CTRL_TFIFOLVL Mask */ 397 398 #define MXC_F_SPIXFC_FIFO_CTRL_TFIFOCNT_POS 8 /**< FIFO_CTRL_TFIFOCNT Position */ 399 #define MXC_F_SPIXFC_FIFO_CTRL_TFIFOCNT ((uint32_t)(0x1FUL << MXC_F_SPIXFC_FIFO_CTRL_TFIFOCNT_POS)) /**< FIFO_CTRL_TFIFOCNT Mask */ 400 401 #define MXC_F_SPIXFC_FIFO_CTRL_RFIFOLVL_POS 16 /**< FIFO_CTRL_RFIFOLVL Position */ 402 #define MXC_F_SPIXFC_FIFO_CTRL_RFIFOLVL ((uint32_t)(0x1FUL << MXC_F_SPIXFC_FIFO_CTRL_RFIFOLVL_POS)) /**< FIFO_CTRL_RFIFOLVL Mask */ 403 404 #define MXC_F_SPIXFC_FIFO_CTRL_RFIFOCNT_POS 24 /**< FIFO_CTRL_RFIFOCNT Position */ 405 #define MXC_F_SPIXFC_FIFO_CTRL_RFIFOCNT ((uint32_t)(0x3FUL << MXC_F_SPIXFC_FIFO_CTRL_RFIFOCNT_POS)) /**< FIFO_CTRL_RFIFOCNT Mask */ 406 407 /**@} end of group SPIXFC_FIFO_CTRL_Register */ 408 409 /** 410 * @ingroup spixfc_registers 411 * @defgroup SPIXFC_SP_CTRL SPIXFC_SP_CTRL 412 * @brief SPIX Controller Special Control Register. 413 * @{ 414 */ 415 #define MXC_F_SPIXFC_SP_CTRL_SAMPL_POS 0 /**< SP_CTRL_SAMPL Position */ 416 #define MXC_F_SPIXFC_SP_CTRL_SAMPL ((uint32_t)(0x1UL << MXC_F_SPIXFC_SP_CTRL_SAMPL_POS)) /**< SP_CTRL_SAMPL Mask */ 417 #define MXC_V_SPIXFC_SP_CTRL_SAMPL_DIS ((uint32_t)0x0UL) /**< SP_CTRL_SAMPL_DIS Value */ 418 #define MXC_S_SPIXFC_SP_CTRL_SAMPL_DIS (MXC_V_SPIXFC_SP_CTRL_SAMPL_DIS << MXC_F_SPIXFC_SP_CTRL_SAMPL_POS) /**< SP_CTRL_SAMPL_DIS Setting */ 419 #define MXC_V_SPIXFC_SP_CTRL_SAMPL_EN ((uint32_t)0x1UL) /**< SP_CTRL_SAMPL_EN Value */ 420 #define MXC_S_SPIXFC_SP_CTRL_SAMPL_EN (MXC_V_SPIXFC_SP_CTRL_SAMPL_EN << MXC_F_SPIXFC_SP_CTRL_SAMPL_POS) /**< SP_CTRL_SAMPL_EN Setting */ 421 422 #define MXC_F_SPIXFC_SP_CTRL_SDIO_OUT_POS 4 /**< SP_CTRL_SDIO_OUT Position */ 423 #define MXC_F_SPIXFC_SP_CTRL_SDIO_OUT ((uint32_t)(0xFUL << MXC_F_SPIXFC_SP_CTRL_SDIO_OUT_POS)) /**< SP_CTRL_SDIO_OUT Mask */ 424 #define MXC_V_SPIXFC_SP_CTRL_SDIO_OUT_SDIO0 ((uint32_t)0x1UL) /**< SP_CTRL_SDIO_OUT_SDIO0 Value */ 425 #define MXC_S_SPIXFC_SP_CTRL_SDIO_OUT_SDIO0 (MXC_V_SPIXFC_SP_CTRL_SDIO_OUT_SDIO0 << MXC_F_SPIXFC_SP_CTRL_SDIO_OUT_POS) /**< SP_CTRL_SDIO_OUT_SDIO0 Setting */ 426 #define MXC_V_SPIXFC_SP_CTRL_SDIO_OUT_SDIO1 ((uint32_t)0x2UL) /**< SP_CTRL_SDIO_OUT_SDIO1 Value */ 427 #define MXC_S_SPIXFC_SP_CTRL_SDIO_OUT_SDIO1 (MXC_V_SPIXFC_SP_CTRL_SDIO_OUT_SDIO1 << MXC_F_SPIXFC_SP_CTRL_SDIO_OUT_POS) /**< SP_CTRL_SDIO_OUT_SDIO1 Setting */ 428 #define MXC_V_SPIXFC_SP_CTRL_SDIO_OUT_SDIO2 ((uint32_t)0x4UL) /**< SP_CTRL_SDIO_OUT_SDIO2 Value */ 429 #define MXC_S_SPIXFC_SP_CTRL_SDIO_OUT_SDIO2 (MXC_V_SPIXFC_SP_CTRL_SDIO_OUT_SDIO2 << MXC_F_SPIXFC_SP_CTRL_SDIO_OUT_POS) /**< SP_CTRL_SDIO_OUT_SDIO2 Setting */ 430 #define MXC_V_SPIXFC_SP_CTRL_SDIO_OUT_SDIO3 ((uint32_t)0x8UL) /**< SP_CTRL_SDIO_OUT_SDIO3 Value */ 431 #define MXC_S_SPIXFC_SP_CTRL_SDIO_OUT_SDIO3 (MXC_V_SPIXFC_SP_CTRL_SDIO_OUT_SDIO3 << MXC_F_SPIXFC_SP_CTRL_SDIO_OUT_POS) /**< SP_CTRL_SDIO_OUT_SDIO3 Setting */ 432 433 #define MXC_F_SPIXFC_SP_CTRL_SDIO_OUT_EN_POS 8 /**< SP_CTRL_SDIO_OUT_EN Position */ 434 #define MXC_F_SPIXFC_SP_CTRL_SDIO_OUT_EN ((uint32_t)(0xFUL << MXC_F_SPIXFC_SP_CTRL_SDIO_OUT_EN_POS)) /**< SP_CTRL_SDIO_OUT_EN Mask */ 435 #define MXC_V_SPIXFC_SP_CTRL_SDIO_OUT_EN_SDIO0 ((uint32_t)0x1UL) /**< SP_CTRL_SDIO_OUT_EN_SDIO0 Value */ 436 #define MXC_S_SPIXFC_SP_CTRL_SDIO_OUT_EN_SDIO0 (MXC_V_SPIXFC_SP_CTRL_SDIO_OUT_EN_SDIO0 << MXC_F_SPIXFC_SP_CTRL_SDIO_OUT_EN_POS) /**< SP_CTRL_SDIO_OUT_EN_SDIO0 Setting */ 437 #define MXC_V_SPIXFC_SP_CTRL_SDIO_OUT_EN_SDIO1 ((uint32_t)0x2UL) /**< SP_CTRL_SDIO_OUT_EN_SDIO1 Value */ 438 #define MXC_S_SPIXFC_SP_CTRL_SDIO_OUT_EN_SDIO1 (MXC_V_SPIXFC_SP_CTRL_SDIO_OUT_EN_SDIO1 << MXC_F_SPIXFC_SP_CTRL_SDIO_OUT_EN_POS) /**< SP_CTRL_SDIO_OUT_EN_SDIO1 Setting */ 439 #define MXC_V_SPIXFC_SP_CTRL_SDIO_OUT_EN_SDIO2 ((uint32_t)0x4UL) /**< SP_CTRL_SDIO_OUT_EN_SDIO2 Value */ 440 #define MXC_S_SPIXFC_SP_CTRL_SDIO_OUT_EN_SDIO2 (MXC_V_SPIXFC_SP_CTRL_SDIO_OUT_EN_SDIO2 << MXC_F_SPIXFC_SP_CTRL_SDIO_OUT_EN_POS) /**< SP_CTRL_SDIO_OUT_EN_SDIO2 Setting */ 441 #define MXC_V_SPIXFC_SP_CTRL_SDIO_OUT_EN_SDIO3 ((uint32_t)0x8UL) /**< SP_CTRL_SDIO_OUT_EN_SDIO3 Value */ 442 #define MXC_S_SPIXFC_SP_CTRL_SDIO_OUT_EN_SDIO3 (MXC_V_SPIXFC_SP_CTRL_SDIO_OUT_EN_SDIO3 << MXC_F_SPIXFC_SP_CTRL_SDIO_OUT_EN_POS) /**< SP_CTRL_SDIO_OUT_EN_SDIO3 Setting */ 443 444 #define MXC_F_SPIXFC_SP_CTRL_SCKINH3_POS 16 /**< SP_CTRL_SCKINH3 Position */ 445 #define MXC_F_SPIXFC_SP_CTRL_SCKINH3 ((uint32_t)(0x1UL << MXC_F_SPIXFC_SP_CTRL_SCKINH3_POS)) /**< SP_CTRL_SCKINH3 Mask */ 446 #define MXC_V_SPIXFC_SP_CTRL_SCKINH3_EN ((uint32_t)0x0UL) /**< SP_CTRL_SCKINH3_EN Value */ 447 #define MXC_S_SPIXFC_SP_CTRL_SCKINH3_EN (MXC_V_SPIXFC_SP_CTRL_SCKINH3_EN << MXC_F_SPIXFC_SP_CTRL_SCKINH3_POS) /**< SP_CTRL_SCKINH3_EN Setting */ 448 #define MXC_V_SPIXFC_SP_CTRL_SCKINH3_DIS ((uint32_t)0x1UL) /**< SP_CTRL_SCKINH3_DIS Value */ 449 #define MXC_S_SPIXFC_SP_CTRL_SCKINH3_DIS (MXC_V_SPIXFC_SP_CTRL_SCKINH3_DIS << MXC_F_SPIXFC_SP_CTRL_SCKINH3_POS) /**< SP_CTRL_SCKINH3_DIS Setting */ 450 451 /**@} end of group SPIXFC_SP_CTRL_Register */ 452 453 /** 454 * @ingroup spixfc_registers 455 * @defgroup SPIXFC_INT_FL SPIXFC_INT_FL 456 * @brief SPIX Controller Interrupt Status Register. 457 * @{ 458 */ 459 #define MXC_F_SPIXFC_INT_FL_TSTALL_POS 0 /**< INT_FL_TSTALL Position */ 460 #define MXC_F_SPIXFC_INT_FL_TSTALL ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_FL_TSTALL_POS)) /**< INT_FL_TSTALL Mask */ 461 #define MXC_V_SPIXFC_INT_FL_TSTALL_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TSTALL_CLEAR Value */ 462 #define MXC_S_SPIXFC_INT_FL_TSTALL_CLEAR (MXC_V_SPIXFC_INT_FL_TSTALL_CLEAR << MXC_F_SPIXFC_INT_FL_TSTALL_POS) /**< INT_FL_TSTALL_CLEAR Setting */ 463 464 #define MXC_F_SPIXFC_INT_FL_RSTALL_POS 1 /**< INT_FL_RSTALL Position */ 465 #define MXC_F_SPIXFC_INT_FL_RSTALL ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_FL_RSTALL_POS)) /**< INT_FL_RSTALL Mask */ 466 #define MXC_V_SPIXFC_INT_FL_RSTALL_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RSTALL_CLEAR Value */ 467 #define MXC_S_SPIXFC_INT_FL_RSTALL_CLEAR (MXC_V_SPIXFC_INT_FL_RSTALL_CLEAR << MXC_F_SPIXFC_INT_FL_RSTALL_POS) /**< INT_FL_RSTALL_CLEAR Setting */ 468 469 #define MXC_F_SPIXFC_INT_FL_TRDY_POS 2 /**< INT_FL_TRDY Position */ 470 #define MXC_F_SPIXFC_INT_FL_TRDY ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_FL_TRDY_POS)) /**< INT_FL_TRDY Mask */ 471 #define MXC_V_SPIXFC_INT_FL_TRDY_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TRDY_CLEAR Value */ 472 #define MXC_S_SPIXFC_INT_FL_TRDY_CLEAR (MXC_V_SPIXFC_INT_FL_TRDY_CLEAR << MXC_F_SPIXFC_INT_FL_TRDY_POS) /**< INT_FL_TRDY_CLEAR Setting */ 473 474 #define MXC_F_SPIXFC_INT_FL_RDONE_POS 3 /**< INT_FL_RDONE Position */ 475 #define MXC_F_SPIXFC_INT_FL_RDONE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_FL_RDONE_POS)) /**< INT_FL_RDONE Mask */ 476 #define MXC_V_SPIXFC_INT_FL_RDONE_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RDONE_CLEAR Value */ 477 #define MXC_S_SPIXFC_INT_FL_RDONE_CLEAR (MXC_V_SPIXFC_INT_FL_RDONE_CLEAR << MXC_F_SPIXFC_INT_FL_RDONE_POS) /**< INT_FL_RDONE_CLEAR Setting */ 478 479 #define MXC_F_SPIXFC_INT_FL_TFIFOAE_POS 4 /**< INT_FL_TFIFOAE Position */ 480 #define MXC_F_SPIXFC_INT_FL_TFIFOAE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_FL_TFIFOAE_POS)) /**< INT_FL_TFIFOAE Mask */ 481 #define MXC_V_SPIXFC_INT_FL_TFIFOAE_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TFIFOAE_CLEAR Value */ 482 #define MXC_S_SPIXFC_INT_FL_TFIFOAE_CLEAR (MXC_V_SPIXFC_INT_FL_TFIFOAE_CLEAR << MXC_F_SPIXFC_INT_FL_TFIFOAE_POS) /**< INT_FL_TFIFOAE_CLEAR Setting */ 483 484 #define MXC_F_SPIXFC_INT_FL_RFIFOAF_POS 5 /**< INT_FL_RFIFOAF Position */ 485 #define MXC_F_SPIXFC_INT_FL_RFIFOAF ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_FL_RFIFOAF_POS)) /**< INT_FL_RFIFOAF Mask */ 486 #define MXC_V_SPIXFC_INT_FL_RFIFOAF_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RFIFOAF_CLEAR Value */ 487 #define MXC_S_SPIXFC_INT_FL_RFIFOAF_CLEAR (MXC_V_SPIXFC_INT_FL_RFIFOAF_CLEAR << MXC_F_SPIXFC_INT_FL_RFIFOAF_POS) /**< INT_FL_RFIFOAF_CLEAR Setting */ 488 489 /**@} end of group SPIXFC_INT_FL_Register */ 490 491 /** 492 * @ingroup spixfc_registers 493 * @defgroup SPIXFC_INT_EN SPIXFC_INT_EN 494 * @brief SPIX Controller Interrupt Enable Register. 495 * @{ 496 */ 497 #define MXC_F_SPIXFC_INT_EN_TSTALLIE_POS 0 /**< INT_EN_TSTALLIE Position */ 498 #define MXC_F_SPIXFC_INT_EN_TSTALLIE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_EN_TSTALLIE_POS)) /**< INT_EN_TSTALLIE Mask */ 499 #define MXC_V_SPIXFC_INT_EN_TSTALLIE_DIS ((uint32_t)0x0UL) /**< INT_EN_TSTALLIE_DIS Value */ 500 #define MXC_S_SPIXFC_INT_EN_TSTALLIE_DIS (MXC_V_SPIXFC_INT_EN_TSTALLIE_DIS << MXC_F_SPIXFC_INT_EN_TSTALLIE_POS) /**< INT_EN_TSTALLIE_DIS Setting */ 501 #define MXC_V_SPIXFC_INT_EN_TSTALLIE_EN ((uint32_t)0x1UL) /**< INT_EN_TSTALLIE_EN Value */ 502 #define MXC_S_SPIXFC_INT_EN_TSTALLIE_EN (MXC_V_SPIXFC_INT_EN_TSTALLIE_EN << MXC_F_SPIXFC_INT_EN_TSTALLIE_POS) /**< INT_EN_TSTALLIE_EN Setting */ 503 504 #define MXC_F_SPIXFC_INT_EN_RSTALLIE_POS 1 /**< INT_EN_RSTALLIE Position */ 505 #define MXC_F_SPIXFC_INT_EN_RSTALLIE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_EN_RSTALLIE_POS)) /**< INT_EN_RSTALLIE Mask */ 506 #define MXC_V_SPIXFC_INT_EN_RSTALLIE_DIS ((uint32_t)0x0UL) /**< INT_EN_RSTALLIE_DIS Value */ 507 #define MXC_S_SPIXFC_INT_EN_RSTALLIE_DIS (MXC_V_SPIXFC_INT_EN_RSTALLIE_DIS << MXC_F_SPIXFC_INT_EN_RSTALLIE_POS) /**< INT_EN_RSTALLIE_DIS Setting */ 508 #define MXC_V_SPIXFC_INT_EN_RSTALLIE_EN ((uint32_t)0x1UL) /**< INT_EN_RSTALLIE_EN Value */ 509 #define MXC_S_SPIXFC_INT_EN_RSTALLIE_EN (MXC_V_SPIXFC_INT_EN_RSTALLIE_EN << MXC_F_SPIXFC_INT_EN_RSTALLIE_POS) /**< INT_EN_RSTALLIE_EN Setting */ 510 511 #define MXC_F_SPIXFC_INT_EN_TRDYIE_POS 2 /**< INT_EN_TRDYIE Position */ 512 #define MXC_F_SPIXFC_INT_EN_TRDYIE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_EN_TRDYIE_POS)) /**< INT_EN_TRDYIE Mask */ 513 #define MXC_V_SPIXFC_INT_EN_TRDYIE_DIS ((uint32_t)0x0UL) /**< INT_EN_TRDYIE_DIS Value */ 514 #define MXC_S_SPIXFC_INT_EN_TRDYIE_DIS (MXC_V_SPIXFC_INT_EN_TRDYIE_DIS << MXC_F_SPIXFC_INT_EN_TRDYIE_POS) /**< INT_EN_TRDYIE_DIS Setting */ 515 #define MXC_V_SPIXFC_INT_EN_TRDYIE_EN ((uint32_t)0x1UL) /**< INT_EN_TRDYIE_EN Value */ 516 #define MXC_S_SPIXFC_INT_EN_TRDYIE_EN (MXC_V_SPIXFC_INT_EN_TRDYIE_EN << MXC_F_SPIXFC_INT_EN_TRDYIE_POS) /**< INT_EN_TRDYIE_EN Setting */ 517 518 #define MXC_F_SPIXFC_INT_EN_RDONEIE_POS 3 /**< INT_EN_RDONEIE Position */ 519 #define MXC_F_SPIXFC_INT_EN_RDONEIE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_EN_RDONEIE_POS)) /**< INT_EN_RDONEIE Mask */ 520 #define MXC_V_SPIXFC_INT_EN_RDONEIE_DIS ((uint32_t)0x0UL) /**< INT_EN_RDONEIE_DIS Value */ 521 #define MXC_S_SPIXFC_INT_EN_RDONEIE_DIS (MXC_V_SPIXFC_INT_EN_RDONEIE_DIS << MXC_F_SPIXFC_INT_EN_RDONEIE_POS) /**< INT_EN_RDONEIE_DIS Setting */ 522 #define MXC_V_SPIXFC_INT_EN_RDONEIE_EN ((uint32_t)0x1UL) /**< INT_EN_RDONEIE_EN Value */ 523 #define MXC_S_SPIXFC_INT_EN_RDONEIE_EN (MXC_V_SPIXFC_INT_EN_RDONEIE_EN << MXC_F_SPIXFC_INT_EN_RDONEIE_POS) /**< INT_EN_RDONEIE_EN Setting */ 524 525 #define MXC_F_SPIXFC_INT_EN_TFIFOAEIE_POS 4 /**< INT_EN_TFIFOAEIE Position */ 526 #define MXC_F_SPIXFC_INT_EN_TFIFOAEIE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_EN_TFIFOAEIE_POS)) /**< INT_EN_TFIFOAEIE Mask */ 527 #define MXC_V_SPIXFC_INT_EN_TFIFOAEIE_DIS ((uint32_t)0x0UL) /**< INT_EN_TFIFOAEIE_DIS Value */ 528 #define MXC_S_SPIXFC_INT_EN_TFIFOAEIE_DIS (MXC_V_SPIXFC_INT_EN_TFIFOAEIE_DIS << MXC_F_SPIXFC_INT_EN_TFIFOAEIE_POS) /**< INT_EN_TFIFOAEIE_DIS Setting */ 529 #define MXC_V_SPIXFC_INT_EN_TFIFOAEIE_EN ((uint32_t)0x1UL) /**< INT_EN_TFIFOAEIE_EN Value */ 530 #define MXC_S_SPIXFC_INT_EN_TFIFOAEIE_EN (MXC_V_SPIXFC_INT_EN_TFIFOAEIE_EN << MXC_F_SPIXFC_INT_EN_TFIFOAEIE_POS) /**< INT_EN_TFIFOAEIE_EN Setting */ 531 532 #define MXC_F_SPIXFC_INT_EN_RFIFOAFIE_POS 5 /**< INT_EN_RFIFOAFIE Position */ 533 #define MXC_F_SPIXFC_INT_EN_RFIFOAFIE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_EN_RFIFOAFIE_POS)) /**< INT_EN_RFIFOAFIE Mask */ 534 #define MXC_V_SPIXFC_INT_EN_RFIFOAFIE_DIS ((uint32_t)0x0UL) /**< INT_EN_RFIFOAFIE_DIS Value */ 535 #define MXC_S_SPIXFC_INT_EN_RFIFOAFIE_DIS (MXC_V_SPIXFC_INT_EN_RFIFOAFIE_DIS << MXC_F_SPIXFC_INT_EN_RFIFOAFIE_POS) /**< INT_EN_RFIFOAFIE_DIS Setting */ 536 #define MXC_V_SPIXFC_INT_EN_RFIFOAFIE_EN ((uint32_t)0x1UL) /**< INT_EN_RFIFOAFIE_EN Value */ 537 #define MXC_S_SPIXFC_INT_EN_RFIFOAFIE_EN (MXC_V_SPIXFC_INT_EN_RFIFOAFIE_EN << MXC_F_SPIXFC_INT_EN_RFIFOAFIE_POS) /**< INT_EN_RFIFOAFIE_EN Setting */ 538 539 /**@} end of group SPIXFC_INT_EN_Register */ 540 541 #ifdef __cplusplus 542 } 543 #endif 544 545 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SPIXFC_REGS_H_ 546
