1 /** 2 * @file spixf_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPIXF Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup spixf_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SPIXF_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SPIXF_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup spixf 67 * @defgroup spixf_registers SPIXF_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SPIXF Peripheral Module. 69 * @details SPIXF Master 70 */ 71 72 /** 73 * @ingroup spixf_registers 74 * Structure type to access the SPIXF Registers. 75 */ 76 typedef struct { 77 __IO uint32_t cfg; /**< <tt>\b 0x00:</tt> SPIXF CFG Register */ 78 __IO uint32_t fetch_ctrl; /**< <tt>\b 0x04:</tt> SPIXF FETCH_CTRL Register */ 79 __IO uint32_t mode_ctrl; /**< <tt>\b 0x08:</tt> SPIXF MODE_CTRL Register */ 80 __IO uint32_t mode_data; /**< <tt>\b 0x0C:</tt> SPIXF MODE_DATA Register */ 81 __IO uint32_t fb_ctrl; /**< <tt>\b 0x10:</tt> SPIXF FB_CTRL Register */ 82 __R uint32_t rsv_0x14_0x1b[2]; 83 __IO uint32_t io_ctrl; /**< <tt>\b 0x1C:</tt> SPIXF IO_CTRL Register */ 84 __IO uint32_t sec_ctrl; /**< <tt>\b 0x20:</tt> SPIXF SEC_CTRL Register */ 85 __IO uint32_t bus_idle; /**< <tt>\b 0x24:</tt> SPIXF BUS_IDLE Register */ 86 } mxc_spixf_regs_t; 87 88 /* Register offsets for module SPIXF */ 89 /** 90 * @ingroup spixf_registers 91 * @defgroup SPIXF_Register_Offsets Register Offsets 92 * @brief SPIXF Peripheral Register Offsets from the SPIXF Base Peripheral Address. 93 * @{ 94 */ 95 #define MXC_R_SPIXF_CFG ((uint32_t)0x00000000UL) /**< Offset from SPIXF Base Address: <tt> 0x0000</tt> */ 96 #define MXC_R_SPIXF_FETCH_CTRL ((uint32_t)0x00000004UL) /**< Offset from SPIXF Base Address: <tt> 0x0004</tt> */ 97 #define MXC_R_SPIXF_MODE_CTRL ((uint32_t)0x00000008UL) /**< Offset from SPIXF Base Address: <tt> 0x0008</tt> */ 98 #define MXC_R_SPIXF_MODE_DATA ((uint32_t)0x0000000CUL) /**< Offset from SPIXF Base Address: <tt> 0x000C</tt> */ 99 #define MXC_R_SPIXF_FB_CTRL ((uint32_t)0x00000010UL) /**< Offset from SPIXF Base Address: <tt> 0x0010</tt> */ 100 #define MXC_R_SPIXF_IO_CTRL ((uint32_t)0x0000001CUL) /**< Offset from SPIXF Base Address: <tt> 0x001C</tt> */ 101 #define MXC_R_SPIXF_SEC_CTRL ((uint32_t)0x00000020UL) /**< Offset from SPIXF Base Address: <tt> 0x0020</tt> */ 102 #define MXC_R_SPIXF_BUS_IDLE ((uint32_t)0x00000024UL) /**< Offset from SPIXF Base Address: <tt> 0x0024</tt> */ 103 /**@} end of group spixf_registers */ 104 105 /** 106 * @ingroup spixf_registers 107 * @defgroup SPIXF_CFG SPIXF_CFG 108 * @brief SPIX Configuration Register. 109 * @{ 110 */ 111 #define MXC_F_SPIXF_CFG_MODE_POS 0 /**< CFG_MODE Position */ 112 #define MXC_F_SPIXF_CFG_MODE ((uint32_t)(0x3UL << MXC_F_SPIXF_CFG_MODE_POS)) /**< CFG_MODE Mask */ 113 #define MXC_V_SPIXF_CFG_MODE_MODE0 ((uint32_t)0x0UL) /**< CFG_MODE_MODE0 Value */ 114 #define MXC_S_SPIXF_CFG_MODE_MODE0 (MXC_V_SPIXF_CFG_MODE_MODE0 << MXC_F_SPIXF_CFG_MODE_POS) /**< CFG_MODE_MODE0 Setting */ 115 #define MXC_V_SPIXF_CFG_MODE_MODE3 ((uint32_t)0x3UL) /**< CFG_MODE_MODE3 Value */ 116 #define MXC_S_SPIXF_CFG_MODE_MODE3 (MXC_V_SPIXF_CFG_MODE_MODE3 << MXC_F_SPIXF_CFG_MODE_POS) /**< CFG_MODE_MODE3 Setting */ 117 118 #define MXC_F_SPIXF_CFG_SSPOL_POS 2 /**< CFG_SSPOL Position */ 119 #define MXC_F_SPIXF_CFG_SSPOL ((uint32_t)(0x1UL << MXC_F_SPIXF_CFG_SSPOL_POS)) /**< CFG_SSPOL Mask */ 120 #define MXC_V_SPIXF_CFG_SSPOL_ACTIVEHI ((uint32_t)0x0UL) /**< CFG_SSPOL_ACTIVEHI Value */ 121 #define MXC_S_SPIXF_CFG_SSPOL_ACTIVEHI (MXC_V_SPIXF_CFG_SSPOL_ACTIVEHI << MXC_F_SPIXF_CFG_SSPOL_POS) /**< CFG_SSPOL_ACTIVEHI Setting */ 122 #define MXC_V_SPIXF_CFG_SSPOL_ACTIVELO ((uint32_t)0x1UL) /**< CFG_SSPOL_ACTIVELO Value */ 123 #define MXC_S_SPIXF_CFG_SSPOL_ACTIVELO (MXC_V_SPIXF_CFG_SSPOL_ACTIVELO << MXC_F_SPIXF_CFG_SSPOL_POS) /**< CFG_SSPOL_ACTIVELO Setting */ 124 125 #define MXC_F_SPIXF_CFG_SSEL_POS 4 /**< CFG_SSEL Position */ 126 #define MXC_F_SPIXF_CFG_SSEL ((uint32_t)(0x7UL << MXC_F_SPIXF_CFG_SSEL_POS)) /**< CFG_SSEL Mask */ 127 #define MXC_V_SPIXF_CFG_SSEL_SLAVE0 ((uint32_t)0x0UL) /**< CFG_SSEL_SLAVE0 Value */ 128 #define MXC_S_SPIXF_CFG_SSEL_SLAVE0 (MXC_V_SPIXF_CFG_SSEL_SLAVE0 << MXC_F_SPIXF_CFG_SSEL_POS) /**< CFG_SSEL_SLAVE0 Setting */ 129 130 #define MXC_F_SPIXF_CFG_LOCLK_POS 8 /**< CFG_LOCLK Position */ 131 #define MXC_F_SPIXF_CFG_LOCLK ((uint32_t)(0xFUL << MXC_F_SPIXF_CFG_LOCLK_POS)) /**< CFG_LOCLK Mask */ 132 133 #define MXC_F_SPIXF_CFG_HICLK_POS 12 /**< CFG_HICLK Position */ 134 #define MXC_F_SPIXF_CFG_HICLK ((uint32_t)(0xFUL << MXC_F_SPIXF_CFG_HICLK_POS)) /**< CFG_HICLK Mask */ 135 136 #define MXC_F_SPIXF_CFG_SSACT_POS 16 /**< CFG_SSACT Position */ 137 #define MXC_F_SPIXF_CFG_SSACT ((uint32_t)(0x3UL << MXC_F_SPIXF_CFG_SSACT_POS)) /**< CFG_SSACT Mask */ 138 #define MXC_V_SPIXF_CFG_SSACT_OFF ((uint32_t)0x0UL) /**< CFG_SSACT_OFF Value */ 139 #define MXC_S_SPIXF_CFG_SSACT_OFF (MXC_V_SPIXF_CFG_SSACT_OFF << MXC_F_SPIXF_CFG_SSACT_POS) /**< CFG_SSACT_OFF Setting */ 140 #define MXC_V_SPIXF_CFG_SSACT_2CLK ((uint32_t)0x1UL) /**< CFG_SSACT_2CLK Value */ 141 #define MXC_S_SPIXF_CFG_SSACT_2CLK (MXC_V_SPIXF_CFG_SSACT_2CLK << MXC_F_SPIXF_CFG_SSACT_POS) /**< CFG_SSACT_2CLK Setting */ 142 #define MXC_V_SPIXF_CFG_SSACT_4CLK ((uint32_t)0x2UL) /**< CFG_SSACT_4CLK Value */ 143 #define MXC_S_SPIXF_CFG_SSACT_4CLK (MXC_V_SPIXF_CFG_SSACT_4CLK << MXC_F_SPIXF_CFG_SSACT_POS) /**< CFG_SSACT_4CLK Setting */ 144 #define MXC_V_SPIXF_CFG_SSACT_8CLK ((uint32_t)0x3UL) /**< CFG_SSACT_8CLK Value */ 145 #define MXC_S_SPIXF_CFG_SSACT_8CLK (MXC_V_SPIXF_CFG_SSACT_8CLK << MXC_F_SPIXF_CFG_SSACT_POS) /**< CFG_SSACT_8CLK Setting */ 146 147 #define MXC_F_SPIXF_CFG_SSIACT_POS 18 /**< CFG_SSIACT Position */ 148 #define MXC_F_SPIXF_CFG_SSIACT ((uint32_t)(0x3UL << MXC_F_SPIXF_CFG_SSIACT_POS)) /**< CFG_SSIACT Mask */ 149 #define MXC_V_SPIXF_CFG_SSIACT_1CLK ((uint32_t)0x0UL) /**< CFG_SSIACT_1CLK Value */ 150 #define MXC_S_SPIXF_CFG_SSIACT_1CLK (MXC_V_SPIXF_CFG_SSIACT_1CLK << MXC_F_SPIXF_CFG_SSIACT_POS) /**< CFG_SSIACT_1CLK Setting */ 151 #define MXC_V_SPIXF_CFG_SSIACT_3CLK ((uint32_t)0x1UL) /**< CFG_SSIACT_3CLK Value */ 152 #define MXC_S_SPIXF_CFG_SSIACT_3CLK (MXC_V_SPIXF_CFG_SSIACT_3CLK << MXC_F_SPIXF_CFG_SSIACT_POS) /**< CFG_SSIACT_3CLK Setting */ 153 #define MXC_V_SPIXF_CFG_SSIACT_5CLK ((uint32_t)0x2UL) /**< CFG_SSIACT_5CLK Value */ 154 #define MXC_S_SPIXF_CFG_SSIACT_5CLK (MXC_V_SPIXF_CFG_SSIACT_5CLK << MXC_F_SPIXF_CFG_SSIACT_POS) /**< CFG_SSIACT_5CLK Setting */ 155 #define MXC_V_SPIXF_CFG_SSIACT_9CLK ((uint32_t)0x3UL) /**< CFG_SSIACT_9CLK Value */ 156 #define MXC_S_SPIXF_CFG_SSIACT_9CLK (MXC_V_SPIXF_CFG_SSIACT_9CLK << MXC_F_SPIXF_CFG_SSIACT_POS) /**< CFG_SSIACT_9CLK Setting */ 157 158 /**@} end of group SPIXF_CFG_Register */ 159 160 /** 161 * @ingroup spixf_registers 162 * @defgroup SPIXF_FETCH_CTRL SPIXF_FETCH_CTRL 163 * @brief SPIX Fetch Control Register. 164 * @{ 165 */ 166 #define MXC_F_SPIXF_FETCH_CTRL_CMDVAL_POS 0 /**< FETCH_CTRL_CMDVAL Position */ 167 #define MXC_F_SPIXF_FETCH_CTRL_CMDVAL ((uint32_t)(0xFFUL << MXC_F_SPIXF_FETCH_CTRL_CMDVAL_POS)) /**< FETCH_CTRL_CMDVAL Mask */ 168 169 #define MXC_F_SPIXF_FETCH_CTRL_CMDWTH_POS 8 /**< FETCH_CTRL_CMDWTH Position */ 170 #define MXC_F_SPIXF_FETCH_CTRL_CMDWTH ((uint32_t)(0x3UL << MXC_F_SPIXF_FETCH_CTRL_CMDWTH_POS)) /**< FETCH_CTRL_CMDWTH Mask */ 171 #define MXC_V_SPIXF_FETCH_CTRL_CMDWTH_MONO ((uint32_t)0x0UL) /**< FETCH_CTRL_CMDWTH_MONO Value */ 172 #define MXC_S_SPIXF_FETCH_CTRL_CMDWTH_MONO (MXC_V_SPIXF_FETCH_CTRL_CMDWTH_MONO << MXC_F_SPIXF_FETCH_CTRL_CMDWTH_POS) /**< FETCH_CTRL_CMDWTH_MONO Setting */ 173 #define MXC_V_SPIXF_FETCH_CTRL_CMDWTH_DUAL ((uint32_t)0x1UL) /**< FETCH_CTRL_CMDWTH_DUAL Value */ 174 #define MXC_S_SPIXF_FETCH_CTRL_CMDWTH_DUAL (MXC_V_SPIXF_FETCH_CTRL_CMDWTH_DUAL << MXC_F_SPIXF_FETCH_CTRL_CMDWTH_POS) /**< FETCH_CTRL_CMDWTH_DUAL Setting */ 175 #define MXC_V_SPIXF_FETCH_CTRL_CMDWTH_QUAD ((uint32_t)0x2UL) /**< FETCH_CTRL_CMDWTH_QUAD Value */ 176 #define MXC_S_SPIXF_FETCH_CTRL_CMDWTH_QUAD (MXC_V_SPIXF_FETCH_CTRL_CMDWTH_QUAD << MXC_F_SPIXF_FETCH_CTRL_CMDWTH_POS) /**< FETCH_CTRL_CMDWTH_QUAD Setting */ 177 #define MXC_V_SPIXF_FETCH_CTRL_CMDWTH_INVALID ((uint32_t)0x3UL) /**< FETCH_CTRL_CMDWTH_INVALID Value */ 178 #define MXC_S_SPIXF_FETCH_CTRL_CMDWTH_INVALID (MXC_V_SPIXF_FETCH_CTRL_CMDWTH_INVALID << MXC_F_SPIXF_FETCH_CTRL_CMDWTH_POS) /**< FETCH_CTRL_CMDWTH_INVALID Setting */ 179 180 #define MXC_F_SPIXF_FETCH_CTRL_ADDR_WIDTH_POS 10 /**< FETCH_CTRL_ADDR_WIDTH Position */ 181 #define MXC_F_SPIXF_FETCH_CTRL_ADDR_WIDTH ((uint32_t)(0x3UL << MXC_F_SPIXF_FETCH_CTRL_ADDR_WIDTH_POS)) /**< FETCH_CTRL_ADDR_WIDTH Mask */ 182 #define MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_SINGLE ((uint32_t)0x0UL) /**< FETCH_CTRL_ADDR_WIDTH_SINGLE Value */ 183 #define MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_SINGLE (MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_SINGLE << MXC_F_SPIXF_FETCH_CTRL_ADDR_WIDTH_POS) /**< FETCH_CTRL_ADDR_WIDTH_SINGLE Setting */ 184 #define MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_DUAL ((uint32_t)0x1UL) /**< FETCH_CTRL_ADDR_WIDTH_DUAL Value */ 185 #define MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_DUAL (MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_DUAL << MXC_F_SPIXF_FETCH_CTRL_ADDR_WIDTH_POS) /**< FETCH_CTRL_ADDR_WIDTH_DUAL Setting */ 186 #define MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_QUAD ((uint32_t)0x2UL) /**< FETCH_CTRL_ADDR_WIDTH_QUAD Value */ 187 #define MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_QUAD (MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_QUAD << MXC_F_SPIXF_FETCH_CTRL_ADDR_WIDTH_POS) /**< FETCH_CTRL_ADDR_WIDTH_QUAD Setting */ 188 #define MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_INVALID ((uint32_t)0x3UL) /**< FETCH_CTRL_ADDR_WIDTH_INVALID Value */ 189 #define MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_INVALID (MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_INVALID << MXC_F_SPIXF_FETCH_CTRL_ADDR_WIDTH_POS) /**< FETCH_CTRL_ADDR_WIDTH_INVALID Setting */ 190 191 #define MXC_F_SPIXF_FETCH_CTRL_DATA_WIDTH_POS 12 /**< FETCH_CTRL_DATA_WIDTH Position */ 192 #define MXC_F_SPIXF_FETCH_CTRL_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPIXF_FETCH_CTRL_DATA_WIDTH_POS)) /**< FETCH_CTRL_DATA_WIDTH Mask */ 193 #define MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_SINGLE ((uint32_t)0x0UL) /**< FETCH_CTRL_DATA_WIDTH_SINGLE Value */ 194 #define MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_SINGLE (MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_SINGLE << MXC_F_SPIXF_FETCH_CTRL_DATA_WIDTH_POS) /**< FETCH_CTRL_DATA_WIDTH_SINGLE Setting */ 195 #define MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< FETCH_CTRL_DATA_WIDTH_DUAL Value */ 196 #define MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_DUAL (MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_DUAL << MXC_F_SPIXF_FETCH_CTRL_DATA_WIDTH_POS) /**< FETCH_CTRL_DATA_WIDTH_DUAL Setting */ 197 #define MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< FETCH_CTRL_DATA_WIDTH_QUAD Value */ 198 #define MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_QUAD (MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_QUAD << MXC_F_SPIXF_FETCH_CTRL_DATA_WIDTH_POS) /**< FETCH_CTRL_DATA_WIDTH_QUAD Setting */ 199 #define MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_INVALID ((uint32_t)0x3UL) /**< FETCH_CTRL_DATA_WIDTH_INVALID Value */ 200 #define MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_INVALID (MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_INVALID << MXC_F_SPIXF_FETCH_CTRL_DATA_WIDTH_POS) /**< FETCH_CTRL_DATA_WIDTH_INVALID Setting */ 201 202 #define MXC_F_SPIXF_FETCH_CTRL_ADDR4_POS 16 /**< FETCH_CTRL_ADDR4 Position */ 203 #define MXC_F_SPIXF_FETCH_CTRL_ADDR4 ((uint32_t)(0x1UL << MXC_F_SPIXF_FETCH_CTRL_ADDR4_POS)) /**< FETCH_CTRL_ADDR4 Mask */ 204 #define MXC_V_SPIXF_FETCH_CTRL_ADDR4_3BYTE ((uint32_t)0x0UL) /**< FETCH_CTRL_ADDR4_3BYTE Value */ 205 #define MXC_S_SPIXF_FETCH_CTRL_ADDR4_3BYTE (MXC_V_SPIXF_FETCH_CTRL_ADDR4_3BYTE << MXC_F_SPIXF_FETCH_CTRL_ADDR4_POS) /**< FETCH_CTRL_ADDR4_3BYTE Setting */ 206 #define MXC_V_SPIXF_FETCH_CTRL_ADDR4_4BYTE ((uint32_t)0x1UL) /**< FETCH_CTRL_ADDR4_4BYTE Value */ 207 #define MXC_S_SPIXF_FETCH_CTRL_ADDR4_4BYTE (MXC_V_SPIXF_FETCH_CTRL_ADDR4_4BYTE << MXC_F_SPIXF_FETCH_CTRL_ADDR4_POS) /**< FETCH_CTRL_ADDR4_4BYTE Setting */ 208 209 /**@} end of group SPIXF_FETCH_CTRL_Register */ 210 211 /** 212 * @ingroup spixf_registers 213 * @defgroup SPIXF_MODE_CTRL SPIXF_MODE_CTRL 214 * @brief SPIX Mode Control Register. 215 * @{ 216 */ 217 #define MXC_F_SPIXF_MODE_CTRL_MDCLK_POS 0 /**< MODE_CTRL_MDCLK Position */ 218 #define MXC_F_SPIXF_MODE_CTRL_MDCLK ((uint32_t)(0xFUL << MXC_F_SPIXF_MODE_CTRL_MDCLK_POS)) /**< MODE_CTRL_MDCLK Mask */ 219 220 #define MXC_F_SPIXF_MODE_CTRL_NOCMD_POS 8 /**< MODE_CTRL_NOCMD Position */ 221 #define MXC_F_SPIXF_MODE_CTRL_NOCMD ((uint32_t)(0x1UL << MXC_F_SPIXF_MODE_CTRL_NOCMD_POS)) /**< MODE_CTRL_NOCMD Mask */ 222 #define MXC_V_SPIXF_MODE_CTRL_NOCMD_ALWAYS ((uint32_t)0x0UL) /**< MODE_CTRL_NOCMD_ALWAYS Value */ 223 #define MXC_S_SPIXF_MODE_CTRL_NOCMD_ALWAYS (MXC_V_SPIXF_MODE_CTRL_NOCMD_ALWAYS << MXC_F_SPIXF_MODE_CTRL_NOCMD_POS) /**< MODE_CTRL_NOCMD_ALWAYS Setting */ 224 #define MXC_V_SPIXF_MODE_CTRL_NOCMD_ONCE ((uint32_t)0x1UL) /**< MODE_CTRL_NOCMD_ONCE Value */ 225 #define MXC_S_SPIXF_MODE_CTRL_NOCMD_ONCE (MXC_V_SPIXF_MODE_CTRL_NOCMD_ONCE << MXC_F_SPIXF_MODE_CTRL_NOCMD_POS) /**< MODE_CTRL_NOCMD_ONCE Setting */ 226 227 #define MXC_F_SPIXF_MODE_CTRL_MODE_SEND_POS 9 /**< MODE_CTRL_MODE_SEND Position */ 228 #define MXC_F_SPIXF_MODE_CTRL_MODE_SEND ((uint32_t)(0x1UL << MXC_F_SPIXF_MODE_CTRL_MODE_SEND_POS)) /**< MODE_CTRL_MODE_SEND Mask */ 229 #define MXC_V_SPIXF_MODE_CTRL_MODE_SEND_NEXT ((uint32_t)0x1UL) /**< MODE_CTRL_MODE_SEND_NEXT Value */ 230 #define MXC_S_SPIXF_MODE_CTRL_MODE_SEND_NEXT (MXC_V_SPIXF_MODE_CTRL_MODE_SEND_NEXT << MXC_F_SPIXF_MODE_CTRL_MODE_SEND_POS) /**< MODE_CTRL_MODE_SEND_NEXT Setting */ 231 232 /**@} end of group SPIXF_MODE_CTRL_Register */ 233 234 /** 235 * @ingroup spixf_registers 236 * @defgroup SPIXF_MODE_DATA SPIXF_MODE_DATA 237 * @brief SPIX Mode Data Register. 238 * @{ 239 */ 240 #define MXC_F_SPIXF_MODE_DATA_MDDATA_POS 0 /**< MODE_DATA_MDDATA Position */ 241 #define MXC_F_SPIXF_MODE_DATA_MDDATA ((uint32_t)(0xFFFFUL << MXC_F_SPIXF_MODE_DATA_MDDATA_POS)) /**< MODE_DATA_MDDATA Mask */ 242 243 #define MXC_F_SPIXF_MODE_DATA_MDOE_POS 16 /**< MODE_DATA_MDOE Position */ 244 #define MXC_F_SPIXF_MODE_DATA_MDOE ((uint32_t)(0xFFFFUL << MXC_F_SPIXF_MODE_DATA_MDOE_POS)) /**< MODE_DATA_MDOE Mask */ 245 246 /**@} end of group SPIXF_MODE_DATA_Register */ 247 248 /** 249 * @ingroup spixf_registers 250 * @defgroup SPIXF_FB_CTRL SPIXF_FB_CTRL 251 * @brief SPIX Feedback Control Register. 252 * @{ 253 */ 254 #define MXC_F_SPIXF_FB_CTRL_FBMD_POS 0 /**< FB_CTRL_FBMD Position */ 255 #define MXC_F_SPIXF_FB_CTRL_FBMD ((uint32_t)(0x1UL << MXC_F_SPIXF_FB_CTRL_FBMD_POS)) /**< FB_CTRL_FBMD Mask */ 256 #define MXC_V_SPIXF_FB_CTRL_FBMD_DIS ((uint32_t)0x0UL) /**< FB_CTRL_FBMD_DIS Value */ 257 #define MXC_S_SPIXF_FB_CTRL_FBMD_DIS (MXC_V_SPIXF_FB_CTRL_FBMD_DIS << MXC_F_SPIXF_FB_CTRL_FBMD_POS) /**< FB_CTRL_FBMD_DIS Setting */ 258 #define MXC_V_SPIXF_FB_CTRL_FBMD_EN ((uint32_t)0x1UL) /**< FB_CTRL_FBMD_EN Value */ 259 #define MXC_S_SPIXF_FB_CTRL_FBMD_EN (MXC_V_SPIXF_FB_CTRL_FBMD_EN << MXC_F_SPIXF_FB_CTRL_FBMD_POS) /**< FB_CTRL_FBMD_EN Setting */ 260 261 #define MXC_F_SPIXF_FB_CTRL_FBINV_POS 1 /**< FB_CTRL_FBINV Position */ 262 #define MXC_F_SPIXF_FB_CTRL_FBINV ((uint32_t)(0x1UL << MXC_F_SPIXF_FB_CTRL_FBINV_POS)) /**< FB_CTRL_FBINV Mask */ 263 #define MXC_V_SPIXF_FB_CTRL_FBINV_DIS ((uint32_t)0x0UL) /**< FB_CTRL_FBINV_DIS Value */ 264 #define MXC_S_SPIXF_FB_CTRL_FBINV_DIS (MXC_V_SPIXF_FB_CTRL_FBINV_DIS << MXC_F_SPIXF_FB_CTRL_FBINV_POS) /**< FB_CTRL_FBINV_DIS Setting */ 265 #define MXC_V_SPIXF_FB_CTRL_FBINV_EN ((uint32_t)0x1UL) /**< FB_CTRL_FBINV_EN Value */ 266 #define MXC_S_SPIXF_FB_CTRL_FBINV_EN (MXC_V_SPIXF_FB_CTRL_FBINV_EN << MXC_F_SPIXF_FB_CTRL_FBINV_POS) /**< FB_CTRL_FBINV_EN Setting */ 267 268 /**@} end of group SPIXF_FB_CTRL_Register */ 269 270 /** 271 * @ingroup spixf_registers 272 * @defgroup SPIXF_IO_CTRL SPIXF_IO_CTRL 273 * @brief SPIX IO Control Register. 274 * @{ 275 */ 276 #define MXC_F_SPIXF_IO_CTRL_SCK_DS_POS 0 /**< IO_CTRL_SCK_DS Position */ 277 #define MXC_F_SPIXF_IO_CTRL_SCK_DS ((uint32_t)(0x1UL << MXC_F_SPIXF_IO_CTRL_SCK_DS_POS)) /**< IO_CTRL_SCK_DS Mask */ 278 #define MXC_V_SPIXF_IO_CTRL_SCK_DS_LOW ((uint32_t)0x0UL) /**< IO_CTRL_SCK_DS_LOW Value */ 279 #define MXC_S_SPIXF_IO_CTRL_SCK_DS_LOW (MXC_V_SPIXF_IO_CTRL_SCK_DS_LOW << MXC_F_SPIXF_IO_CTRL_SCK_DS_POS) /**< IO_CTRL_SCK_DS_LOW Setting */ 280 #define MXC_V_SPIXF_IO_CTRL_SCK_DS_HIGH ((uint32_t)0x1UL) /**< IO_CTRL_SCK_DS_HIGH Value */ 281 #define MXC_S_SPIXF_IO_CTRL_SCK_DS_HIGH (MXC_V_SPIXF_IO_CTRL_SCK_DS_HIGH << MXC_F_SPIXF_IO_CTRL_SCK_DS_POS) /**< IO_CTRL_SCK_DS_HIGH Setting */ 282 283 #define MXC_F_SPIXF_IO_CTRL_SS_DS_POS 1 /**< IO_CTRL_SS_DS Position */ 284 #define MXC_F_SPIXF_IO_CTRL_SS_DS ((uint32_t)(0x1UL << MXC_F_SPIXF_IO_CTRL_SS_DS_POS)) /**< IO_CTRL_SS_DS Mask */ 285 #define MXC_V_SPIXF_IO_CTRL_SS_DS_LOW ((uint32_t)0x0UL) /**< IO_CTRL_SS_DS_LOW Value */ 286 #define MXC_S_SPIXF_IO_CTRL_SS_DS_LOW (MXC_V_SPIXF_IO_CTRL_SS_DS_LOW << MXC_F_SPIXF_IO_CTRL_SS_DS_POS) /**< IO_CTRL_SS_DS_LOW Setting */ 287 #define MXC_V_SPIXF_IO_CTRL_SS_DS_HIGH ((uint32_t)0x1UL) /**< IO_CTRL_SS_DS_HIGH Value */ 288 #define MXC_S_SPIXF_IO_CTRL_SS_DS_HIGH (MXC_V_SPIXF_IO_CTRL_SS_DS_HIGH << MXC_F_SPIXF_IO_CTRL_SS_DS_POS) /**< IO_CTRL_SS_DS_HIGH Setting */ 289 290 #define MXC_F_SPIXF_IO_CTRL_SDIO_DS_POS 2 /**< IO_CTRL_SDIO_DS Position */ 291 #define MXC_F_SPIXF_IO_CTRL_SDIO_DS ((uint32_t)(0x1UL << MXC_F_SPIXF_IO_CTRL_SDIO_DS_POS)) /**< IO_CTRL_SDIO_DS Mask */ 292 #define MXC_V_SPIXF_IO_CTRL_SDIO_DS_LOW ((uint32_t)0x0UL) /**< IO_CTRL_SDIO_DS_LOW Value */ 293 #define MXC_S_SPIXF_IO_CTRL_SDIO_DS_LOW (MXC_V_SPIXF_IO_CTRL_SDIO_DS_LOW << MXC_F_SPIXF_IO_CTRL_SDIO_DS_POS) /**< IO_CTRL_SDIO_DS_LOW Setting */ 294 #define MXC_V_SPIXF_IO_CTRL_SDIO_DS_HIGH ((uint32_t)0x1UL) /**< IO_CTRL_SDIO_DS_HIGH Value */ 295 #define MXC_S_SPIXF_IO_CTRL_SDIO_DS_HIGH (MXC_V_SPIXF_IO_CTRL_SDIO_DS_HIGH << MXC_F_SPIXF_IO_CTRL_SDIO_DS_POS) /**< IO_CTRL_SDIO_DS_HIGH Setting */ 296 297 #define MXC_F_SPIXF_IO_CTRL_PUPDCTRL_POS 3 /**< IO_CTRL_PUPDCTRL Position */ 298 #define MXC_F_SPIXF_IO_CTRL_PUPDCTRL ((uint32_t)(0x3UL << MXC_F_SPIXF_IO_CTRL_PUPDCTRL_POS)) /**< IO_CTRL_PUPDCTRL Mask */ 299 #define MXC_V_SPIXF_IO_CTRL_PUPDCTRL_TRI_STATE ((uint32_t)0x0UL) /**< IO_CTRL_PUPDCTRL_TRI_STATE Value */ 300 #define MXC_S_SPIXF_IO_CTRL_PUPDCTRL_TRI_STATE (MXC_V_SPIXF_IO_CTRL_PUPDCTRL_TRI_STATE << MXC_F_SPIXF_IO_CTRL_PUPDCTRL_POS) /**< IO_CTRL_PUPDCTRL_TRI_STATE Setting */ 301 #define MXC_V_SPIXF_IO_CTRL_PUPDCTRL_PULL_UP ((uint32_t)0x1UL) /**< IO_CTRL_PUPDCTRL_PULL_UP Value */ 302 #define MXC_S_SPIXF_IO_CTRL_PUPDCTRL_PULL_UP (MXC_V_SPIXF_IO_CTRL_PUPDCTRL_PULL_UP << MXC_F_SPIXF_IO_CTRL_PUPDCTRL_POS) /**< IO_CTRL_PUPDCTRL_PULL_UP Setting */ 303 #define MXC_V_SPIXF_IO_CTRL_PUPDCTRL_PULL_DOWN ((uint32_t)0x2UL) /**< IO_CTRL_PUPDCTRL_PULL_DOWN Value */ 304 #define MXC_S_SPIXF_IO_CTRL_PUPDCTRL_PULL_DOWN (MXC_V_SPIXF_IO_CTRL_PUPDCTRL_PULL_DOWN << MXC_F_SPIXF_IO_CTRL_PUPDCTRL_POS) /**< IO_CTRL_PUPDCTRL_PULL_DOWN Setting */ 305 306 /**@} end of group SPIXF_IO_CTRL_Register */ 307 308 /** 309 * @ingroup spixf_registers 310 * @defgroup SPIXF_SEC_CTRL SPIXF_SEC_CTRL 311 * @brief SPIX Memory Security Control Register. 312 * @{ 313 */ 314 #define MXC_F_SPIXF_SEC_CTRL_DEC_EN_POS 0 /**< SEC_CTRL_DEC_EN Position */ 315 #define MXC_F_SPIXF_SEC_CTRL_DEC_EN ((uint32_t)(0x1UL << MXC_F_SPIXF_SEC_CTRL_DEC_EN_POS)) /**< SEC_CTRL_DEC_EN Mask */ 316 #define MXC_V_SPIXF_SEC_CTRL_DEC_EN_DIS ((uint32_t)0x0UL) /**< SEC_CTRL_DEC_EN_DIS Value */ 317 #define MXC_S_SPIXF_SEC_CTRL_DEC_EN_DIS (MXC_V_SPIXF_SEC_CTRL_DEC_EN_DIS << MXC_F_SPIXF_SEC_CTRL_DEC_EN_POS) /**< SEC_CTRL_DEC_EN_DIS Setting */ 318 #define MXC_V_SPIXF_SEC_CTRL_DEC_EN_EN ((uint32_t)0x1UL) /**< SEC_CTRL_DEC_EN_EN Value */ 319 #define MXC_S_SPIXF_SEC_CTRL_DEC_EN_EN (MXC_V_SPIXF_SEC_CTRL_DEC_EN_EN << MXC_F_SPIXF_SEC_CTRL_DEC_EN_POS) /**< SEC_CTRL_DEC_EN_EN Setting */ 320 321 #define MXC_F_SPIXF_SEC_CTRL_AUTH_DISABLE_POS 1 /**< SEC_CTRL_AUTH_DISABLE Position */ 322 #define MXC_F_SPIXF_SEC_CTRL_AUTH_DISABLE ((uint32_t)(0x1UL << MXC_F_SPIXF_SEC_CTRL_AUTH_DISABLE_POS)) /**< SEC_CTRL_AUTH_DISABLE Mask */ 323 #define MXC_V_SPIXF_SEC_CTRL_AUTH_DISABLE_EN ((uint32_t)0x0UL) /**< SEC_CTRL_AUTH_DISABLE_EN Value */ 324 #define MXC_S_SPIXF_SEC_CTRL_AUTH_DISABLE_EN (MXC_V_SPIXF_SEC_CTRL_AUTH_DISABLE_EN << MXC_F_SPIXF_SEC_CTRL_AUTH_DISABLE_POS) /**< SEC_CTRL_AUTH_DISABLE_EN Setting */ 325 #define MXC_V_SPIXF_SEC_CTRL_AUTH_DISABLE_DIS ((uint32_t)0x1UL) /**< SEC_CTRL_AUTH_DISABLE_DIS Value */ 326 #define MXC_S_SPIXF_SEC_CTRL_AUTH_DISABLE_DIS (MXC_V_SPIXF_SEC_CTRL_AUTH_DISABLE_DIS << MXC_F_SPIXF_SEC_CTRL_AUTH_DISABLE_POS) /**< SEC_CTRL_AUTH_DISABLE_DIS Setting */ 327 328 /**@} end of group SPIXF_SEC_CTRL_Register */ 329 330 /** 331 * @ingroup spixf_registers 332 * @defgroup SPIXF_BUS_IDLE SPIXF_BUS_IDLE 333 * @brief Bus Idle 334 * @{ 335 */ 336 #define MXC_F_SPIXF_BUS_IDLE_BUSIDLE_POS 0 /**< BUS_IDLE_BUSIDLE Position */ 337 #define MXC_F_SPIXF_BUS_IDLE_BUSIDLE ((uint32_t)(0xFFFFUL << MXC_F_SPIXF_BUS_IDLE_BUSIDLE_POS)) /**< BUS_IDLE_BUSIDLE Mask */ 338 339 /**@} end of group SPIXF_BUS_IDLE_Register */ 340 341 #ifdef __cplusplus 342 } 343 #endif 344 345 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SPIXF_REGS_H_ 346
