1 /** 2 * @file spimss_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup spimss_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SPIMSS_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SPIMSS_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup spimss 67 * @defgroup spimss_registers SPIMSS_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module. 69 * @details Serial Peripheral Interface. 70 */ 71 72 /** 73 * @ingroup spimss_registers 74 * Structure type to access the SPIMSS Registers. 75 */ 76 typedef struct { 77 __IO uint32_t data; /**< <tt>\b 0x00:</tt> SPIMSS DATA Register */ 78 __IO uint32_t ctrl; /**< <tt>\b 0x04:</tt> SPIMSS CTRL Register */ 79 __IO uint32_t int_fl; /**< <tt>\b 0x08:</tt> SPIMSS INT_FL Register */ 80 __IO uint32_t mod; /**< <tt>\b 0x0C:</tt> SPIMSS MOD Register */ 81 __R uint32_t rsv_0x10; 82 __IO uint32_t brg; /**< <tt>\b 0x14:</tt> SPIMSS BRG Register */ 83 __IO uint32_t dma; /**< <tt>\b 0x18:</tt> SPIMSS DMA Register */ 84 __IO uint32_t i2s_ctrl; /**< <tt>\b 0x1C:</tt> SPIMSS I2S_CTRL Register */ 85 } mxc_spimss_regs_t; 86 87 /* Register offsets for module SPIMSS */ 88 /** 89 * @ingroup spimss_registers 90 * @defgroup SPIMSS_Register_Offsets Register Offsets 91 * @brief SPIMSS Peripheral Register Offsets from the SPIMSS Base Peripheral Address. 92 * @{ 93 */ 94 #define MXC_R_SPIMSS_DATA ((uint32_t)0x00000000UL) /**< Offset from SPIMSS Base Address: <tt> 0x0000</tt> */ 95 #define MXC_R_SPIMSS_CTRL ((uint32_t)0x00000004UL) /**< Offset from SPIMSS Base Address: <tt> 0x0004</tt> */ 96 #define MXC_R_SPIMSS_INT_FL ((uint32_t)0x00000008UL) /**< Offset from SPIMSS Base Address: <tt> 0x0008</tt> */ 97 #define MXC_R_SPIMSS_MOD ((uint32_t)0x0000000CUL) /**< Offset from SPIMSS Base Address: <tt> 0x000C</tt> */ 98 #define MXC_R_SPIMSS_BRG ((uint32_t)0x00000014UL) /**< Offset from SPIMSS Base Address: <tt> 0x0014</tt> */ 99 #define MXC_R_SPIMSS_DMA ((uint32_t)0x00000018UL) /**< Offset from SPIMSS Base Address: <tt> 0x0018</tt> */ 100 #define MXC_R_SPIMSS_I2S_CTRL ((uint32_t)0x0000001CUL) /**< Offset from SPIMSS Base Address: <tt> 0x001C</tt> */ 101 /**@} end of group spimss_registers */ 102 103 /** 104 * @ingroup spimss_registers 105 * @defgroup SPIMSS_DATA SPIMSS_DATA 106 * @brief SPI 16-bit Data Access 107 * @{ 108 */ 109 #define MXC_F_SPIMSS_DATA_DATA_POS 0 /**< DATA_DATA Position */ 110 #define MXC_F_SPIMSS_DATA_DATA ((uint32_t)(0xFFFFUL << MXC_F_SPIMSS_DATA_DATA_POS)) /**< DATA_DATA Mask */ 111 112 /**@} end of group SPIMSS_DATA_Register */ 113 114 /** 115 * @ingroup spimss_registers 116 * @defgroup SPIMSS_CTRL SPIMSS_CTRL 117 * @brief SPI Control Register. 118 * @{ 119 */ 120 #define MXC_F_SPIMSS_CTRL_START_POS 0 /**< CTRL_START Position */ 121 #define MXC_F_SPIMSS_CTRL_START ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_START_POS)) /**< CTRL_START Mask */ 122 #define MXC_V_SPIMSS_CTRL_START_STOP ((uint32_t)0x0UL) /**< CTRL_START_STOP Value */ 123 #define MXC_S_SPIMSS_CTRL_START_STOP (MXC_V_SPIMSS_CTRL_START_STOP << MXC_F_SPIMSS_CTRL_START_POS) /**< CTRL_START_STOP Setting */ 124 #define MXC_V_SPIMSS_CTRL_START_START ((uint32_t)0x1UL) /**< CTRL_START_START Value */ 125 #define MXC_S_SPIMSS_CTRL_START_START (MXC_V_SPIMSS_CTRL_START_START << MXC_F_SPIMSS_CTRL_START_POS) /**< CTRL_START_START Setting */ 126 127 #define MXC_F_SPIMSS_CTRL_MMEN_POS 1 /**< CTRL_MMEN Position */ 128 #define MXC_F_SPIMSS_CTRL_MMEN ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_MMEN_POS)) /**< CTRL_MMEN Mask */ 129 #define MXC_V_SPIMSS_CTRL_MMEN_SLAVE ((uint32_t)0x0UL) /**< CTRL_MMEN_SLAVE Value */ 130 #define MXC_S_SPIMSS_CTRL_MMEN_SLAVE (MXC_V_SPIMSS_CTRL_MMEN_SLAVE << MXC_F_SPIMSS_CTRL_MMEN_POS) /**< CTRL_MMEN_SLAVE Setting */ 131 #define MXC_V_SPIMSS_CTRL_MMEN_MASTER ((uint32_t)0x1UL) /**< CTRL_MMEN_MASTER Value */ 132 #define MXC_S_SPIMSS_CTRL_MMEN_MASTER (MXC_V_SPIMSS_CTRL_MMEN_MASTER << MXC_F_SPIMSS_CTRL_MMEN_POS) /**< CTRL_MMEN_MASTER Setting */ 133 134 #define MXC_F_SPIMSS_CTRL_OD_OUT_EN_POS 2 /**< CTRL_OD_OUT_EN Position */ 135 #define MXC_F_SPIMSS_CTRL_OD_OUT_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_OD_OUT_EN_POS)) /**< CTRL_OD_OUT_EN Mask */ 136 #define MXC_V_SPIMSS_CTRL_OD_OUT_EN_DIS ((uint32_t)0x0UL) /**< CTRL_OD_OUT_EN_DIS Value */ 137 #define MXC_S_SPIMSS_CTRL_OD_OUT_EN_DIS (MXC_V_SPIMSS_CTRL_OD_OUT_EN_DIS << MXC_F_SPIMSS_CTRL_OD_OUT_EN_POS) /**< CTRL_OD_OUT_EN_DIS Setting */ 138 #define MXC_V_SPIMSS_CTRL_OD_OUT_EN_EN ((uint32_t)0x1UL) /**< CTRL_OD_OUT_EN_EN Value */ 139 #define MXC_S_SPIMSS_CTRL_OD_OUT_EN_EN (MXC_V_SPIMSS_CTRL_OD_OUT_EN_EN << MXC_F_SPIMSS_CTRL_OD_OUT_EN_POS) /**< CTRL_OD_OUT_EN_EN Setting */ 140 141 #define MXC_F_SPIMSS_CTRL_CLKPOL_POS 3 /**< CTRL_CLKPOL Position */ 142 #define MXC_F_SPIMSS_CTRL_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_CLKPOL_POS)) /**< CTRL_CLKPOL Mask */ 143 #define MXC_V_SPIMSS_CTRL_CLKPOL_IDLELO ((uint32_t)0x0UL) /**< CTRL_CLKPOL_IDLELO Value */ 144 #define MXC_S_SPIMSS_CTRL_CLKPOL_IDLELO (MXC_V_SPIMSS_CTRL_CLKPOL_IDLELO << MXC_F_SPIMSS_CTRL_CLKPOL_POS) /**< CTRL_CLKPOL_IDLELO Setting */ 145 #define MXC_V_SPIMSS_CTRL_CLKPOL_IDLEHI ((uint32_t)0x1UL) /**< CTRL_CLKPOL_IDLEHI Value */ 146 #define MXC_S_SPIMSS_CTRL_CLKPOL_IDLEHI (MXC_V_SPIMSS_CTRL_CLKPOL_IDLEHI << MXC_F_SPIMSS_CTRL_CLKPOL_POS) /**< CTRL_CLKPOL_IDLEHI Setting */ 147 148 #define MXC_F_SPIMSS_CTRL_PHASE_POS 4 /**< CTRL_PHASE Position */ 149 #define MXC_F_SPIMSS_CTRL_PHASE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_PHASE_POS)) /**< CTRL_PHASE Mask */ 150 #define MXC_V_SPIMSS_CTRL_PHASE_ACTIVEEDGE ((uint32_t)0x0UL) /**< CTRL_PHASE_ACTIVEEDGE Value */ 151 #define MXC_S_SPIMSS_CTRL_PHASE_ACTIVEEDGE (MXC_V_SPIMSS_CTRL_PHASE_ACTIVEEDGE << MXC_F_SPIMSS_CTRL_PHASE_POS) /**< CTRL_PHASE_ACTIVEEDGE Setting */ 152 #define MXC_V_SPIMSS_CTRL_PHASE_INACTIVEEDGE ((uint32_t)0x1UL) /**< CTRL_PHASE_INACTIVEEDGE Value */ 153 #define MXC_S_SPIMSS_CTRL_PHASE_INACTIVEEDGE (MXC_V_SPIMSS_CTRL_PHASE_INACTIVEEDGE << MXC_F_SPIMSS_CTRL_PHASE_POS) /**< CTRL_PHASE_INACTIVEEDGE Setting */ 154 155 #define MXC_F_SPIMSS_CTRL_BIRQ_POS 5 /**< CTRL_BIRQ Position */ 156 #define MXC_F_SPIMSS_CTRL_BIRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_BIRQ_POS)) /**< CTRL_BIRQ Mask */ 157 #define MXC_V_SPIMSS_CTRL_BIRQ_DIS ((uint32_t)0x0UL) /**< CTRL_BIRQ_DIS Value */ 158 #define MXC_S_SPIMSS_CTRL_BIRQ_DIS (MXC_V_SPIMSS_CTRL_BIRQ_DIS << MXC_F_SPIMSS_CTRL_BIRQ_POS) /**< CTRL_BIRQ_DIS Setting */ 159 #define MXC_V_SPIMSS_CTRL_BIRQ_EN ((uint32_t)0x1UL) /**< CTRL_BIRQ_EN Value */ 160 #define MXC_S_SPIMSS_CTRL_BIRQ_EN (MXC_V_SPIMSS_CTRL_BIRQ_EN << MXC_F_SPIMSS_CTRL_BIRQ_POS) /**< CTRL_BIRQ_EN Setting */ 161 162 #define MXC_F_SPIMSS_CTRL_STR_POS 6 /**< CTRL_STR Position */ 163 #define MXC_F_SPIMSS_CTRL_STR ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_STR_POS)) /**< CTRL_STR Mask */ 164 #define MXC_V_SPIMSS_CTRL_STR_COMPLETE ((uint32_t)0x0UL) /**< CTRL_STR_COMPLETE Value */ 165 #define MXC_S_SPIMSS_CTRL_STR_COMPLETE (MXC_V_SPIMSS_CTRL_STR_COMPLETE << MXC_F_SPIMSS_CTRL_STR_POS) /**< CTRL_STR_COMPLETE Setting */ 166 #define MXC_V_SPIMSS_CTRL_STR_START ((uint32_t)0x1UL) /**< CTRL_STR_START Value */ 167 #define MXC_S_SPIMSS_CTRL_STR_START (MXC_V_SPIMSS_CTRL_STR_START << MXC_F_SPIMSS_CTRL_STR_POS) /**< CTRL_STR_START Setting */ 168 169 #define MXC_F_SPIMSS_CTRL_IRQE_POS 7 /**< CTRL_IRQE Position */ 170 #define MXC_F_SPIMSS_CTRL_IRQE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_IRQE_POS)) /**< CTRL_IRQE Mask */ 171 #define MXC_V_SPIMSS_CTRL_IRQE_DIS ((uint32_t)0x0UL) /**< CTRL_IRQE_DIS Value */ 172 #define MXC_S_SPIMSS_CTRL_IRQE_DIS (MXC_V_SPIMSS_CTRL_IRQE_DIS << MXC_F_SPIMSS_CTRL_IRQE_POS) /**< CTRL_IRQE_DIS Setting */ 173 #define MXC_V_SPIMSS_CTRL_IRQE_EN ((uint32_t)0x1UL) /**< CTRL_IRQE_EN Value */ 174 #define MXC_S_SPIMSS_CTRL_IRQE_EN (MXC_V_SPIMSS_CTRL_IRQE_EN << MXC_F_SPIMSS_CTRL_IRQE_POS) /**< CTRL_IRQE_EN Setting */ 175 176 /**@} end of group SPIMSS_CTRL_Register */ 177 178 /** 179 * @ingroup spimss_registers 180 * @defgroup SPIMSS_INT_FL SPIMSS_INT_FL 181 * @brief SPI Interrupt Flag Register. 182 * @{ 183 */ 184 #define MXC_F_SPIMSS_INT_FL_SLAS_POS 0 /**< INT_FL_SLAS Position */ 185 #define MXC_F_SPIMSS_INT_FL_SLAS ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_SLAS_POS)) /**< INT_FL_SLAS Mask */ 186 #define MXC_V_SPIMSS_INT_FL_SLAS_SELECTED ((uint32_t)0x0UL) /**< INT_FL_SLAS_SELECTED Value */ 187 #define MXC_S_SPIMSS_INT_FL_SLAS_SELECTED (MXC_V_SPIMSS_INT_FL_SLAS_SELECTED << MXC_F_SPIMSS_INT_FL_SLAS_POS) /**< INT_FL_SLAS_SELECTED Setting */ 188 #define MXC_V_SPIMSS_INT_FL_SLAS_NOTSELECTED ((uint32_t)0x1UL) /**< INT_FL_SLAS_NOTSELECTED Value */ 189 #define MXC_S_SPIMSS_INT_FL_SLAS_NOTSELECTED (MXC_V_SPIMSS_INT_FL_SLAS_NOTSELECTED << MXC_F_SPIMSS_INT_FL_SLAS_POS) /**< INT_FL_SLAS_NOTSELECTED Setting */ 190 191 #define MXC_F_SPIMSS_INT_FL_TXST_POS 1 /**< INT_FL_TXST Position */ 192 #define MXC_F_SPIMSS_INT_FL_TXST ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TXST_POS)) /**< INT_FL_TXST Mask */ 193 #define MXC_V_SPIMSS_INT_FL_TXST_IDLE ((uint32_t)0x0UL) /**< INT_FL_TXST_IDLE Value */ 194 #define MXC_S_SPIMSS_INT_FL_TXST_IDLE (MXC_V_SPIMSS_INT_FL_TXST_IDLE << MXC_F_SPIMSS_INT_FL_TXST_POS) /**< INT_FL_TXST_IDLE Setting */ 195 #define MXC_V_SPIMSS_INT_FL_TXST_BUSY ((uint32_t)0x1UL) /**< INT_FL_TXST_BUSY Value */ 196 #define MXC_S_SPIMSS_INT_FL_TXST_BUSY (MXC_V_SPIMSS_INT_FL_TXST_BUSY << MXC_F_SPIMSS_INT_FL_TXST_POS) /**< INT_FL_TXST_BUSY Setting */ 197 198 #define MXC_F_SPIMSS_INT_FL_TUND_POS 2 /**< INT_FL_TUND Position */ 199 #define MXC_F_SPIMSS_INT_FL_TUND ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TUND_POS)) /**< INT_FL_TUND Mask */ 200 #define MXC_V_SPIMSS_INT_FL_TUND_NOEVENT ((uint32_t)0x0UL) /**< INT_FL_TUND_NOEVENT Value */ 201 #define MXC_S_SPIMSS_INT_FL_TUND_NOEVENT (MXC_V_SPIMSS_INT_FL_TUND_NOEVENT << MXC_F_SPIMSS_INT_FL_TUND_POS) /**< INT_FL_TUND_NOEVENT Setting */ 202 #define MXC_V_SPIMSS_INT_FL_TUND_UNDERRUN ((uint32_t)0x1UL) /**< INT_FL_TUND_UNDERRUN Value */ 203 #define MXC_S_SPIMSS_INT_FL_TUND_UNDERRUN (MXC_V_SPIMSS_INT_FL_TUND_UNDERRUN << MXC_F_SPIMSS_INT_FL_TUND_POS) /**< INT_FL_TUND_UNDERRUN Setting */ 204 205 #define MXC_F_SPIMSS_INT_FL_ROVR_POS 3 /**< INT_FL_ROVR Position */ 206 #define MXC_F_SPIMSS_INT_FL_ROVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_ROVR_POS)) /**< INT_FL_ROVR Mask */ 207 #define MXC_V_SPIMSS_INT_FL_ROVR_NOEVENT ((uint32_t)0x0UL) /**< INT_FL_ROVR_NOEVENT Value */ 208 #define MXC_S_SPIMSS_INT_FL_ROVR_NOEVENT (MXC_V_SPIMSS_INT_FL_ROVR_NOEVENT << MXC_F_SPIMSS_INT_FL_ROVR_POS) /**< INT_FL_ROVR_NOEVENT Setting */ 209 #define MXC_V_SPIMSS_INT_FL_ROVR_OVERRUN ((uint32_t)0x1UL) /**< INT_FL_ROVR_OVERRUN Value */ 210 #define MXC_S_SPIMSS_INT_FL_ROVR_OVERRUN (MXC_V_SPIMSS_INT_FL_ROVR_OVERRUN << MXC_F_SPIMSS_INT_FL_ROVR_POS) /**< INT_FL_ROVR_OVERRUN Setting */ 211 212 #define MXC_F_SPIMSS_INT_FL_ABT_POS 4 /**< INT_FL_ABT Position */ 213 #define MXC_F_SPIMSS_INT_FL_ABT ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_ABT_POS)) /**< INT_FL_ABT Mask */ 214 #define MXC_V_SPIMSS_INT_FL_ABT_NOEVENT ((uint32_t)0x0UL) /**< INT_FL_ABT_NOEVENT Value */ 215 #define MXC_S_SPIMSS_INT_FL_ABT_NOEVENT (MXC_V_SPIMSS_INT_FL_ABT_NOEVENT << MXC_F_SPIMSS_INT_FL_ABT_POS) /**< INT_FL_ABT_NOEVENT Setting */ 216 #define MXC_V_SPIMSS_INT_FL_ABT_ABORTED ((uint32_t)0x1UL) /**< INT_FL_ABT_ABORTED Value */ 217 #define MXC_S_SPIMSS_INT_FL_ABT_ABORTED (MXC_V_SPIMSS_INT_FL_ABT_ABORTED << MXC_F_SPIMSS_INT_FL_ABT_POS) /**< INT_FL_ABT_ABORTED Setting */ 218 219 #define MXC_F_SPIMSS_INT_FL_COL_POS 5 /**< INT_FL_COL Position */ 220 #define MXC_F_SPIMSS_INT_FL_COL ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_COL_POS)) /**< INT_FL_COL Mask */ 221 #define MXC_V_SPIMSS_INT_FL_COL_NOEVENT ((uint32_t)0x0UL) /**< INT_FL_COL_NOEVENT Value */ 222 #define MXC_S_SPIMSS_INT_FL_COL_NOEVENT (MXC_V_SPIMSS_INT_FL_COL_NOEVENT << MXC_F_SPIMSS_INT_FL_COL_POS) /**< INT_FL_COL_NOEVENT Setting */ 223 #define MXC_V_SPIMSS_INT_FL_COL_COLLISION ((uint32_t)0x1UL) /**< INT_FL_COL_COLLISION Value */ 224 #define MXC_S_SPIMSS_INT_FL_COL_COLLISION (MXC_V_SPIMSS_INT_FL_COL_COLLISION << MXC_F_SPIMSS_INT_FL_COL_POS) /**< INT_FL_COL_COLLISION Setting */ 225 226 #define MXC_F_SPIMSS_INT_FL_TOVR_POS 6 /**< INT_FL_TOVR Position */ 227 #define MXC_F_SPIMSS_INT_FL_TOVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TOVR_POS)) /**< INT_FL_TOVR Mask */ 228 #define MXC_V_SPIMSS_INT_FL_TOVR_NOEVENT ((uint32_t)0x0UL) /**< INT_FL_TOVR_NOEVENT Value */ 229 #define MXC_S_SPIMSS_INT_FL_TOVR_NOEVENT (MXC_V_SPIMSS_INT_FL_TOVR_NOEVENT << MXC_F_SPIMSS_INT_FL_TOVR_POS) /**< INT_FL_TOVR_NOEVENT Setting */ 230 #define MXC_V_SPIMSS_INT_FL_TOVR_OVERRUN ((uint32_t)0x1UL) /**< INT_FL_TOVR_OVERRUN Value */ 231 #define MXC_S_SPIMSS_INT_FL_TOVR_OVERRUN (MXC_V_SPIMSS_INT_FL_TOVR_OVERRUN << MXC_F_SPIMSS_INT_FL_TOVR_POS) /**< INT_FL_TOVR_OVERRUN Setting */ 232 233 #define MXC_F_SPIMSS_INT_FL_IRQ_POS 7 /**< INT_FL_IRQ Position */ 234 #define MXC_F_SPIMSS_INT_FL_IRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_IRQ_POS)) /**< INT_FL_IRQ Mask */ 235 #define MXC_V_SPIMSS_INT_FL_IRQ_INACTIVE ((uint32_t)0x0UL) /**< INT_FL_IRQ_INACTIVE Value */ 236 #define MXC_S_SPIMSS_INT_FL_IRQ_INACTIVE (MXC_V_SPIMSS_INT_FL_IRQ_INACTIVE << MXC_F_SPIMSS_INT_FL_IRQ_POS) /**< INT_FL_IRQ_INACTIVE Setting */ 237 #define MXC_V_SPIMSS_INT_FL_IRQ_PENDING ((uint32_t)0x1UL) /**< INT_FL_IRQ_PENDING Value */ 238 #define MXC_S_SPIMSS_INT_FL_IRQ_PENDING (MXC_V_SPIMSS_INT_FL_IRQ_PENDING << MXC_F_SPIMSS_INT_FL_IRQ_POS) /**< INT_FL_IRQ_PENDING Setting */ 239 240 /**@} end of group SPIMSS_INT_FL_Register */ 241 242 /** 243 * @ingroup spimss_registers 244 * @defgroup SPIMSS_MOD SPIMSS_MOD 245 * @brief SPI Mode Register. 246 * @{ 247 */ 248 #define MXC_F_SPIMSS_MOD_SSV_POS 0 /**< MOD_SSV Position */ 249 #define MXC_F_SPIMSS_MOD_SSV ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSV_POS)) /**< MOD_SSV Mask */ 250 #define MXC_V_SPIMSS_MOD_SSV_LO ((uint32_t)0x0UL) /**< MOD_SSV_LO Value */ 251 #define MXC_S_SPIMSS_MOD_SSV_LO (MXC_V_SPIMSS_MOD_SSV_LO << MXC_F_SPIMSS_MOD_SSV_POS) /**< MOD_SSV_LO Setting */ 252 #define MXC_V_SPIMSS_MOD_SSV_HI ((uint32_t)0x1UL) /**< MOD_SSV_HI Value */ 253 #define MXC_S_SPIMSS_MOD_SSV_HI (MXC_V_SPIMSS_MOD_SSV_HI << MXC_F_SPIMSS_MOD_SSV_POS) /**< MOD_SSV_HI Setting */ 254 255 #define MXC_F_SPIMSS_MOD_SSEL_POS 1 /**< MOD_SSEL Position */ 256 #define MXC_F_SPIMSS_MOD_SSEL ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSEL_POS)) /**< MOD_SSEL Mask */ 257 #define MXC_V_SPIMSS_MOD_SSEL_INPUT ((uint32_t)0x0UL) /**< MOD_SSEL_INPUT Value */ 258 #define MXC_S_SPIMSS_MOD_SSEL_INPUT (MXC_V_SPIMSS_MOD_SSEL_INPUT << MXC_F_SPIMSS_MOD_SSEL_POS) /**< MOD_SSEL_INPUT Setting */ 259 #define MXC_V_SPIMSS_MOD_SSEL_OUTPUT ((uint32_t)0x1UL) /**< MOD_SSEL_OUTPUT Value */ 260 #define MXC_S_SPIMSS_MOD_SSEL_OUTPUT (MXC_V_SPIMSS_MOD_SSEL_OUTPUT << MXC_F_SPIMSS_MOD_SSEL_POS) /**< MOD_SSEL_OUTPUT Setting */ 261 262 #define MXC_F_SPIMSS_MOD_NUMBITS_POS 2 /**< MOD_NUMBITS Position */ 263 #define MXC_F_SPIMSS_MOD_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPIMSS_MOD_NUMBITS_POS)) /**< MOD_NUMBITS Mask */ 264 #define MXC_V_SPIMSS_MOD_NUMBITS_16BITS ((uint32_t)0x0UL) /**< MOD_NUMBITS_16BITS Value */ 265 #define MXC_S_SPIMSS_MOD_NUMBITS_16BITS (MXC_V_SPIMSS_MOD_NUMBITS_16BITS << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_16BITS Setting */ 266 #define MXC_V_SPIMSS_MOD_NUMBITS_1BITS ((uint32_t)0x1UL) /**< MOD_NUMBITS_1BITS Value */ 267 #define MXC_S_SPIMSS_MOD_NUMBITS_1BITS (MXC_V_SPIMSS_MOD_NUMBITS_1BITS << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_1BITS Setting */ 268 #define MXC_V_SPIMSS_MOD_NUMBITS_2BITS ((uint32_t)0x2UL) /**< MOD_NUMBITS_2BITS Value */ 269 #define MXC_S_SPIMSS_MOD_NUMBITS_2BITS (MXC_V_SPIMSS_MOD_NUMBITS_2BITS << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_2BITS Setting */ 270 #define MXC_V_SPIMSS_MOD_NUMBITS_3BITS ((uint32_t)0x3UL) /**< MOD_NUMBITS_3BITS Value */ 271 #define MXC_S_SPIMSS_MOD_NUMBITS_3BITS (MXC_V_SPIMSS_MOD_NUMBITS_3BITS << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_3BITS Setting */ 272 #define MXC_V_SPIMSS_MOD_NUMBITS_4BITS ((uint32_t)0x4UL) /**< MOD_NUMBITS_4BITS Value */ 273 #define MXC_S_SPIMSS_MOD_NUMBITS_4BITS (MXC_V_SPIMSS_MOD_NUMBITS_4BITS << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_4BITS Setting */ 274 #define MXC_V_SPIMSS_MOD_NUMBITS_5BITS ((uint32_t)0x5UL) /**< MOD_NUMBITS_5BITS Value */ 275 #define MXC_S_SPIMSS_MOD_NUMBITS_5BITS (MXC_V_SPIMSS_MOD_NUMBITS_5BITS << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_5BITS Setting */ 276 #define MXC_V_SPIMSS_MOD_NUMBITS_6BITS ((uint32_t)0x6UL) /**< MOD_NUMBITS_6BITS Value */ 277 #define MXC_S_SPIMSS_MOD_NUMBITS_6BITS (MXC_V_SPIMSS_MOD_NUMBITS_6BITS << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_6BITS Setting */ 278 #define MXC_V_SPIMSS_MOD_NUMBITS_7BITS ((uint32_t)0x7UL) /**< MOD_NUMBITS_7BITS Value */ 279 #define MXC_S_SPIMSS_MOD_NUMBITS_7BITS (MXC_V_SPIMSS_MOD_NUMBITS_7BITS << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_7BITS Setting */ 280 #define MXC_V_SPIMSS_MOD_NUMBITS_8BITS ((uint32_t)0x8UL) /**< MOD_NUMBITS_8BITS Value */ 281 #define MXC_S_SPIMSS_MOD_NUMBITS_8BITS (MXC_V_SPIMSS_MOD_NUMBITS_8BITS << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_8BITS Setting */ 282 #define MXC_V_SPIMSS_MOD_NUMBITS_9BITS ((uint32_t)0x9UL) /**< MOD_NUMBITS_9BITS Value */ 283 #define MXC_S_SPIMSS_MOD_NUMBITS_9BITS (MXC_V_SPIMSS_MOD_NUMBITS_9BITS << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_9BITS Setting */ 284 #define MXC_V_SPIMSS_MOD_NUMBITS_10BITS ((uint32_t)0xAUL) /**< MOD_NUMBITS_10BITS Value */ 285 #define MXC_S_SPIMSS_MOD_NUMBITS_10BITS (MXC_V_SPIMSS_MOD_NUMBITS_10BITS << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_10BITS Setting */ 286 #define MXC_V_SPIMSS_MOD_NUMBITS_11BITS ((uint32_t)0xBUL) /**< MOD_NUMBITS_11BITS Value */ 287 #define MXC_S_SPIMSS_MOD_NUMBITS_11BITS (MXC_V_SPIMSS_MOD_NUMBITS_11BITS << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_11BITS Setting */ 288 #define MXC_V_SPIMSS_MOD_NUMBITS_12BITS ((uint32_t)0xCUL) /**< MOD_NUMBITS_12BITS Value */ 289 #define MXC_S_SPIMSS_MOD_NUMBITS_12BITS (MXC_V_SPIMSS_MOD_NUMBITS_12BITS << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_12BITS Setting */ 290 #define MXC_V_SPIMSS_MOD_NUMBITS_13BITS ((uint32_t)0xDUL) /**< MOD_NUMBITS_13BITS Value */ 291 #define MXC_S_SPIMSS_MOD_NUMBITS_13BITS (MXC_V_SPIMSS_MOD_NUMBITS_13BITS << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_13BITS Setting */ 292 #define MXC_V_SPIMSS_MOD_NUMBITS_14BITS ((uint32_t)0xEUL) /**< MOD_NUMBITS_14BITS Value */ 293 #define MXC_S_SPIMSS_MOD_NUMBITS_14BITS (MXC_V_SPIMSS_MOD_NUMBITS_14BITS << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_14BITS Setting */ 294 #define MXC_V_SPIMSS_MOD_NUMBITS_15BITS ((uint32_t)0xFUL) /**< MOD_NUMBITS_15BITS Value */ 295 #define MXC_S_SPIMSS_MOD_NUMBITS_15BITS (MXC_V_SPIMSS_MOD_NUMBITS_15BITS << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_15BITS Setting */ 296 297 #define MXC_F_SPIMSS_MOD_TX_ALIGN_POS 7 /**< MOD_TX_ALIGN Position */ 298 #define MXC_F_SPIMSS_MOD_TX_ALIGN ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_TX_ALIGN_POS)) /**< MOD_TX_ALIGN Mask */ 299 #define MXC_V_SPIMSS_MOD_TX_ALIGN_LSB ((uint32_t)0x0UL) /**< MOD_TX_ALIGN_LSB Value */ 300 #define MXC_S_SPIMSS_MOD_TX_ALIGN_LSB (MXC_V_SPIMSS_MOD_TX_ALIGN_LSB << MXC_F_SPIMSS_MOD_TX_ALIGN_POS) /**< MOD_TX_ALIGN_LSB Setting */ 301 #define MXC_V_SPIMSS_MOD_TX_ALIGN_MSB ((uint32_t)0x1UL) /**< MOD_TX_ALIGN_MSB Value */ 302 #define MXC_S_SPIMSS_MOD_TX_ALIGN_MSB (MXC_V_SPIMSS_MOD_TX_ALIGN_MSB << MXC_F_SPIMSS_MOD_TX_ALIGN_POS) /**< MOD_TX_ALIGN_MSB Setting */ 303 304 /**@} end of group SPIMSS_MOD_Register */ 305 306 /** 307 * @ingroup spimss_registers 308 * @defgroup SPIMSS_BRG SPIMSS_BRG 309 * @brief Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for 310 * the SPI Baud Rate Generator. The reload value must be greater than or equal to 311 * 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by 312 * 4). 313 * @{ 314 */ 315 #define MXC_F_SPIMSS_BRG_DIV_POS 0 /**< BRG_DIV Position */ 316 #define MXC_F_SPIMSS_BRG_DIV ((uint32_t)(0xFFFFUL << MXC_F_SPIMSS_BRG_DIV_POS)) /**< BRG_DIV Mask */ 317 318 /**@} end of group SPIMSS_BRG_Register */ 319 320 /** 321 * @ingroup spimss_registers 322 * @defgroup SPIMSS_DMA SPIMSS_DMA 323 * @brief SPI DMA Register. 324 * @{ 325 */ 326 #define MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS 0 /**< DMA_TX_FIFO_LVL Position */ 327 #define MXC_F_SPIMSS_DMA_TX_FIFO_LVL ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)) /**< DMA_TX_FIFO_LVL Mask */ 328 #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_1ENTRIES ((uint32_t)0x0UL) /**< DMA_TX_FIFO_LVL_1ENTRIES Value */ 329 #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_1ENTRIES (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_1ENTRIES << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_1ENTRIES Setting */ 330 #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_2ENTRIES ((uint32_t)0x1UL) /**< DMA_TX_FIFO_LVL_2ENTRIES Value */ 331 #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_2ENTRIES (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_2ENTRIES << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_2ENTRIES Setting */ 332 #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_3ENTRIES ((uint32_t)0x2UL) /**< DMA_TX_FIFO_LVL_3ENTRIES Value */ 333 #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_3ENTRIES (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_3ENTRIES << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_3ENTRIES Setting */ 334 #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_4ENTRIES ((uint32_t)0x3UL) /**< DMA_TX_FIFO_LVL_4ENTRIES Value */ 335 #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_4ENTRIES (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_4ENTRIES << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_4ENTRIES Setting */ 336 #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_5ENTRIES ((uint32_t)0x4UL) /**< DMA_TX_FIFO_LVL_5ENTRIES Value */ 337 #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_5ENTRIES (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_5ENTRIES << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_5ENTRIES Setting */ 338 #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_6ENTRIES ((uint32_t)0x5UL) /**< DMA_TX_FIFO_LVL_6ENTRIES Value */ 339 #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_6ENTRIES (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_6ENTRIES << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_6ENTRIES Setting */ 340 #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_7ENTRIES ((uint32_t)0x6UL) /**< DMA_TX_FIFO_LVL_7ENTRIES Value */ 341 #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_7ENTRIES (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_7ENTRIES << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_7ENTRIES Setting */ 342 #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_8ENTRIES ((uint32_t)0x7UL) /**< DMA_TX_FIFO_LVL_8ENTRIES Value */ 343 #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_8ENTRIES (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_8ENTRIES << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_8ENTRIES Setting */ 344 345 #define MXC_F_SPIMSS_DMA_TX_FIFO_CLR_POS 4 /**< DMA_TX_FIFO_CLR Position */ 346 #define MXC_F_SPIMSS_DMA_TX_FIFO_CLR ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_FIFO_CLR_POS)) /**< DMA_TX_FIFO_CLR Mask */ 347 #define MXC_V_SPIMSS_DMA_TX_FIFO_CLR_CLEAR ((uint32_t)0x1UL) /**< DMA_TX_FIFO_CLR_CLEAR Value */ 348 #define MXC_S_SPIMSS_DMA_TX_FIFO_CLR_CLEAR (MXC_V_SPIMSS_DMA_TX_FIFO_CLR_CLEAR << MXC_F_SPIMSS_DMA_TX_FIFO_CLR_POS) /**< DMA_TX_FIFO_CLR_CLEAR Setting */ 349 350 #define MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */ 351 #define MXC_F_SPIMSS_DMA_TX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */ 352 353 #define MXC_F_SPIMSS_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */ 354 #define MXC_F_SPIMSS_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */ 355 #define MXC_V_SPIMSS_DMA_TX_DMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_DMA_EN_DIS Value */ 356 #define MXC_S_SPIMSS_DMA_TX_DMA_EN_DIS (MXC_V_SPIMSS_DMA_TX_DMA_EN_DIS << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_DIS Setting */ 357 #define MXC_V_SPIMSS_DMA_TX_DMA_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_DMA_EN_EN Value */ 358 #define MXC_S_SPIMSS_DMA_TX_DMA_EN_EN (MXC_V_SPIMSS_DMA_TX_DMA_EN_EN << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_EN Setting */ 359 360 #define MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS 16 /**< DMA_RX_FIFO_LVL Position */ 361 #define MXC_F_SPIMSS_DMA_RX_FIFO_LVL ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)) /**< DMA_RX_FIFO_LVL Mask */ 362 #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_1ENTRIES ((uint32_t)0x0UL) /**< DMA_RX_FIFO_LVL_1ENTRIES Value */ 363 #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_1ENTRIES (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_1ENTRIES << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_1ENTRIES Setting */ 364 #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_2ENTRIES ((uint32_t)0x1UL) /**< DMA_RX_FIFO_LVL_2ENTRIES Value */ 365 #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_2ENTRIES (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_2ENTRIES << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_2ENTRIES Setting */ 366 #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_3ENTRIES ((uint32_t)0x2UL) /**< DMA_RX_FIFO_LVL_3ENTRIES Value */ 367 #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_3ENTRIES (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_3ENTRIES << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_3ENTRIES Setting */ 368 #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_4ENTRIES ((uint32_t)0x3UL) /**< DMA_RX_FIFO_LVL_4ENTRIES Value */ 369 #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_4ENTRIES (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_4ENTRIES << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_4ENTRIES Setting */ 370 #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_5ENTRIES ((uint32_t)0x4UL) /**< DMA_RX_FIFO_LVL_5ENTRIES Value */ 371 #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_5ENTRIES (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_5ENTRIES << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_5ENTRIES Setting */ 372 #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_6ENTRIES ((uint32_t)0x5UL) /**< DMA_RX_FIFO_LVL_6ENTRIES Value */ 373 #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_6ENTRIES (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_6ENTRIES << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_6ENTRIES Setting */ 374 #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_7ENTRIES ((uint32_t)0x6UL) /**< DMA_RX_FIFO_LVL_7ENTRIES Value */ 375 #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_7ENTRIES (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_7ENTRIES << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_7ENTRIES Setting */ 376 #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_8ENTRIES ((uint32_t)0x7UL) /**< DMA_RX_FIFO_LVL_8ENTRIES Value */ 377 #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_8ENTRIES (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_8ENTRIES << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_8ENTRIES Setting */ 378 379 #define MXC_F_SPIMSS_DMA_RX_FIFO_CLR_POS 20 /**< DMA_RX_FIFO_CLR Position */ 380 #define MXC_F_SPIMSS_DMA_RX_FIFO_CLR ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_FIFO_CLR_POS)) /**< DMA_RX_FIFO_CLR Mask */ 381 #define MXC_V_SPIMSS_DMA_RX_FIFO_CLR_CLEAR ((uint32_t)0x1UL) /**< DMA_RX_FIFO_CLR_CLEAR Value */ 382 #define MXC_S_SPIMSS_DMA_RX_FIFO_CLR_CLEAR (MXC_V_SPIMSS_DMA_RX_FIFO_CLR_CLEAR << MXC_F_SPIMSS_DMA_RX_FIFO_CLR_POS) /**< DMA_RX_FIFO_CLR_CLEAR Setting */ 383 384 #define MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */ 385 #define MXC_F_SPIMSS_DMA_RX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */ 386 387 #define MXC_F_SPIMSS_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */ 388 #define MXC_F_SPIMSS_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */ 389 #define MXC_V_SPIMSS_DMA_RX_DMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_DMA_EN_DIS Value */ 390 #define MXC_S_SPIMSS_DMA_RX_DMA_EN_DIS (MXC_V_SPIMSS_DMA_RX_DMA_EN_DIS << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_DIS Setting */ 391 #define MXC_V_SPIMSS_DMA_RX_DMA_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_DMA_EN_EN Value */ 392 #define MXC_S_SPIMSS_DMA_RX_DMA_EN_EN (MXC_V_SPIMSS_DMA_RX_DMA_EN_EN << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_EN Setting */ 393 394 /**@} end of group SPIMSS_DMA_Register */ 395 396 /** 397 * @ingroup spimss_registers 398 * @defgroup SPIMSS_I2S_CTRL SPIMSS_I2S_CTRL 399 * @brief I2S Control Register. 400 * @{ 401 */ 402 #define MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS 0 /**< I2S_CTRL_I2S_EN Position */ 403 #define MXC_F_SPIMSS_I2S_CTRL_I2S_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS)) /**< I2S_CTRL_I2S_EN Mask */ 404 #define MXC_V_SPIMSS_I2S_CTRL_I2S_EN_DIS ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_EN_DIS Value */ 405 #define MXC_S_SPIMSS_I2S_CTRL_I2S_EN_DIS (MXC_V_SPIMSS_I2S_CTRL_I2S_EN_DIS << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS) /**< I2S_CTRL_I2S_EN_DIS Setting */ 406 #define MXC_V_SPIMSS_I2S_CTRL_I2S_EN_EN ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_EN_EN Value */ 407 #define MXC_S_SPIMSS_I2S_CTRL_I2S_EN_EN (MXC_V_SPIMSS_I2S_CTRL_I2S_EN_EN << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS) /**< I2S_CTRL_I2S_EN_EN Setting */ 408 409 #define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS 1 /**< I2S_CTRL_I2S_MUTE Position */ 410 #define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS)) /**< I2S_CTRL_I2S_MUTE Mask */ 411 #define MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_MUTE_NORMAL Value */ 412 #define MXC_S_SPIMSS_I2S_CTRL_I2S_MUTE_NORMAL (MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_NORMAL << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS) /**< I2S_CTRL_I2S_MUTE_NORMAL Setting */ 413 #define MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_MUTED ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_MUTE_MUTED Value */ 414 #define MXC_S_SPIMSS_I2S_CTRL_I2S_MUTE_MUTED (MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_MUTED << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS) /**< I2S_CTRL_I2S_MUTE_MUTED Setting */ 415 416 #define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS 2 /**< I2S_CTRL_I2S_PAUSE Position */ 417 #define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS)) /**< I2S_CTRL_I2S_PAUSE Mask */ 418 #define MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_PAUSE_NORMAL Value */ 419 #define MXC_S_SPIMSS_I2S_CTRL_I2S_PAUSE_NORMAL (MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_NORMAL << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS) /**< I2S_CTRL_I2S_PAUSE_NORMAL Setting */ 420 #define MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_PAUSE ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_PAUSE_PAUSE Value */ 421 #define MXC_S_SPIMSS_I2S_CTRL_I2S_PAUSE_PAUSE (MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_PAUSE << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS) /**< I2S_CTRL_I2S_PAUSE_PAUSE Setting */ 422 423 #define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS 3 /**< I2S_CTRL_I2S_MONO Position */ 424 #define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS)) /**< I2S_CTRL_I2S_MONO Mask */ 425 #define MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_STEREO ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_MONO_STEREO Value */ 426 #define MXC_S_SPIMSS_I2S_CTRL_I2S_MONO_STEREO (MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_STEREO << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS) /**< I2S_CTRL_I2S_MONO_STEREO Setting */ 427 #define MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_MONO ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_MONO_MONO Value */ 428 #define MXC_S_SPIMSS_I2S_CTRL_I2S_MONO_MONO (MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_MONO << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS) /**< I2S_CTRL_I2S_MONO_MONO Setting */ 429 430 #define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS 4 /**< I2S_CTRL_I2S_LJ Position */ 431 #define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS)) /**< I2S_CTRL_I2S_LJ Mask */ 432 #define MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_LAG ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_LJ_LAG Value */ 433 #define MXC_S_SPIMSS_I2S_CTRL_I2S_LJ_LAG (MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_LAG << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS) /**< I2S_CTRL_I2S_LJ_LAG Setting */ 434 #define MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_SYNCRONIZED ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_LJ_SYNCRONIZED Value */ 435 #define MXC_S_SPIMSS_I2S_CTRL_I2S_LJ_SYNCRONIZED (MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_SYNCRONIZED << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS) /**< I2S_CTRL_I2S_LJ_SYNCRONIZED Setting */ 436 437 /**@} end of group SPIMSS_I2S_CTRL_Register */ 438 439 #ifdef __cplusplus 440 } 441 #endif 442 443 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SPIMSS_REGS_H_ 444
