1 /** 2 * @file sir_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup sir_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SIR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SIR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup sir 67 * @defgroup sir_registers SIR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. 69 * @details System Initialization Registers. 70 */ 71 72 /** 73 * @ingroup sir_registers 74 * Structure type to access the SIR Registers. 75 */ 76 typedef struct { 77 __I uint32_t sistat; /**< <tt>\b 0x000:</tt> SIR SISTAT Register */ 78 __I uint32_t erraddr; /**< <tt>\b 0x004:</tt> SIR ERRADDR Register */ 79 __R uint32_t rsv_0x8_0xff[62]; 80 __I uint32_t fstat; /**< <tt>\b 0x100:</tt> SIR FSTAT Register */ 81 __I uint32_t sfstat; /**< <tt>\b 0x104:</tt> SIR SFSTAT Register */ 82 } mxc_sir_regs_t; 83 84 /* Register offsets for module SIR */ 85 /** 86 * @ingroup sir_registers 87 * @defgroup SIR_Register_Offsets Register Offsets 88 * @brief SIR Peripheral Register Offsets from the SIR Base Peripheral Address. 89 * @{ 90 */ 91 #define MXC_R_SIR_SISTAT ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: <tt> 0x0000</tt> */ 92 #define MXC_R_SIR_ERRADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: <tt> 0x0004</tt> */ 93 #define MXC_R_SIR_FSTAT ((uint32_t)0x00000100UL) /**< Offset from SIR Base Address: <tt> 0x0100</tt> */ 94 #define MXC_R_SIR_SFSTAT ((uint32_t)0x00000104UL) /**< Offset from SIR Base Address: <tt> 0x0104</tt> */ 95 /**@} end of group sir_registers */ 96 97 /** 98 * @ingroup sir_registers 99 * @defgroup SIR_SISTAT SIR_SISTAT 100 * @brief System Initialization Status Register. 101 * @{ 102 */ 103 #define MXC_F_SIR_SISTAT_MAGIC_POS 0 /**< SISTAT_MAGIC Position */ 104 #define MXC_F_SIR_SISTAT_MAGIC ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_MAGIC_POS)) /**< SISTAT_MAGIC Mask */ 105 #define MXC_V_SIR_SISTAT_MAGIC_MAGICNOTSET ((uint32_t)0x0UL) /**< SISTAT_MAGIC_MAGICNOTSET Value */ 106 #define MXC_S_SIR_SISTAT_MAGIC_MAGICNOTSET (MXC_V_SIR_SISTAT_MAGIC_MAGICNOTSET << MXC_F_SIR_SISTAT_MAGIC_POS) /**< SISTAT_MAGIC_MAGICNOTSET Setting */ 107 #define MXC_V_SIR_SISTAT_MAGIC_MAGICSET ((uint32_t)0x1UL) /**< SISTAT_MAGIC_MAGICSET Value */ 108 #define MXC_S_SIR_SISTAT_MAGIC_MAGICSET (MXC_V_SIR_SISTAT_MAGIC_MAGICSET << MXC_F_SIR_SISTAT_MAGIC_POS) /**< SISTAT_MAGIC_MAGICSET Setting */ 109 110 #define MXC_F_SIR_SISTAT_CRCERR_POS 1 /**< SISTAT_CRCERR Position */ 111 #define MXC_F_SIR_SISTAT_CRCERR ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_CRCERR_POS)) /**< SISTAT_CRCERR Mask */ 112 #define MXC_V_SIR_SISTAT_CRCERR_NOERROR ((uint32_t)0x0UL) /**< SISTAT_CRCERR_NOERROR Value */ 113 #define MXC_S_SIR_SISTAT_CRCERR_NOERROR (MXC_V_SIR_SISTAT_CRCERR_NOERROR << MXC_F_SIR_SISTAT_CRCERR_POS) /**< SISTAT_CRCERR_NOERROR Setting */ 114 #define MXC_V_SIR_SISTAT_CRCERR_ERROR ((uint32_t)0x1UL) /**< SISTAT_CRCERR_ERROR Value */ 115 #define MXC_S_SIR_SISTAT_CRCERR_ERROR (MXC_V_SIR_SISTAT_CRCERR_ERROR << MXC_F_SIR_SISTAT_CRCERR_POS) /**< SISTAT_CRCERR_ERROR Setting */ 116 117 /**@} end of group SIR_SISTAT_Register */ 118 119 /** 120 * @ingroup sir_registers 121 * @defgroup SIR_ERRADDR SIR_ERRADDR 122 * @brief Read-only field set by the SIB block if a CRC error occurs during the read of 123 * the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 124 * 1). 125 * @{ 126 */ 127 #define MXC_F_SIR_ERRADDR_ERRADDR_POS 0 /**< ERRADDR_ERRADDR Position */ 128 #define MXC_F_SIR_ERRADDR_ERRADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_ERRADDR_ERRADDR_POS)) /**< ERRADDR_ERRADDR Mask */ 129 130 /**@} end of group SIR_ERRADDR_Register */ 131 132 /** 133 * @ingroup sir_registers 134 * @defgroup SIR_FSTAT SIR_FSTAT 135 * @brief funcstat register. 136 * @{ 137 */ 138 #define MXC_F_SIR_FSTAT_FPU_POS 0 /**< FSTAT_FPU Position */ 139 #define MXC_F_SIR_FSTAT_FPU ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_FPU_POS)) /**< FSTAT_FPU Mask */ 140 #define MXC_V_SIR_FSTAT_FPU_NO ((uint32_t)0x0UL) /**< FSTAT_FPU_NO Value */ 141 #define MXC_S_SIR_FSTAT_FPU_NO (MXC_V_SIR_FSTAT_FPU_NO << MXC_F_SIR_FSTAT_FPU_POS) /**< FSTAT_FPU_NO Setting */ 142 #define MXC_V_SIR_FSTAT_FPU_YES ((uint32_t)0x1UL) /**< FSTAT_FPU_YES Value */ 143 #define MXC_S_SIR_FSTAT_FPU_YES (MXC_V_SIR_FSTAT_FPU_YES << MXC_F_SIR_FSTAT_FPU_POS) /**< FSTAT_FPU_YES Setting */ 144 145 #define MXC_F_SIR_FSTAT_USB_POS 1 /**< FSTAT_USB Position */ 146 #define MXC_F_SIR_FSTAT_USB ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_USB_POS)) /**< FSTAT_USB Mask */ 147 #define MXC_V_SIR_FSTAT_USB_NO ((uint32_t)0x0UL) /**< FSTAT_USB_NO Value */ 148 #define MXC_S_SIR_FSTAT_USB_NO (MXC_V_SIR_FSTAT_USB_NO << MXC_F_SIR_FSTAT_USB_POS) /**< FSTAT_USB_NO Setting */ 149 #define MXC_V_SIR_FSTAT_USB_YES ((uint32_t)0x1UL) /**< FSTAT_USB_YES Value */ 150 #define MXC_S_SIR_FSTAT_USB_YES (MXC_V_SIR_FSTAT_USB_YES << MXC_F_SIR_FSTAT_USB_POS) /**< FSTAT_USB_YES Setting */ 151 152 #define MXC_F_SIR_FSTAT_ADC_POS 2 /**< FSTAT_ADC Position */ 153 #define MXC_F_SIR_FSTAT_ADC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_ADC_POS)) /**< FSTAT_ADC Mask */ 154 #define MXC_V_SIR_FSTAT_ADC_NO ((uint32_t)0x0UL) /**< FSTAT_ADC_NO Value */ 155 #define MXC_S_SIR_FSTAT_ADC_NO (MXC_V_SIR_FSTAT_ADC_NO << MXC_F_SIR_FSTAT_ADC_POS) /**< FSTAT_ADC_NO Setting */ 156 #define MXC_V_SIR_FSTAT_ADC_YES ((uint32_t)0x1UL) /**< FSTAT_ADC_YES Value */ 157 #define MXC_S_SIR_FSTAT_ADC_YES (MXC_V_SIR_FSTAT_ADC_YES << MXC_F_SIR_FSTAT_ADC_POS) /**< FSTAT_ADC_YES Setting */ 158 159 #define MXC_F_SIR_FSTAT_XIP_POS 3 /**< FSTAT_XIP Position */ 160 #define MXC_F_SIR_FSTAT_XIP ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_XIP_POS)) /**< FSTAT_XIP Mask */ 161 #define MXC_V_SIR_FSTAT_XIP_NO ((uint32_t)0x0UL) /**< FSTAT_XIP_NO Value */ 162 #define MXC_S_SIR_FSTAT_XIP_NO (MXC_V_SIR_FSTAT_XIP_NO << MXC_F_SIR_FSTAT_XIP_POS) /**< FSTAT_XIP_NO Setting */ 163 #define MXC_V_SIR_FSTAT_XIP_YES ((uint32_t)0x1UL) /**< FSTAT_XIP_YES Value */ 164 #define MXC_S_SIR_FSTAT_XIP_YES (MXC_V_SIR_FSTAT_XIP_YES << MXC_F_SIR_FSTAT_XIP_POS) /**< FSTAT_XIP_YES Setting */ 165 166 #define MXC_F_SIR_FSTAT_PBM_POS 4 /**< FSTAT_PBM Position */ 167 #define MXC_F_SIR_FSTAT_PBM ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_PBM_POS)) /**< FSTAT_PBM Mask */ 168 #define MXC_V_SIR_FSTAT_PBM_NO ((uint32_t)0x0UL) /**< FSTAT_PBM_NO Value */ 169 #define MXC_S_SIR_FSTAT_PBM_NO (MXC_V_SIR_FSTAT_PBM_NO << MXC_F_SIR_FSTAT_PBM_POS) /**< FSTAT_PBM_NO Setting */ 170 #define MXC_V_SIR_FSTAT_PBM_YES ((uint32_t)0x1UL) /**< FSTAT_PBM_YES Value */ 171 #define MXC_S_SIR_FSTAT_PBM_YES (MXC_V_SIR_FSTAT_PBM_YES << MXC_F_SIR_FSTAT_PBM_POS) /**< FSTAT_PBM_YES Setting */ 172 173 #define MXC_F_SIR_FSTAT_HBC_POS 5 /**< FSTAT_HBC Position */ 174 #define MXC_F_SIR_FSTAT_HBC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_HBC_POS)) /**< FSTAT_HBC Mask */ 175 #define MXC_V_SIR_FSTAT_HBC_NO ((uint32_t)0x0UL) /**< FSTAT_HBC_NO Value */ 176 #define MXC_S_SIR_FSTAT_HBC_NO (MXC_V_SIR_FSTAT_HBC_NO << MXC_F_SIR_FSTAT_HBC_POS) /**< FSTAT_HBC_NO Setting */ 177 #define MXC_V_SIR_FSTAT_HBC_YES ((uint32_t)0x1UL) /**< FSTAT_HBC_YES Value */ 178 #define MXC_S_SIR_FSTAT_HBC_YES (MXC_V_SIR_FSTAT_HBC_YES << MXC_F_SIR_FSTAT_HBC_POS) /**< FSTAT_HBC_YES Setting */ 179 180 #define MXC_F_SIR_FSTAT_SDHC_POS 6 /**< FSTAT_SDHC Position */ 181 #define MXC_F_SIR_FSTAT_SDHC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SDHC_POS)) /**< FSTAT_SDHC Mask */ 182 #define MXC_V_SIR_FSTAT_SDHC_NO ((uint32_t)0x0UL) /**< FSTAT_SDHC_NO Value */ 183 #define MXC_S_SIR_FSTAT_SDHC_NO (MXC_V_SIR_FSTAT_SDHC_NO << MXC_F_SIR_FSTAT_SDHC_POS) /**< FSTAT_SDHC_NO Setting */ 184 #define MXC_V_SIR_FSTAT_SDHC_YES ((uint32_t)0x1UL) /**< FSTAT_SDHC_YES Value */ 185 #define MXC_S_SIR_FSTAT_SDHC_YES (MXC_V_SIR_FSTAT_SDHC_YES << MXC_F_SIR_FSTAT_SDHC_POS) /**< FSTAT_SDHC_YES Setting */ 186 187 #define MXC_F_SIR_FSTAT_SMPHR_POS 7 /**< FSTAT_SMPHR Position */ 188 #define MXC_F_SIR_FSTAT_SMPHR ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SMPHR_POS)) /**< FSTAT_SMPHR Mask */ 189 #define MXC_V_SIR_FSTAT_SMPHR_NO ((uint32_t)0x0UL) /**< FSTAT_SMPHR_NO Value */ 190 #define MXC_S_SIR_FSTAT_SMPHR_NO (MXC_V_SIR_FSTAT_SMPHR_NO << MXC_F_SIR_FSTAT_SMPHR_POS) /**< FSTAT_SMPHR_NO Setting */ 191 #define MXC_V_SIR_FSTAT_SMPHR_YES ((uint32_t)0x1UL) /**< FSTAT_SMPHR_YES Value */ 192 #define MXC_S_SIR_FSTAT_SMPHR_YES (MXC_V_SIR_FSTAT_SMPHR_YES << MXC_F_SIR_FSTAT_SMPHR_POS) /**< FSTAT_SMPHR_YES Setting */ 193 194 #define MXC_F_SIR_FSTAT_SCACHE_POS 8 /**< FSTAT_SCACHE Position */ 195 #define MXC_F_SIR_FSTAT_SCACHE ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SCACHE_POS)) /**< FSTAT_SCACHE Mask */ 196 #define MXC_V_SIR_FSTAT_SCACHE_NO ((uint32_t)0x0UL) /**< FSTAT_SCACHE_NO Value */ 197 #define MXC_S_SIR_FSTAT_SCACHE_NO (MXC_V_SIR_FSTAT_SCACHE_NO << MXC_F_SIR_FSTAT_SCACHE_POS) /**< FSTAT_SCACHE_NO Setting */ 198 #define MXC_V_SIR_FSTAT_SCACHE_YES ((uint32_t)0x1UL) /**< FSTAT_SCACHE_YES Value */ 199 #define MXC_S_SIR_FSTAT_SCACHE_YES (MXC_V_SIR_FSTAT_SCACHE_YES << MXC_F_SIR_FSTAT_SCACHE_POS) /**< FSTAT_SCACHE_YES Setting */ 200 201 /**@} end of group SIR_FSTAT_Register */ 202 203 /** 204 * @ingroup sir_registers 205 * @defgroup SIR_SFSTAT SIR_SFSTAT 206 * @brief secfuncstat register. 207 * @{ 208 */ 209 #define MXC_F_SIR_SFSTAT_TRNG_POS 2 /**< SFSTAT_TRNG Position */ 210 #define MXC_F_SIR_SFSTAT_TRNG ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_TRNG_POS)) /**< SFSTAT_TRNG Mask */ 211 #define MXC_V_SIR_SFSTAT_TRNG_NO ((uint32_t)0x0UL) /**< SFSTAT_TRNG_NO Value */ 212 #define MXC_S_SIR_SFSTAT_TRNG_NO (MXC_V_SIR_SFSTAT_TRNG_NO << MXC_F_SIR_SFSTAT_TRNG_POS) /**< SFSTAT_TRNG_NO Setting */ 213 #define MXC_V_SIR_SFSTAT_TRNG_YES ((uint32_t)0x1UL) /**< SFSTAT_TRNG_YES Value */ 214 #define MXC_S_SIR_SFSTAT_TRNG_YES (MXC_V_SIR_SFSTAT_TRNG_YES << MXC_F_SIR_SFSTAT_TRNG_POS) /**< SFSTAT_TRNG_YES Setting */ 215 216 #define MXC_F_SIR_SFSTAT_AES_POS 3 /**< SFSTAT_AES Position */ 217 #define MXC_F_SIR_SFSTAT_AES ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_AES_POS)) /**< SFSTAT_AES Mask */ 218 #define MXC_V_SIR_SFSTAT_AES_NO ((uint32_t)0x0UL) /**< SFSTAT_AES_NO Value */ 219 #define MXC_S_SIR_SFSTAT_AES_NO (MXC_V_SIR_SFSTAT_AES_NO << MXC_F_SIR_SFSTAT_AES_POS) /**< SFSTAT_AES_NO Setting */ 220 #define MXC_V_SIR_SFSTAT_AES_YES ((uint32_t)0x1UL) /**< SFSTAT_AES_YES Value */ 221 #define MXC_S_SIR_SFSTAT_AES_YES (MXC_V_SIR_SFSTAT_AES_YES << MXC_F_SIR_SFSTAT_AES_POS) /**< SFSTAT_AES_YES Setting */ 222 223 #define MXC_F_SIR_SFSTAT_SHA_POS 4 /**< SFSTAT_SHA Position */ 224 #define MXC_F_SIR_SFSTAT_SHA ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SHA_POS)) /**< SFSTAT_SHA Mask */ 225 #define MXC_V_SIR_SFSTAT_SHA_NO ((uint32_t)0x0UL) /**< SFSTAT_SHA_NO Value */ 226 #define MXC_S_SIR_SFSTAT_SHA_NO (MXC_V_SIR_SFSTAT_SHA_NO << MXC_F_SIR_SFSTAT_SHA_POS) /**< SFSTAT_SHA_NO Setting */ 227 #define MXC_V_SIR_SFSTAT_SHA_YES ((uint32_t)0x1UL) /**< SFSTAT_SHA_YES Value */ 228 #define MXC_S_SIR_SFSTAT_SHA_YES (MXC_V_SIR_SFSTAT_SHA_YES << MXC_F_SIR_SFSTAT_SHA_POS) /**< SFSTAT_SHA_YES Setting */ 229 230 #define MXC_F_SIR_SFSTAT_MAA_POS 5 /**< SFSTAT_MAA Position */ 231 #define MXC_F_SIR_SFSTAT_MAA ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_MAA_POS)) /**< SFSTAT_MAA Mask */ 232 #define MXC_V_SIR_SFSTAT_MAA_NO ((uint32_t)0x0UL) /**< SFSTAT_MAA_NO Value */ 233 #define MXC_S_SIR_SFSTAT_MAA_NO (MXC_V_SIR_SFSTAT_MAA_NO << MXC_F_SIR_SFSTAT_MAA_POS) /**< SFSTAT_MAA_NO Setting */ 234 #define MXC_V_SIR_SFSTAT_MAA_YES ((uint32_t)0x1UL) /**< SFSTAT_MAA_YES Value */ 235 #define MXC_S_SIR_SFSTAT_MAA_YES (MXC_V_SIR_SFSTAT_MAA_YES << MXC_F_SIR_SFSTAT_MAA_POS) /**< SFSTAT_MAA_YES Setting */ 236 237 /**@} end of group SIR_SFSTAT_Register */ 238 239 #ifdef __cplusplus 240 } 241 #endif 242 243 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SIR_REGS_H_ 244
