1 /** 2 * @file sdma_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SDMA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _SDMA_REGS_H_ 27 #define _SDMA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup sdma 65 * @defgroup sdma_registers SDMA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the SDMA Peripheral Module. 67 * @details Smart DMA 68 */ 69 70 /** 71 * @ingroup sdma_registers 72 * Structure type to access the SDMA Registers. 73 */ 74 typedef struct { 75 __I uint32_t ip; /**< <tt>\b 0x00:</tt> SDMA IP Register */ 76 __I uint32_t sp; /**< <tt>\b 0x04:</tt> SDMA SP Register */ 77 __I uint32_t dp0; /**< <tt>\b 0x08:</tt> SDMA DP0 Register */ 78 __I uint32_t dp1; /**< <tt>\b 0x0C:</tt> SDMA DP1 Register */ 79 __I uint32_t bp; /**< <tt>\b 0x10:</tt> SDMA BP Register */ 80 __I uint32_t offs; /**< <tt>\b 0x14:</tt> SDMA OFFS Register */ 81 __I uint32_t lc0; /**< <tt>\b 0x18:</tt> SDMA LC0 Register */ 82 __I uint32_t lc1; /**< <tt>\b 0x1C:</tt> SDMA LC1 Register */ 83 __I uint32_t a0; /**< <tt>\b 0x20:</tt> SDMA A0 Register */ 84 __I uint32_t a1; /**< <tt>\b 0x24:</tt> SDMA A1 Register */ 85 __I uint32_t a2; /**< <tt>\b 0x28:</tt> SDMA A2 Register */ 86 __I uint32_t a3; /**< <tt>\b 0x2C:</tt> SDMA A3 Register */ 87 __I uint32_t wdcn; /**< <tt>\b 0x30:</tt> SDMA WDCN Register */ 88 __R uint32_t rsv_0x34_0x7f[19]; 89 __IO uint32_t int_mux_ctrl0; /**< <tt>\b 0x80:</tt> SDMA INT_MUX_CTRL0 Register */ 90 __IO uint32_t int_mux_ctrl1; /**< <tt>\b 0x84:</tt> SDMA INT_MUX_CTRL1 Register */ 91 __IO uint32_t int_mux_ctrl2; /**< <tt>\b 0x88:</tt> SDMA INT_MUX_CTRL2 Register */ 92 __IO uint32_t int_mux_ctrl3; /**< <tt>\b 0x8C:</tt> SDMA INT_MUX_CTRL3 Register */ 93 __IO uint32_t ip_addr; /**< <tt>\b 0x90:</tt> SDMA IP_ADDR Register */ 94 __IO uint32_t ctrl; /**< <tt>\b 0x94:</tt> SDMA CTRL Register */ 95 __R uint32_t rsv_0x98_0x9f[2]; 96 __IO uint32_t int_in_ctrl; /**< <tt>\b 0xA0:</tt> SDMA INT_IN_CTRL Register */ 97 __IO uint32_t int_in_flag; /**< <tt>\b 0xA4:</tt> SDMA INT_IN_FLAG Register */ 98 __IO uint32_t int_in_ie; /**< <tt>\b 0xA8:</tt> SDMA INT_IN_IE Register */ 99 __R uint32_t rsv_0xac; 100 __IO uint32_t irq_flag; /**< <tt>\b 0xB0:</tt> SDMA IRQ_FLAG Register */ 101 __IO uint32_t irq_ie; /**< <tt>\b 0xB4:</tt> SDMA IRQ_IE Register */ 102 } mxc_sdma_regs_t; 103 104 /* Register offsets for module SDMA */ 105 /** 106 * @ingroup sdma_registers 107 * @defgroup SDMA_Register_Offsets Register Offsets 108 * @brief SDMA Peripheral Register Offsets from the SDMA Base Peripheral Address. 109 * @{ 110 */ 111 #define MXC_R_SDMA_IP ((uint32_t)0x00000000UL) /**< Offset from SDMA Base Address: <tt> 0x0000</tt> */ 112 #define MXC_R_SDMA_SP ((uint32_t)0x00000004UL) /**< Offset from SDMA Base Address: <tt> 0x0004</tt> */ 113 #define MXC_R_SDMA_DP0 ((uint32_t)0x00000008UL) /**< Offset from SDMA Base Address: <tt> 0x0008</tt> */ 114 #define MXC_R_SDMA_DP1 ((uint32_t)0x0000000CUL) /**< Offset from SDMA Base Address: <tt> 0x000C</tt> */ 115 #define MXC_R_SDMA_BP ((uint32_t)0x00000010UL) /**< Offset from SDMA Base Address: <tt> 0x0010</tt> */ 116 #define MXC_R_SDMA_OFFS ((uint32_t)0x00000014UL) /**< Offset from SDMA Base Address: <tt> 0x0014</tt> */ 117 #define MXC_R_SDMA_LC0 ((uint32_t)0x00000018UL) /**< Offset from SDMA Base Address: <tt> 0x0018</tt> */ 118 #define MXC_R_SDMA_LC1 ((uint32_t)0x0000001CUL) /**< Offset from SDMA Base Address: <tt> 0x001C</tt> */ 119 #define MXC_R_SDMA_A0 ((uint32_t)0x00000020UL) /**< Offset from SDMA Base Address: <tt> 0x0020</tt> */ 120 #define MXC_R_SDMA_A1 ((uint32_t)0x00000024UL) /**< Offset from SDMA Base Address: <tt> 0x0024</tt> */ 121 #define MXC_R_SDMA_A2 ((uint32_t)0x00000028UL) /**< Offset from SDMA Base Address: <tt> 0x0028</tt> */ 122 #define MXC_R_SDMA_A3 ((uint32_t)0x0000002CUL) /**< Offset from SDMA Base Address: <tt> 0x002C</tt> */ 123 #define MXC_R_SDMA_WDCN ((uint32_t)0x00000030UL) /**< Offset from SDMA Base Address: <tt> 0x0030</tt> */ 124 #define MXC_R_SDMA_INT_MUX_CTRL0 ((uint32_t)0x00000080UL) /**< Offset from SDMA Base Address: <tt> 0x0080</tt> */ 125 #define MXC_R_SDMA_INT_MUX_CTRL1 ((uint32_t)0x00000084UL) /**< Offset from SDMA Base Address: <tt> 0x0084</tt> */ 126 #define MXC_R_SDMA_INT_MUX_CTRL2 ((uint32_t)0x00000088UL) /**< Offset from SDMA Base Address: <tt> 0x0088</tt> */ 127 #define MXC_R_SDMA_INT_MUX_CTRL3 ((uint32_t)0x0000008CUL) /**< Offset from SDMA Base Address: <tt> 0x008C</tt> */ 128 #define MXC_R_SDMA_IP_ADDR ((uint32_t)0x00000090UL) /**< Offset from SDMA Base Address: <tt> 0x0090</tt> */ 129 #define MXC_R_SDMA_CTRL ((uint32_t)0x00000094UL) /**< Offset from SDMA Base Address: <tt> 0x0094</tt> */ 130 #define MXC_R_SDMA_INT_IN_CTRL ((uint32_t)0x000000A0UL) /**< Offset from SDMA Base Address: <tt> 0x00A0</tt> */ 131 #define MXC_R_SDMA_INT_IN_FLAG ((uint32_t)0x000000A4UL) /**< Offset from SDMA Base Address: <tt> 0x00A4</tt> */ 132 #define MXC_R_SDMA_INT_IN_IE ((uint32_t)0x000000A8UL) /**< Offset from SDMA Base Address: <tt> 0x00A8</tt> */ 133 #define MXC_R_SDMA_IRQ_FLAG ((uint32_t)0x000000B0UL) /**< Offset from SDMA Base Address: <tt> 0x00B0</tt> */ 134 #define MXC_R_SDMA_IRQ_IE ((uint32_t)0x000000B4UL) /**< Offset from SDMA Base Address: <tt> 0x00B4</tt> */ 135 /**@} end of group sdma_registers */ 136 137 /** 138 * @ingroup sdma_registers 139 * @defgroup SDMA_INT_MUX_CTRL0 SDMA_INT_MUX_CTRL0 140 * @brief Interrupt Mux Control 0. 141 * @{ 142 */ 143 #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL16_POS 0 /**< INT_MUX_CTRL0_INTSEL16 Position */ 144 #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL16 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL0_INTSEL16_POS)) /**< INT_MUX_CTRL0_INTSEL16 Mask */ 145 146 #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL17_POS 8 /**< INT_MUX_CTRL0_INTSEL17 Position */ 147 #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL17 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL0_INTSEL17_POS)) /**< INT_MUX_CTRL0_INTSEL17 Mask */ 148 149 #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL18_POS 16 /**< INT_MUX_CTRL0_INTSEL18 Position */ 150 #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL18 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL0_INTSEL18_POS)) /**< INT_MUX_CTRL0_INTSEL18 Mask */ 151 152 #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL19_POS 24 /**< INT_MUX_CTRL0_INTSEL19 Position */ 153 #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL19 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL0_INTSEL19_POS)) /**< INT_MUX_CTRL0_INTSEL19 Mask */ 154 155 /**@} end of group SDMA_INT_MUX_CTRL0_Register */ 156 157 /** 158 * @ingroup sdma_registers 159 * @defgroup SDMA_INT_MUX_CTRL1 SDMA_INT_MUX_CTRL1 160 * @brief Interrupt Mux Control 1. 161 * @{ 162 */ 163 #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL20_POS 0 /**< INT_MUX_CTRL1_INTSEL20 Position */ 164 #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL20 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL1_INTSEL20_POS)) /**< INT_MUX_CTRL1_INTSEL20 Mask */ 165 166 #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL21_POS 8 /**< INT_MUX_CTRL1_INTSEL21 Position */ 167 #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL21 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL1_INTSEL21_POS)) /**< INT_MUX_CTRL1_INTSEL21 Mask */ 168 169 #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL22_POS 16 /**< INT_MUX_CTRL1_INTSEL22 Position */ 170 #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL22 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL1_INTSEL22_POS)) /**< INT_MUX_CTRL1_INTSEL22 Mask */ 171 172 #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL23_POS 24 /**< INT_MUX_CTRL1_INTSEL23 Position */ 173 #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL23 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL1_INTSEL23_POS)) /**< INT_MUX_CTRL1_INTSEL23 Mask */ 174 175 /**@} end of group SDMA_INT_MUX_CTRL1_Register */ 176 177 /** 178 * @ingroup sdma_registers 179 * @defgroup SDMA_INT_MUX_CTRL2 SDMA_INT_MUX_CTRL2 180 * @brief Interrupt Mux Control 2. 181 * @{ 182 */ 183 #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL24_POS 0 /**< INT_MUX_CTRL2_INTSEL24 Position */ 184 #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL24 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL2_INTSEL24_POS)) /**< INT_MUX_CTRL2_INTSEL24 Mask */ 185 186 #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL25_POS 8 /**< INT_MUX_CTRL2_INTSEL25 Position */ 187 #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL25 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL2_INTSEL25_POS)) /**< INT_MUX_CTRL2_INTSEL25 Mask */ 188 189 #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL26_POS 16 /**< INT_MUX_CTRL2_INTSEL26 Position */ 190 #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL26 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL2_INTSEL26_POS)) /**< INT_MUX_CTRL2_INTSEL26 Mask */ 191 192 #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL27_POS 24 /**< INT_MUX_CTRL2_INTSEL27 Position */ 193 #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL27 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL2_INTSEL27_POS)) /**< INT_MUX_CTRL2_INTSEL27 Mask */ 194 195 /**@} end of group SDMA_INT_MUX_CTRL2_Register */ 196 197 /** 198 * @ingroup sdma_registers 199 * @defgroup SDMA_INT_MUX_CTRL3 SDMA_INT_MUX_CTRL3 200 * @brief Interrupt Mux Control 3. 201 * @{ 202 */ 203 #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL28_POS 0 /**< INT_MUX_CTRL3_INTSEL28 Position */ 204 #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL28 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL3_INTSEL28_POS)) /**< INT_MUX_CTRL3_INTSEL28 Mask */ 205 206 #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL29_POS 8 /**< INT_MUX_CTRL3_INTSEL29 Position */ 207 #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL29 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL3_INTSEL29_POS)) /**< INT_MUX_CTRL3_INTSEL29 Mask */ 208 209 #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL30_POS 16 /**< INT_MUX_CTRL3_INTSEL30 Position */ 210 #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL30 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL3_INTSEL30_POS)) /**< INT_MUX_CTRL3_INTSEL30 Mask */ 211 212 #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL31_POS 24 /**< INT_MUX_CTRL3_INTSEL31 Position */ 213 #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL31 ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL3_INTSEL31_POS)) /**< INT_MUX_CTRL3_INTSEL31 Mask */ 214 215 /**@} end of group SDMA_INT_MUX_CTRL3_Register */ 216 217 /** 218 * @ingroup sdma_registers 219 * @defgroup SDMA_IP_ADDR SDMA_IP_ADDR 220 * @brief Configurable starting IP address for Q30E. 221 * @{ 222 */ 223 #define MXC_F_SDMA_IP_ADDR_START_IP_ADDR_POS 0 /**< IP_ADDR_START_IP_ADDR Position */ 224 #define MXC_F_SDMA_IP_ADDR_START_IP_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDMA_IP_ADDR_START_IP_ADDR_POS)) /**< IP_ADDR_START_IP_ADDR Mask */ 225 226 /**@} end of group SDMA_IP_ADDR_Register */ 227 228 /** 229 * @ingroup sdma_registers 230 * @defgroup SDMA_CTRL SDMA_CTRL 231 * @brief Control Register. 232 * @{ 233 */ 234 #define MXC_F_SDMA_CTRL_EN_POS 0 /**< CTRL_EN Position */ 235 #define MXC_F_SDMA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_SDMA_CTRL_EN_POS)) /**< CTRL_EN Mask */ 236 #define MXC_V_SDMA_CTRL_EN_DIS ((uint32_t)0x0UL) /**< CTRL_EN_DIS Value */ 237 #define MXC_S_SDMA_CTRL_EN_DIS (MXC_V_SDMA_CTRL_EN_DIS << MXC_F_SDMA_CTRL_EN_POS) /**< CTRL_EN_DIS Setting */ 238 #define MXC_V_SDMA_CTRL_EN_EN ((uint32_t)0x1UL) /**< CTRL_EN_EN Value */ 239 #define MXC_S_SDMA_CTRL_EN_EN (MXC_V_SDMA_CTRL_EN_EN << MXC_F_SDMA_CTRL_EN_POS) /**< CTRL_EN_EN Setting */ 240 241 /**@} end of group SDMA_CTRL_Register */ 242 243 /** 244 * @ingroup sdma_registers 245 * @defgroup SDMA_INT_IN_CTRL SDMA_INT_IN_CTRL 246 * @brief Interrupt Input From CPU Control Register. 247 * @{ 248 */ 249 #define MXC_F_SDMA_INT_IN_CTRL_INTSET_POS 0 /**< INT_IN_CTRL_INTSET Position */ 250 #define MXC_F_SDMA_INT_IN_CTRL_INTSET ((uint32_t)(0x1UL << MXC_F_SDMA_INT_IN_CTRL_INTSET_POS)) /**< INT_IN_CTRL_INTSET Mask */ 251 #define MXC_V_SDMA_INT_IN_CTRL_INTSET_DIS ((uint32_t)0x0UL) /**< INT_IN_CTRL_INTSET_DIS Value */ 252 #define MXC_S_SDMA_INT_IN_CTRL_INTSET_DIS (MXC_V_SDMA_INT_IN_CTRL_INTSET_DIS << MXC_F_SDMA_INT_IN_CTRL_INTSET_POS) /**< INT_IN_CTRL_INTSET_DIS Setting */ 253 #define MXC_V_SDMA_INT_IN_CTRL_INTSET_SET ((uint32_t)0x1UL) /**< INT_IN_CTRL_INTSET_SET Value */ 254 #define MXC_S_SDMA_INT_IN_CTRL_INTSET_SET (MXC_V_SDMA_INT_IN_CTRL_INTSET_SET << MXC_F_SDMA_INT_IN_CTRL_INTSET_POS) /**< INT_IN_CTRL_INTSET_SET Setting */ 255 256 /**@} end of group SDMA_INT_IN_CTRL_Register */ 257 258 /** 259 * @ingroup sdma_registers 260 * @defgroup SDMA_INT_IN_FLAG SDMA_INT_IN_FLAG 261 * @brief Interrupt Input From CPU Flag. 262 * @{ 263 */ 264 #define MXC_F_SDMA_INT_IN_FLAG_INTFLAG_POS 0 /**< INT_IN_FLAG_INTFLAG Position */ 265 #define MXC_F_SDMA_INT_IN_FLAG_INTFLAG ((uint32_t)(0x1UL << MXC_F_SDMA_INT_IN_FLAG_INTFLAG_POS)) /**< INT_IN_FLAG_INTFLAG Mask */ 266 #define MXC_V_SDMA_INT_IN_FLAG_INTFLAG_NO_EFF ((uint32_t)0x0UL) /**< INT_IN_FLAG_INTFLAG_NO_EFF Value */ 267 #define MXC_S_SDMA_INT_IN_FLAG_INTFLAG_NO_EFF (MXC_V_SDMA_INT_IN_FLAG_INTFLAG_NO_EFF << MXC_F_SDMA_INT_IN_FLAG_INTFLAG_POS) /**< INT_IN_FLAG_INTFLAG_NO_EFF Setting */ 268 #define MXC_V_SDMA_INT_IN_FLAG_INTFLAG_CLEAR ((uint32_t)0x1UL) /**< INT_IN_FLAG_INTFLAG_CLEAR Value */ 269 #define MXC_S_SDMA_INT_IN_FLAG_INTFLAG_CLEAR (MXC_V_SDMA_INT_IN_FLAG_INTFLAG_CLEAR << MXC_F_SDMA_INT_IN_FLAG_INTFLAG_POS) /**< INT_IN_FLAG_INTFLAG_CLEAR Setting */ 270 271 /**@} end of group SDMA_INT_IN_FLAG_Register */ 272 273 /** 274 * @ingroup sdma_registers 275 * @defgroup SDMA_INT_IN_IE SDMA_INT_IN_IE 276 * @brief Interrupt Input From CPU Enable. 277 * @{ 278 */ 279 #define MXC_F_SDMA_INT_IN_IE_INT_IN_EN_POS 0 /**< INT_IN_IE_INT_IN_EN Position */ 280 #define MXC_F_SDMA_INT_IN_IE_INT_IN_EN ((uint32_t)(0x1UL << MXC_F_SDMA_INT_IN_IE_INT_IN_EN_POS)) /**< INT_IN_IE_INT_IN_EN Mask */ 281 282 /**@} end of group SDMA_INT_IN_IE_Register */ 283 284 /** 285 * @ingroup sdma_registers 286 * @defgroup SDMA_IRQ_FLAG SDMA_IRQ_FLAG 287 * @brief Interrupt Output To CPU Flag. 288 * @{ 289 */ 290 #define MXC_F_SDMA_IRQ_FLAG_IRQ_FLAG_POS 0 /**< IRQ_FLAG_IRQ_FLAG Position */ 291 #define MXC_F_SDMA_IRQ_FLAG_IRQ_FLAG ((uint32_t)(0x1UL << MXC_F_SDMA_IRQ_FLAG_IRQ_FLAG_POS)) /**< IRQ_FLAG_IRQ_FLAG Mask */ 292 293 /**@} end of group SDMA_IRQ_FLAG_Register */ 294 295 /** 296 * @ingroup sdma_registers 297 * @defgroup SDMA_IRQ_IE SDMA_IRQ_IE 298 * @brief Interrupt Output To CPU Control Register. 299 * @{ 300 */ 301 #define MXC_F_SDMA_IRQ_IE_IRQ_EN_POS 0 /**< IRQ_IE_IRQ_EN Position */ 302 #define MXC_F_SDMA_IRQ_IE_IRQ_EN ((uint32_t)(0x1UL << MXC_F_SDMA_IRQ_IE_IRQ_EN_POS)) /**< IRQ_IE_IRQ_EN Mask */ 303 304 /**@} end of group SDMA_IRQ_IE_Register */ 305 306 #ifdef __cplusplus 307 } 308 #endif 309 310 #endif /* _SDMA_REGS_H_ */ 311
