1 /** 2 * @file sdhc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SDHC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup sdhc_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SDHC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SDHC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup sdhc 67 * @defgroup sdhc_registers SDHC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SDHC Peripheral Module. 69 * @details SDHC/SDIO Controller 70 */ 71 72 /** 73 * @ingroup sdhc_registers 74 * Structure type to access the SDHC Registers. 75 */ 76 typedef struct { 77 __IO uint32_t sdma; /**< <tt>\b 0x00:</tt> SDHC SDMA Register */ 78 __IO uint16_t blk_size; /**< <tt>\b 0x04:</tt> SDHC BLK_SIZE Register */ 79 __IO uint16_t blk_cnt; /**< <tt>\b 0x06:</tt> SDHC BLK_CNT Register */ 80 __IO uint32_t arg_1; /**< <tt>\b 0x08:</tt> SDHC ARG_1 Register */ 81 __IO uint16_t trans; /**< <tt>\b 0x0C:</tt> SDHC TRANS Register */ 82 __IO uint16_t cmd; /**< <tt>\b 0x0E:</tt> SDHC CMD Register */ 83 __IO uint16_t resp[8]; /**< <tt>\b 0x010:</tt> SDHC RESP Register */ 84 __IO uint32_t buffer; /**< <tt>\b 0x20:</tt> SDHC BUFFER Register */ 85 __I uint32_t present; /**< <tt>\b 0x024:</tt> SDHC PRESENT Register */ 86 __IO uint8_t host_cn_1; /**< <tt>\b 0x028:</tt> SDHC HOST_CN_1 Register */ 87 __IO uint8_t pwr; /**< <tt>\b 0x029:</tt> SDHC PWR Register */ 88 __IO uint8_t blk_gap; /**< <tt>\b 0x02A:</tt> SDHC BLK_GAP Register */ 89 __IO uint8_t wakeup; /**< <tt>\b 0x02B:</tt> SDHC WAKEUP Register */ 90 __IO uint16_t clk_cn; /**< <tt>\b 0x02C:</tt> SDHC CLK_CN Register */ 91 __IO uint8_t to; /**< <tt>\b 0x02E:</tt> SDHC TO Register */ 92 __IO uint8_t sw_reset; /**< <tt>\b 0x02F:</tt> SDHC SW_RESET Register */ 93 __IO uint16_t int_stat; /**< <tt>\b 0x030:</tt> SDHC INT_STAT Register */ 94 __IO uint16_t er_int_stat; /**< <tt>\b 0x032:</tt> SDHC ER_INT_STAT Register */ 95 __IO uint16_t int_en; /**< <tt>\b 0x034:</tt> SDHC INT_EN Register */ 96 __IO uint16_t er_int_en; /**< <tt>\b 0x36:</tt> SDHC ER_INT_EN Register */ 97 __IO uint16_t int_signal; /**< <tt>\b 0x038:</tt> SDHC INT_SIGNAL Register */ 98 __IO uint16_t er_int_signal; /**< <tt>\b 0x03A:</tt> SDHC ER_INT_SIGNAL Register */ 99 __IO uint16_t auto_cmd_er; /**< <tt>\b 0x03C:</tt> SDHC AUTO_CMD_ER Register */ 100 __IO uint16_t host_cn_2; /**< <tt>\b 0x03E:</tt> SDHC HOST_CN_2 Register */ 101 __I uint32_t cfg_0; /**< <tt>\b 0x040:</tt> SDHC CFG_0 Register */ 102 __I uint32_t cfg_1; /**< <tt>\b 0x044:</tt> SDHC CFG_1 Register */ 103 __I uint32_t max_curr_cfg; /**< <tt>\b 0x048:</tt> SDHC MAX_CURR_CFG Register */ 104 __R uint32_t rsv_0x4c; 105 __O uint16_t force_cmd; /**< <tt>\b 0x050:</tt> SDHC FORCE_CMD Register */ 106 __IO uint16_t force_event_int_stat; /**< <tt>\b 0x052:</tt> SDHC FORCE_EVENT_INT_STAT Register */ 107 __IO uint8_t adma_er; /**< <tt>\b 0x054:</tt> SDHC ADMA_ER Register */ 108 __R uint8_t rsv_0x55_0x57[3]; 109 __IO uint32_t adma_addr_0; /**< <tt>\b 0x058:</tt> SDHC ADMA_ADDR_0 Register */ 110 __IO uint32_t adma_addr_1; /**< <tt>\b 0x05C:</tt> SDHC ADMA_ADDR_1 Register */ 111 __I uint16_t preset_0; /**< <tt>\b 0x060:</tt> SDHC PRESET_0 Register */ 112 __I uint16_t preset_1; /**< <tt>\b 0x062:</tt> SDHC PRESET_1 Register */ 113 __I uint16_t preset_2; /**< <tt>\b 0x064:</tt> SDHC PRESET_2 Register */ 114 __I uint16_t preset_3; /**< <tt>\b 0x066:</tt> SDHC PRESET_3 Register */ 115 __I uint16_t preset_4; /**< <tt>\b 0x068:</tt> SDHC PRESET_4 Register */ 116 __I uint16_t preset_5; /**< <tt>\b 0x06A:</tt> SDHC PRESET_5 Register */ 117 __I uint16_t preset_6; /**< <tt>\b 0x06C:</tt> SDHC PRESET_6 Register */ 118 __I uint16_t preset_7; /**< <tt>\b 0x06E:</tt> SDHC PRESET_7 Register */ 119 __R uint32_t rsv_0x70_0xdf[28]; 120 __IO uint32_t shared_bus; /**< <tt>\b 0x0E0:</tt> SDHC SHARED_BUS Register */ 121 __R uint32_t rsv_0xe4_0xfb[6]; 122 __I uint16_t slot_int; /**< <tt>\b 0x0FC:</tt> SDHC SLOT_INT Register */ 123 __IO uint16_t host_cn_ver; /**< <tt>\b 0x0FE:</tt> SDHC HOST_CN_VER Register */ 124 } mxc_sdhc_regs_t; 125 126 /* Register offsets for module SDHC */ 127 /** 128 * @ingroup sdhc_registers 129 * @defgroup SDHC_Register_Offsets Register Offsets 130 * @brief SDHC Peripheral Register Offsets from the SDHC Base Peripheral Address. 131 * @{ 132 */ 133 #define MXC_R_SDHC_SDMA ((uint32_t)0x00000000UL) /**< Offset from SDHC Base Address: <tt> 0x0000</tt> */ 134 #define MXC_R_SDHC_BLK_SIZE ((uint32_t)0x00000004UL) /**< Offset from SDHC Base Address: <tt> 0x0004</tt> */ 135 #define MXC_R_SDHC_BLK_CNT ((uint32_t)0x00000006UL) /**< Offset from SDHC Base Address: <tt> 0x0006</tt> */ 136 #define MXC_R_SDHC_ARG_1 ((uint32_t)0x00000008UL) /**< Offset from SDHC Base Address: <tt> 0x0008</tt> */ 137 #define MXC_R_SDHC_TRANS ((uint32_t)0x0000000CUL) /**< Offset from SDHC Base Address: <tt> 0x000C</tt> */ 138 #define MXC_R_SDHC_CMD ((uint32_t)0x0000000EUL) /**< Offset from SDHC Base Address: <tt> 0x000E</tt> */ 139 #define MXC_R_SDHC_RESP ((uint32_t)0x00000010UL) /**< Offset from SDHC Base Address: <tt> 0x0010</tt> */ 140 #define MXC_R_SDHC_BUFFER ((uint32_t)0x00000020UL) /**< Offset from SDHC Base Address: <tt> 0x0020</tt> */ 141 #define MXC_R_SDHC_PRESENT ((uint32_t)0x00000024UL) /**< Offset from SDHC Base Address: <tt> 0x0024</tt> */ 142 #define MXC_R_SDHC_HOST_CN_1 ((uint32_t)0x00000028UL) /**< Offset from SDHC Base Address: <tt> 0x0028</tt> */ 143 #define MXC_R_SDHC_PWR ((uint32_t)0x00000029UL) /**< Offset from SDHC Base Address: <tt> 0x0029</tt> */ 144 #define MXC_R_SDHC_BLK_GAP ((uint32_t)0x0000002AUL) /**< Offset from SDHC Base Address: <tt> 0x002A</tt> */ 145 #define MXC_R_SDHC_WAKEUP ((uint32_t)0x0000002BUL) /**< Offset from SDHC Base Address: <tt> 0x002B</tt> */ 146 #define MXC_R_SDHC_CLK_CN ((uint32_t)0x0000002CUL) /**< Offset from SDHC Base Address: <tt> 0x002C</tt> */ 147 #define MXC_R_SDHC_TO ((uint32_t)0x0000002EUL) /**< Offset from SDHC Base Address: <tt> 0x002E</tt> */ 148 #define MXC_R_SDHC_SW_RESET ((uint32_t)0x0000002FUL) /**< Offset from SDHC Base Address: <tt> 0x002F</tt> */ 149 #define MXC_R_SDHC_INT_STAT ((uint32_t)0x00000030UL) /**< Offset from SDHC Base Address: <tt> 0x0030</tt> */ 150 #define MXC_R_SDHC_ER_INT_STAT ((uint32_t)0x00000032UL) /**< Offset from SDHC Base Address: <tt> 0x0032</tt> */ 151 #define MXC_R_SDHC_INT_EN ((uint32_t)0x00000034UL) /**< Offset from SDHC Base Address: <tt> 0x0034</tt> */ 152 #define MXC_R_SDHC_ER_INT_EN ((uint32_t)0x00000036UL) /**< Offset from SDHC Base Address: <tt> 0x0036</tt> */ 153 #define MXC_R_SDHC_INT_SIGNAL ((uint32_t)0x00000038UL) /**< Offset from SDHC Base Address: <tt> 0x0038</tt> */ 154 #define MXC_R_SDHC_ER_INT_SIGNAL ((uint32_t)0x0000003AUL) /**< Offset from SDHC Base Address: <tt> 0x003A</tt> */ 155 #define MXC_R_SDHC_AUTO_CMD_ER ((uint32_t)0x0000003CUL) /**< Offset from SDHC Base Address: <tt> 0x003C</tt> */ 156 #define MXC_R_SDHC_HOST_CN_2 ((uint32_t)0x0000003EUL) /**< Offset from SDHC Base Address: <tt> 0x003E</tt> */ 157 #define MXC_R_SDHC_CFG_0 ((uint32_t)0x00000040UL) /**< Offset from SDHC Base Address: <tt> 0x0040</tt> */ 158 #define MXC_R_SDHC_CFG_1 ((uint32_t)0x00000044UL) /**< Offset from SDHC Base Address: <tt> 0x0044</tt> */ 159 #define MXC_R_SDHC_MAX_CURR_CFG ((uint32_t)0x00000048UL) /**< Offset from SDHC Base Address: <tt> 0x0048</tt> */ 160 #define MXC_R_SDHC_FORCE_CMD ((uint32_t)0x00000050UL) /**< Offset from SDHC Base Address: <tt> 0x0050</tt> */ 161 #define MXC_R_SDHC_FORCE_EVENT_INT_STAT ((uint32_t)0x00000052UL) /**< Offset from SDHC Base Address: <tt> 0x0052</tt> */ 162 #define MXC_R_SDHC_ADMA_ER ((uint32_t)0x00000054UL) /**< Offset from SDHC Base Address: <tt> 0x0054</tt> */ 163 #define MXC_R_SDHC_ADMA_ADDR_0 ((uint32_t)0x00000058UL) /**< Offset from SDHC Base Address: <tt> 0x0058</tt> */ 164 #define MXC_R_SDHC_ADMA_ADDR_1 ((uint32_t)0x0000005CUL) /**< Offset from SDHC Base Address: <tt> 0x005C</tt> */ 165 #define MXC_R_SDHC_PRESET_0 ((uint32_t)0x00000060UL) /**< Offset from SDHC Base Address: <tt> 0x0060</tt> */ 166 #define MXC_R_SDHC_PRESET_1 ((uint32_t)0x00000062UL) /**< Offset from SDHC Base Address: <tt> 0x0062</tt> */ 167 #define MXC_R_SDHC_PRESET_2 ((uint32_t)0x00000064UL) /**< Offset from SDHC Base Address: <tt> 0x0064</tt> */ 168 #define MXC_R_SDHC_PRESET_3 ((uint32_t)0x00000066UL) /**< Offset from SDHC Base Address: <tt> 0x0066</tt> */ 169 #define MXC_R_SDHC_PRESET_4 ((uint32_t)0x00000068UL) /**< Offset from SDHC Base Address: <tt> 0x0068</tt> */ 170 #define MXC_R_SDHC_PRESET_5 ((uint32_t)0x0000006AUL) /**< Offset from SDHC Base Address: <tt> 0x006A</tt> */ 171 #define MXC_R_SDHC_PRESET_6 ((uint32_t)0x0000006CUL) /**< Offset from SDHC Base Address: <tt> 0x006C</tt> */ 172 #define MXC_R_SDHC_PRESET_7 ((uint32_t)0x0000006EUL) /**< Offset from SDHC Base Address: <tt> 0x006E</tt> */ 173 #define MXC_R_SDHC_SHARED_BUS ((uint32_t)0x000000E0UL) /**< Offset from SDHC Base Address: <tt> 0x00E0</tt> */ 174 #define MXC_R_SDHC_SLOT_INT ((uint32_t)0x000000FCUL) /**< Offset from SDHC Base Address: <tt> 0x00FC</tt> */ 175 #define MXC_R_SDHC_HOST_CN_VER ((uint32_t)0x000000FEUL) /**< Offset from SDHC Base Address: <tt> 0x00FE</tt> */ 176 /**@} end of group sdhc_registers */ 177 178 /** 179 * @ingroup sdhc_registers 180 * @defgroup SDHC_SDMA SDHC_SDMA 181 * @brief SDMA System Address / Argument 2. 182 * @{ 183 */ 184 #define MXC_F_SDHC_SDMA_ADDR_POS 0 /**< SDMA_ADDR Position */ 185 #define MXC_F_SDHC_SDMA_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_SDMA_ADDR_POS)) /**< SDMA_ADDR Mask */ 186 187 /**@} end of group SDHC_SDMA_Register */ 188 189 /** 190 * @ingroup sdhc_registers 191 * @defgroup SDHC_BLK_SIZE SDHC_BLK_SIZE 192 * @brief Block Size. 193 * @{ 194 */ 195 #define MXC_F_SDHC_BLK_SIZE_TRANS_POS 0 /**< BLK_SIZE_TRANS Position */ 196 #define MXC_F_SDHC_BLK_SIZE_TRANS ((uint16_t)(0xFFFUL << MXC_F_SDHC_BLK_SIZE_TRANS_POS)) /**< BLK_SIZE_TRANS Mask */ 197 198 #define MXC_F_SDHC_BLK_SIZE_HOST_BUF_POS 12 /**< BLK_SIZE_HOST_BUF Position */ 199 #define MXC_F_SDHC_BLK_SIZE_HOST_BUF ((uint16_t)(0x7UL << MXC_F_SDHC_BLK_SIZE_HOST_BUF_POS)) /**< BLK_SIZE_HOST_BUF Mask */ 200 #define MXC_V_SDHC_BLK_SIZE_HOST_BUF_4KB ((uint16_t)0x0UL) /**< BLK_SIZE_HOST_BUF_4KB Value */ 201 #define MXC_S_SDHC_BLK_SIZE_HOST_BUF_4KB (MXC_V_SDHC_BLK_SIZE_HOST_BUF_4KB << MXC_F_SDHC_BLK_SIZE_HOST_BUF_POS) /**< BLK_SIZE_HOST_BUF_4KB Setting */ 202 #define MXC_V_SDHC_BLK_SIZE_HOST_BUF_8KB ((uint16_t)0x1UL) /**< BLK_SIZE_HOST_BUF_8KB Value */ 203 #define MXC_S_SDHC_BLK_SIZE_HOST_BUF_8KB (MXC_V_SDHC_BLK_SIZE_HOST_BUF_8KB << MXC_F_SDHC_BLK_SIZE_HOST_BUF_POS) /**< BLK_SIZE_HOST_BUF_8KB Setting */ 204 #define MXC_V_SDHC_BLK_SIZE_HOST_BUF_16KB ((uint16_t)0x2UL) /**< BLK_SIZE_HOST_BUF_16KB Value */ 205 #define MXC_S_SDHC_BLK_SIZE_HOST_BUF_16KB (MXC_V_SDHC_BLK_SIZE_HOST_BUF_16KB << MXC_F_SDHC_BLK_SIZE_HOST_BUF_POS) /**< BLK_SIZE_HOST_BUF_16KB Setting */ 206 #define MXC_V_SDHC_BLK_SIZE_HOST_BUF_32KB ((uint16_t)0x3UL) /**< BLK_SIZE_HOST_BUF_32KB Value */ 207 #define MXC_S_SDHC_BLK_SIZE_HOST_BUF_32KB (MXC_V_SDHC_BLK_SIZE_HOST_BUF_32KB << MXC_F_SDHC_BLK_SIZE_HOST_BUF_POS) /**< BLK_SIZE_HOST_BUF_32KB Setting */ 208 #define MXC_V_SDHC_BLK_SIZE_HOST_BUF_64KB ((uint16_t)0x4UL) /**< BLK_SIZE_HOST_BUF_64KB Value */ 209 #define MXC_S_SDHC_BLK_SIZE_HOST_BUF_64KB (MXC_V_SDHC_BLK_SIZE_HOST_BUF_64KB << MXC_F_SDHC_BLK_SIZE_HOST_BUF_POS) /**< BLK_SIZE_HOST_BUF_64KB Setting */ 210 #define MXC_V_SDHC_BLK_SIZE_HOST_BUF_128KB ((uint16_t)0x5UL) /**< BLK_SIZE_HOST_BUF_128KB Value */ 211 #define MXC_S_SDHC_BLK_SIZE_HOST_BUF_128KB (MXC_V_SDHC_BLK_SIZE_HOST_BUF_128KB << MXC_F_SDHC_BLK_SIZE_HOST_BUF_POS) /**< BLK_SIZE_HOST_BUF_128KB Setting */ 212 #define MXC_V_SDHC_BLK_SIZE_HOST_BUF_256KB ((uint16_t)0x6UL) /**< BLK_SIZE_HOST_BUF_256KB Value */ 213 #define MXC_S_SDHC_BLK_SIZE_HOST_BUF_256KB (MXC_V_SDHC_BLK_SIZE_HOST_BUF_256KB << MXC_F_SDHC_BLK_SIZE_HOST_BUF_POS) /**< BLK_SIZE_HOST_BUF_256KB Setting */ 214 #define MXC_V_SDHC_BLK_SIZE_HOST_BUF_512KB ((uint16_t)0x7UL) /**< BLK_SIZE_HOST_BUF_512KB Value */ 215 #define MXC_S_SDHC_BLK_SIZE_HOST_BUF_512KB (MXC_V_SDHC_BLK_SIZE_HOST_BUF_512KB << MXC_F_SDHC_BLK_SIZE_HOST_BUF_POS) /**< BLK_SIZE_HOST_BUF_512KB Setting */ 216 217 /**@} end of group SDHC_BLK_SIZE_Register */ 218 219 /** 220 * @ingroup sdhc_registers 221 * @defgroup SDHC_BLK_CNT SDHC_BLK_CNT 222 * @brief Block Count. 223 * @{ 224 */ 225 #define MXC_F_SDHC_BLK_CNT_COUNT_POS 0 /**< BLK_CNT_COUNT Position */ 226 #define MXC_F_SDHC_BLK_CNT_COUNT ((uint16_t)(0xFFFFUL << MXC_F_SDHC_BLK_CNT_COUNT_POS)) /**< BLK_CNT_COUNT Mask */ 227 228 /**@} end of group SDHC_BLK_CNT_Register */ 229 230 /** 231 * @ingroup sdhc_registers 232 * @defgroup SDHC_ARG_1 SDHC_ARG_1 233 * @brief Argument 1. 234 * @{ 235 */ 236 #define MXC_F_SDHC_ARG_1_CMD_POS 0 /**< ARG_1_CMD Position */ 237 #define MXC_F_SDHC_ARG_1_CMD ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_ARG_1_CMD_POS)) /**< ARG_1_CMD Mask */ 238 239 /**@} end of group SDHC_ARG_1_Register */ 240 241 /** 242 * @ingroup sdhc_registers 243 * @defgroup SDHC_TRANS SDHC_TRANS 244 * @brief Transfer Mode. 245 * @{ 246 */ 247 #define MXC_F_SDHC_TRANS_DMA_EN_POS 0 /**< TRANS_DMA_EN Position */ 248 #define MXC_F_SDHC_TRANS_DMA_EN ((uint16_t)(0x1UL << MXC_F_SDHC_TRANS_DMA_EN_POS)) /**< TRANS_DMA_EN Mask */ 249 #define MXC_V_SDHC_TRANS_DMA_EN_DIS ((uint16_t)0x0UL) /**< TRANS_DMA_EN_DIS Value */ 250 #define MXC_S_SDHC_TRANS_DMA_EN_DIS (MXC_V_SDHC_TRANS_DMA_EN_DIS << MXC_F_SDHC_TRANS_DMA_EN_POS) /**< TRANS_DMA_EN_DIS Setting */ 251 #define MXC_V_SDHC_TRANS_DMA_EN_EN ((uint16_t)0x1UL) /**< TRANS_DMA_EN_EN Value */ 252 #define MXC_S_SDHC_TRANS_DMA_EN_EN (MXC_V_SDHC_TRANS_DMA_EN_EN << MXC_F_SDHC_TRANS_DMA_EN_POS) /**< TRANS_DMA_EN_EN Setting */ 253 254 #define MXC_F_SDHC_TRANS_BLK_CNT_EN_POS 1 /**< TRANS_BLK_CNT_EN Position */ 255 #define MXC_F_SDHC_TRANS_BLK_CNT_EN ((uint16_t)(0x1UL << MXC_F_SDHC_TRANS_BLK_CNT_EN_POS)) /**< TRANS_BLK_CNT_EN Mask */ 256 #define MXC_V_SDHC_TRANS_BLK_CNT_EN_DIS ((uint16_t)0x0UL) /**< TRANS_BLK_CNT_EN_DIS Value */ 257 #define MXC_S_SDHC_TRANS_BLK_CNT_EN_DIS (MXC_V_SDHC_TRANS_BLK_CNT_EN_DIS << MXC_F_SDHC_TRANS_BLK_CNT_EN_POS) /**< TRANS_BLK_CNT_EN_DIS Setting */ 258 #define MXC_V_SDHC_TRANS_BLK_CNT_EN_EN ((uint16_t)0x1UL) /**< TRANS_BLK_CNT_EN_EN Value */ 259 #define MXC_S_SDHC_TRANS_BLK_CNT_EN_EN (MXC_V_SDHC_TRANS_BLK_CNT_EN_EN << MXC_F_SDHC_TRANS_BLK_CNT_EN_POS) /**< TRANS_BLK_CNT_EN_EN Setting */ 260 261 #define MXC_F_SDHC_TRANS_AUTO_CMD_EN_POS 2 /**< TRANS_AUTO_CMD_EN Position */ 262 #define MXC_F_SDHC_TRANS_AUTO_CMD_EN ((uint16_t)(0x3UL << MXC_F_SDHC_TRANS_AUTO_CMD_EN_POS)) /**< TRANS_AUTO_CMD_EN Mask */ 263 #define MXC_V_SDHC_TRANS_AUTO_CMD_EN_DISABLE ((uint16_t)0x0UL) /**< TRANS_AUTO_CMD_EN_DISABLE Value */ 264 #define MXC_S_SDHC_TRANS_AUTO_CMD_EN_DISABLE (MXC_V_SDHC_TRANS_AUTO_CMD_EN_DISABLE << MXC_F_SDHC_TRANS_AUTO_CMD_EN_POS) /**< TRANS_AUTO_CMD_EN_DISABLE Setting */ 265 #define MXC_V_SDHC_TRANS_AUTO_CMD_EN_CMD12 ((uint16_t)0x1UL) /**< TRANS_AUTO_CMD_EN_CMD12 Value */ 266 #define MXC_S_SDHC_TRANS_AUTO_CMD_EN_CMD12 (MXC_V_SDHC_TRANS_AUTO_CMD_EN_CMD12 << MXC_F_SDHC_TRANS_AUTO_CMD_EN_POS) /**< TRANS_AUTO_CMD_EN_CMD12 Setting */ 267 #define MXC_V_SDHC_TRANS_AUTO_CMD_EN_CMD23 ((uint16_t)0x2UL) /**< TRANS_AUTO_CMD_EN_CMD23 Value */ 268 #define MXC_S_SDHC_TRANS_AUTO_CMD_EN_CMD23 (MXC_V_SDHC_TRANS_AUTO_CMD_EN_CMD23 << MXC_F_SDHC_TRANS_AUTO_CMD_EN_POS) /**< TRANS_AUTO_CMD_EN_CMD23 Setting */ 269 270 #define MXC_F_SDHC_TRANS_READ_WRITE_POS 4 /**< TRANS_READ_WRITE Position */ 271 #define MXC_F_SDHC_TRANS_READ_WRITE ((uint16_t)(0x1UL << MXC_F_SDHC_TRANS_READ_WRITE_POS)) /**< TRANS_READ_WRITE Mask */ 272 #define MXC_V_SDHC_TRANS_READ_WRITE_WRITE ((uint16_t)0x0UL) /**< TRANS_READ_WRITE_WRITE Value */ 273 #define MXC_S_SDHC_TRANS_READ_WRITE_WRITE (MXC_V_SDHC_TRANS_READ_WRITE_WRITE << MXC_F_SDHC_TRANS_READ_WRITE_POS) /**< TRANS_READ_WRITE_WRITE Setting */ 274 #define MXC_V_SDHC_TRANS_READ_WRITE_READ ((uint16_t)0x1UL) /**< TRANS_READ_WRITE_READ Value */ 275 #define MXC_S_SDHC_TRANS_READ_WRITE_READ (MXC_V_SDHC_TRANS_READ_WRITE_READ << MXC_F_SDHC_TRANS_READ_WRITE_POS) /**< TRANS_READ_WRITE_READ Setting */ 276 277 #define MXC_F_SDHC_TRANS_MULTI_POS 5 /**< TRANS_MULTI Position */ 278 #define MXC_F_SDHC_TRANS_MULTI ((uint16_t)(0x1UL << MXC_F_SDHC_TRANS_MULTI_POS)) /**< TRANS_MULTI Mask */ 279 #define MXC_V_SDHC_TRANS_MULTI_MULTI ((uint16_t)0x1UL) /**< TRANS_MULTI_MULTI Value */ 280 #define MXC_S_SDHC_TRANS_MULTI_MULTI (MXC_V_SDHC_TRANS_MULTI_MULTI << MXC_F_SDHC_TRANS_MULTI_POS) /**< TRANS_MULTI_MULTI Setting */ 281 #define MXC_V_SDHC_TRANS_MULTI_SINGLE ((uint16_t)0x0UL) /**< TRANS_MULTI_SINGLE Value */ 282 #define MXC_S_SDHC_TRANS_MULTI_SINGLE (MXC_V_SDHC_TRANS_MULTI_SINGLE << MXC_F_SDHC_TRANS_MULTI_POS) /**< TRANS_MULTI_SINGLE Setting */ 283 284 /**@} end of group SDHC_TRANS_Register */ 285 286 /** 287 * @ingroup sdhc_registers 288 * @defgroup SDHC_CMD SDHC_CMD 289 * @brief Command. 290 * @{ 291 */ 292 #define MXC_F_SDHC_CMD_RESP_TYPE_POS 0 /**< CMD_RESP_TYPE Position */ 293 #define MXC_F_SDHC_CMD_RESP_TYPE ((uint16_t)(0x3UL << MXC_F_SDHC_CMD_RESP_TYPE_POS)) /**< CMD_RESP_TYPE Mask */ 294 #define MXC_V_SDHC_CMD_RESP_TYPE_NONE ((uint16_t)0x0UL) /**< CMD_RESP_TYPE_NONE Value */ 295 #define MXC_S_SDHC_CMD_RESP_TYPE_NONE (MXC_V_SDHC_CMD_RESP_TYPE_NONE << MXC_F_SDHC_CMD_RESP_TYPE_POS) /**< CMD_RESP_TYPE_NONE Setting */ 296 #define MXC_V_SDHC_CMD_RESP_TYPE_RESP136 ((uint16_t)0x1UL) /**< CMD_RESP_TYPE_RESP136 Value */ 297 #define MXC_S_SDHC_CMD_RESP_TYPE_RESP136 (MXC_V_SDHC_CMD_RESP_TYPE_RESP136 << MXC_F_SDHC_CMD_RESP_TYPE_POS) /**< CMD_RESP_TYPE_RESP136 Setting */ 298 #define MXC_V_SDHC_CMD_RESP_TYPE_RESP48 ((uint16_t)0x2UL) /**< CMD_RESP_TYPE_RESP48 Value */ 299 #define MXC_S_SDHC_CMD_RESP_TYPE_RESP48 (MXC_V_SDHC_CMD_RESP_TYPE_RESP48 << MXC_F_SDHC_CMD_RESP_TYPE_POS) /**< CMD_RESP_TYPE_RESP48 Setting */ 300 #define MXC_V_SDHC_CMD_RESP_TYPE_RESP48_BUSY ((uint16_t)0x3UL) /**< CMD_RESP_TYPE_RESP48_BUSY Value */ 301 #define MXC_S_SDHC_CMD_RESP_TYPE_RESP48_BUSY (MXC_V_SDHC_CMD_RESP_TYPE_RESP48_BUSY << MXC_F_SDHC_CMD_RESP_TYPE_POS) /**< CMD_RESP_TYPE_RESP48_BUSY Setting */ 302 303 #define MXC_F_SDHC_CMD_CRC_CHK_EN_POS 3 /**< CMD_CRC_CHK_EN Position */ 304 #define MXC_F_SDHC_CMD_CRC_CHK_EN ((uint16_t)(0x1UL << MXC_F_SDHC_CMD_CRC_CHK_EN_POS)) /**< CMD_CRC_CHK_EN Mask */ 305 #define MXC_V_SDHC_CMD_CRC_CHK_EN_EN ((uint16_t)0x1UL) /**< CMD_CRC_CHK_EN_EN Value */ 306 #define MXC_S_SDHC_CMD_CRC_CHK_EN_EN (MXC_V_SDHC_CMD_CRC_CHK_EN_EN << MXC_F_SDHC_CMD_CRC_CHK_EN_POS) /**< CMD_CRC_CHK_EN_EN Setting */ 307 #define MXC_V_SDHC_CMD_CRC_CHK_EN_DIS ((uint16_t)0x0UL) /**< CMD_CRC_CHK_EN_DIS Value */ 308 #define MXC_S_SDHC_CMD_CRC_CHK_EN_DIS (MXC_V_SDHC_CMD_CRC_CHK_EN_DIS << MXC_F_SDHC_CMD_CRC_CHK_EN_POS) /**< CMD_CRC_CHK_EN_DIS Setting */ 309 310 #define MXC_F_SDHC_CMD_IDX_CHK_EN_POS 4 /**< CMD_IDX_CHK_EN Position */ 311 #define MXC_F_SDHC_CMD_IDX_CHK_EN ((uint16_t)(0x1UL << MXC_F_SDHC_CMD_IDX_CHK_EN_POS)) /**< CMD_IDX_CHK_EN Mask */ 312 #define MXC_V_SDHC_CMD_IDX_CHK_EN_EN ((uint16_t)0x1UL) /**< CMD_IDX_CHK_EN_EN Value */ 313 #define MXC_S_SDHC_CMD_IDX_CHK_EN_EN (MXC_V_SDHC_CMD_IDX_CHK_EN_EN << MXC_F_SDHC_CMD_IDX_CHK_EN_POS) /**< CMD_IDX_CHK_EN_EN Setting */ 314 #define MXC_V_SDHC_CMD_IDX_CHK_EN_DIS ((uint16_t)0x0UL) /**< CMD_IDX_CHK_EN_DIS Value */ 315 #define MXC_S_SDHC_CMD_IDX_CHK_EN_DIS (MXC_V_SDHC_CMD_IDX_CHK_EN_DIS << MXC_F_SDHC_CMD_IDX_CHK_EN_POS) /**< CMD_IDX_CHK_EN_DIS Setting */ 316 317 #define MXC_F_SDHC_CMD_DATA_PRES_SEL_POS 5 /**< CMD_DATA_PRES_SEL Position */ 318 #define MXC_F_SDHC_CMD_DATA_PRES_SEL ((uint16_t)(0x1UL << MXC_F_SDHC_CMD_DATA_PRES_SEL_POS)) /**< CMD_DATA_PRES_SEL Mask */ 319 320 #define MXC_F_SDHC_CMD_TYPE_POS 6 /**< CMD_TYPE Position */ 321 #define MXC_F_SDHC_CMD_TYPE ((uint16_t)(0x3UL << MXC_F_SDHC_CMD_TYPE_POS)) /**< CMD_TYPE Mask */ 322 #define MXC_V_SDHC_CMD_TYPE_NORMAL ((uint16_t)0x0UL) /**< CMD_TYPE_NORMAL Value */ 323 #define MXC_S_SDHC_CMD_TYPE_NORMAL (MXC_V_SDHC_CMD_TYPE_NORMAL << MXC_F_SDHC_CMD_TYPE_POS) /**< CMD_TYPE_NORMAL Setting */ 324 #define MXC_V_SDHC_CMD_TYPE_SUSPEND ((uint16_t)0x1UL) /**< CMD_TYPE_SUSPEND Value */ 325 #define MXC_S_SDHC_CMD_TYPE_SUSPEND (MXC_V_SDHC_CMD_TYPE_SUSPEND << MXC_F_SDHC_CMD_TYPE_POS) /**< CMD_TYPE_SUSPEND Setting */ 326 #define MXC_V_SDHC_CMD_TYPE_RESUME ((uint16_t)0x2UL) /**< CMD_TYPE_RESUME Value */ 327 #define MXC_S_SDHC_CMD_TYPE_RESUME (MXC_V_SDHC_CMD_TYPE_RESUME << MXC_F_SDHC_CMD_TYPE_POS) /**< CMD_TYPE_RESUME Setting */ 328 #define MXC_V_SDHC_CMD_TYPE_ABORT ((uint16_t)0x3UL) /**< CMD_TYPE_ABORT Value */ 329 #define MXC_S_SDHC_CMD_TYPE_ABORT (MXC_V_SDHC_CMD_TYPE_ABORT << MXC_F_SDHC_CMD_TYPE_POS) /**< CMD_TYPE_ABORT Setting */ 330 331 #define MXC_F_SDHC_CMD_IDX_POS 8 /**< CMD_IDX Position */ 332 #define MXC_F_SDHC_CMD_IDX ((uint16_t)(0x3FUL << MXC_F_SDHC_CMD_IDX_POS)) /**< CMD_IDX Mask */ 333 334 /**@} end of group SDHC_CMD_Register */ 335 336 /** 337 * @ingroup sdhc_registers 338 * @defgroup SDHC_RESP SDHC_RESP 339 * @brief Response 0 Register 0-15. 340 * @{ 341 */ 342 #define MXC_F_SDHC_RESP_CMD_RESP_POS 0 /**< RESP_CMD_RESP Position */ 343 #define MXC_F_SDHC_RESP_CMD_RESP ((uint16_t)(0xFFFFUL << MXC_F_SDHC_RESP_CMD_RESP_POS)) /**< RESP_CMD_RESP Mask */ 344 345 /**@} end of group SDHC_RESP_Register */ 346 347 /** 348 * @ingroup sdhc_registers 349 * @defgroup SDHC_BUFFER SDHC_BUFFER 350 * @brief Buffer Data Port. 351 * @{ 352 */ 353 #define MXC_F_SDHC_BUFFER_DATA_POS 0 /**< BUFFER_DATA Position */ 354 #define MXC_F_SDHC_BUFFER_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_BUFFER_DATA_POS)) /**< BUFFER_DATA Mask */ 355 356 /**@} end of group SDHC_BUFFER_Register */ 357 358 /** 359 * @ingroup sdhc_registers 360 * @defgroup SDHC_PRESENT SDHC_PRESENT 361 * @brief Present State. 362 * @{ 363 */ 364 #define MXC_F_SDHC_PRESENT_CMD_COMP_POS 0 /**< PRESENT_CMD_COMP Position */ 365 #define MXC_F_SDHC_PRESENT_CMD_COMP ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_CMD_COMP_POS)) /**< PRESENT_CMD_COMP Mask */ 366 367 #define MXC_F_SDHC_PRESENT_DAT_POS 1 /**< PRESENT_DAT Position */ 368 #define MXC_F_SDHC_PRESENT_DAT ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_DAT_POS)) /**< PRESENT_DAT Mask */ 369 370 #define MXC_F_SDHC_PRESENT_DAT_LINE_ACTIVE_POS 2 /**< PRESENT_DAT_LINE_ACTIVE Position */ 371 #define MXC_F_SDHC_PRESENT_DAT_LINE_ACTIVE ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_DAT_LINE_ACTIVE_POS)) /**< PRESENT_DAT_LINE_ACTIVE Mask */ 372 373 #define MXC_F_SDHC_PRESENT_RETUNING_POS 3 /**< PRESENT_RETUNING Position */ 374 #define MXC_F_SDHC_PRESENT_RETUNING ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_RETUNING_POS)) /**< PRESENT_RETUNING Mask */ 375 376 #define MXC_F_SDHC_PRESENT_WRITE_TRANSFER_POS 8 /**< PRESENT_WRITE_TRANSFER Position */ 377 #define MXC_F_SDHC_PRESENT_WRITE_TRANSFER ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_WRITE_TRANSFER_POS)) /**< PRESENT_WRITE_TRANSFER Mask */ 378 379 #define MXC_F_SDHC_PRESENT_READ_TRANSFER_POS 9 /**< PRESENT_READ_TRANSFER Position */ 380 #define MXC_F_SDHC_PRESENT_READ_TRANSFER ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_READ_TRANSFER_POS)) /**< PRESENT_READ_TRANSFER Mask */ 381 382 #define MXC_F_SDHC_PRESENT_BUFFER_WRITE_POS 10 /**< PRESENT_BUFFER_WRITE Position */ 383 #define MXC_F_SDHC_PRESENT_BUFFER_WRITE ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_BUFFER_WRITE_POS)) /**< PRESENT_BUFFER_WRITE Mask */ 384 385 #define MXC_F_SDHC_PRESENT_BUFFER_READ_POS 11 /**< PRESENT_BUFFER_READ Position */ 386 #define MXC_F_SDHC_PRESENT_BUFFER_READ ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_BUFFER_READ_POS)) /**< PRESENT_BUFFER_READ Mask */ 387 388 #define MXC_F_SDHC_PRESENT_CARD_INSERTED_POS 16 /**< PRESENT_CARD_INSERTED Position */ 389 #define MXC_F_SDHC_PRESENT_CARD_INSERTED ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_CARD_INSERTED_POS)) /**< PRESENT_CARD_INSERTED Mask */ 390 391 #define MXC_F_SDHC_PRESENT_CARD_STATE_POS 17 /**< PRESENT_CARD_STATE Position */ 392 #define MXC_F_SDHC_PRESENT_CARD_STATE ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_CARD_STATE_POS)) /**< PRESENT_CARD_STATE Mask */ 393 394 #define MXC_F_SDHC_PRESENT_CARD_DETECT_POS 18 /**< PRESENT_CARD_DETECT Position */ 395 #define MXC_F_SDHC_PRESENT_CARD_DETECT ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_CARD_DETECT_POS)) /**< PRESENT_CARD_DETECT Mask */ 396 397 #define MXC_F_SDHC_PRESENT_WP_POS 19 /**< PRESENT_WP Position */ 398 #define MXC_F_SDHC_PRESENT_WP ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_WP_POS)) /**< PRESENT_WP Mask */ 399 400 #define MXC_F_SDHC_PRESENT_DAT_SIGNAL_LEVEL_POS 20 /**< PRESENT_DAT_SIGNAL_LEVEL Position */ 401 #define MXC_F_SDHC_PRESENT_DAT_SIGNAL_LEVEL ((uint32_t)(0xFUL << MXC_F_SDHC_PRESENT_DAT_SIGNAL_LEVEL_POS)) /**< PRESENT_DAT_SIGNAL_LEVEL Mask */ 402 403 #define MXC_F_SDHC_PRESENT_CMD_SIGNAL_LEVEL_POS 24 /**< PRESENT_CMD_SIGNAL_LEVEL Position */ 404 #define MXC_F_SDHC_PRESENT_CMD_SIGNAL_LEVEL ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_CMD_SIGNAL_LEVEL_POS)) /**< PRESENT_CMD_SIGNAL_LEVEL Mask */ 405 406 /**@} end of group SDHC_PRESENT_Register */ 407 408 /** 409 * @ingroup sdhc_registers 410 * @defgroup SDHC_HOST_CN_1 SDHC_HOST_CN_1 411 * @brief Host Control 1. 412 * @{ 413 */ 414 #define MXC_F_SDHC_HOST_CN_1_LED_CN_POS 0 /**< HOST_CN_1_LED_CN Position */ 415 #define MXC_F_SDHC_HOST_CN_1_LED_CN ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_LED_CN_POS)) /**< HOST_CN_1_LED_CN Mask */ 416 417 #define MXC_F_SDHC_HOST_CN_1_DATA_TRANSFER_WIDTH_POS 1 /**< HOST_CN_1_DATA_TRANSFER_WIDTH Position */ 418 #define MXC_F_SDHC_HOST_CN_1_DATA_TRANSFER_WIDTH ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_DATA_TRANSFER_WIDTH_POS)) /**< HOST_CN_1_DATA_TRANSFER_WIDTH Mask */ 419 420 #define MXC_F_SDHC_HOST_CN_1_HS_EN_POS 2 /**< HOST_CN_1_HS_EN Position */ 421 #define MXC_F_SDHC_HOST_CN_1_HS_EN ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_HS_EN_POS)) /**< HOST_CN_1_HS_EN Mask */ 422 423 #define MXC_F_SDHC_HOST_CN_1_DMA_SELECT_POS 3 /**< HOST_CN_1_DMA_SELECT Position */ 424 #define MXC_F_SDHC_HOST_CN_1_DMA_SELECT ((uint8_t)(0x3UL << MXC_F_SDHC_HOST_CN_1_DMA_SELECT_POS)) /**< HOST_CN_1_DMA_SELECT Mask */ 425 426 #define MXC_F_SDHC_HOST_CN_1_EXT_DATA_TRANSFER_WIDTH_POS 5 /**< HOST_CN_1_EXT_DATA_TRANSFER_WIDTH Position */ 427 #define MXC_F_SDHC_HOST_CN_1_EXT_DATA_TRANSFER_WIDTH ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_EXT_DATA_TRANSFER_WIDTH_POS)) /**< HOST_CN_1_EXT_DATA_TRANSFER_WIDTH Mask */ 428 429 #define MXC_F_SDHC_HOST_CN_1_CARD_DETECT_TEST_POS 6 /**< HOST_CN_1_CARD_DETECT_TEST Position */ 430 #define MXC_F_SDHC_HOST_CN_1_CARD_DETECT_TEST ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_CARD_DETECT_TEST_POS)) /**< HOST_CN_1_CARD_DETECT_TEST Mask */ 431 432 #define MXC_F_SDHC_HOST_CN_1_CARD_DETECT_SIGNAL_POS 7 /**< HOST_CN_1_CARD_DETECT_SIGNAL Position */ 433 #define MXC_F_SDHC_HOST_CN_1_CARD_DETECT_SIGNAL ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_CARD_DETECT_SIGNAL_POS)) /**< HOST_CN_1_CARD_DETECT_SIGNAL Mask */ 434 435 /**@} end of group SDHC_HOST_CN_1_Register */ 436 437 /** 438 * @ingroup sdhc_registers 439 * @defgroup SDHC_PWR SDHC_PWR 440 * @brief Power Control. 441 * @{ 442 */ 443 #define MXC_F_SDHC_PWR_BUS_POWER_POS 0 /**< PWR_BUS_POWER Position */ 444 #define MXC_F_SDHC_PWR_BUS_POWER ((uint8_t)(0x1UL << MXC_F_SDHC_PWR_BUS_POWER_POS)) /**< PWR_BUS_POWER Mask */ 445 446 #define MXC_F_SDHC_PWR_BUS_VOLT_SEL_POS 1 /**< PWR_BUS_VOLT_SEL Position */ 447 #define MXC_F_SDHC_PWR_BUS_VOLT_SEL ((uint8_t)(0x7UL << MXC_F_SDHC_PWR_BUS_VOLT_SEL_POS)) /**< PWR_BUS_VOLT_SEL Mask */ 448 #define MXC_V_SDHC_PWR_BUS_VOLT_SEL_1V8_TYP ((uint8_t)0x5UL) /**< PWR_BUS_VOLT_SEL_1V8_TYP Value */ 449 #define MXC_S_SDHC_PWR_BUS_VOLT_SEL_1V8_TYP (MXC_V_SDHC_PWR_BUS_VOLT_SEL_1V8_TYP << MXC_F_SDHC_PWR_BUS_VOLT_SEL_POS) /**< PWR_BUS_VOLT_SEL_1V8_TYP Setting */ 450 #define MXC_V_SDHC_PWR_BUS_VOLT_SEL_3V_TYP ((uint8_t)0x6UL) /**< PWR_BUS_VOLT_SEL_3V_TYP Value */ 451 #define MXC_S_SDHC_PWR_BUS_VOLT_SEL_3V_TYP (MXC_V_SDHC_PWR_BUS_VOLT_SEL_3V_TYP << MXC_F_SDHC_PWR_BUS_VOLT_SEL_POS) /**< PWR_BUS_VOLT_SEL_3V_TYP Setting */ 452 #define MXC_V_SDHC_PWR_BUS_VOLT_SEL_3V3_TYP ((uint8_t)0x7UL) /**< PWR_BUS_VOLT_SEL_3V3_TYP Value */ 453 #define MXC_S_SDHC_PWR_BUS_VOLT_SEL_3V3_TYP (MXC_V_SDHC_PWR_BUS_VOLT_SEL_3V3_TYP << MXC_F_SDHC_PWR_BUS_VOLT_SEL_POS) /**< PWR_BUS_VOLT_SEL_3V3_TYP Setting */ 454 455 /**@} end of group SDHC_PWR_Register */ 456 457 /** 458 * @ingroup sdhc_registers 459 * @defgroup SDHC_BLK_GAP SDHC_BLK_GAP 460 * @brief Block Gap Control. 461 * @{ 462 */ 463 #define MXC_F_SDHC_BLK_GAP_STOP_POS 0 /**< BLK_GAP_STOP Position */ 464 #define MXC_F_SDHC_BLK_GAP_STOP ((uint8_t)(0x1UL << MXC_F_SDHC_BLK_GAP_STOP_POS)) /**< BLK_GAP_STOP Mask */ 465 466 #define MXC_F_SDHC_BLK_GAP_CONT_POS 1 /**< BLK_GAP_CONT Position */ 467 #define MXC_F_SDHC_BLK_GAP_CONT ((uint8_t)(0x1UL << MXC_F_SDHC_BLK_GAP_CONT_POS)) /**< BLK_GAP_CONT Mask */ 468 469 #define MXC_F_SDHC_BLK_GAP_READ_WAIT_POS 2 /**< BLK_GAP_READ_WAIT Position */ 470 #define MXC_F_SDHC_BLK_GAP_READ_WAIT ((uint8_t)(0x1UL << MXC_F_SDHC_BLK_GAP_READ_WAIT_POS)) /**< BLK_GAP_READ_WAIT Mask */ 471 472 #define MXC_F_SDHC_BLK_GAP_INTR_POS 3 /**< BLK_GAP_INTR Position */ 473 #define MXC_F_SDHC_BLK_GAP_INTR ((uint8_t)(0x1UL << MXC_F_SDHC_BLK_GAP_INTR_POS)) /**< BLK_GAP_INTR Mask */ 474 475 /**@} end of group SDHC_BLK_GAP_Register */ 476 477 /** 478 * @ingroup sdhc_registers 479 * @defgroup SDHC_WAKEUP SDHC_WAKEUP 480 * @brief Wakeup Control. 481 * @{ 482 */ 483 #define MXC_F_SDHC_WAKEUP_CARD_INT_POS 0 /**< WAKEUP_CARD_INT Position */ 484 #define MXC_F_SDHC_WAKEUP_CARD_INT ((uint8_t)(0x1UL << MXC_F_SDHC_WAKEUP_CARD_INT_POS)) /**< WAKEUP_CARD_INT Mask */ 485 486 #define MXC_F_SDHC_WAKEUP_CARD_INS_POS 1 /**< WAKEUP_CARD_INS Position */ 487 #define MXC_F_SDHC_WAKEUP_CARD_INS ((uint8_t)(0x1UL << MXC_F_SDHC_WAKEUP_CARD_INS_POS)) /**< WAKEUP_CARD_INS Mask */ 488 489 #define MXC_F_SDHC_WAKEUP_CARD_REM_POS 2 /**< WAKEUP_CARD_REM Position */ 490 #define MXC_F_SDHC_WAKEUP_CARD_REM ((uint8_t)(0x1UL << MXC_F_SDHC_WAKEUP_CARD_REM_POS)) /**< WAKEUP_CARD_REM Mask */ 491 492 /**@} end of group SDHC_WAKEUP_Register */ 493 494 /** 495 * @ingroup sdhc_registers 496 * @defgroup SDHC_CLK_CN SDHC_CLK_CN 497 * @brief Clock Control. 498 * @{ 499 */ 500 #define MXC_F_SDHC_CLK_CN_INTERNAL_CLK_EN_POS 0 /**< CLK_CN_INTERNAL_CLK_EN Position */ 501 #define MXC_F_SDHC_CLK_CN_INTERNAL_CLK_EN ((uint16_t)(0x1UL << MXC_F_SDHC_CLK_CN_INTERNAL_CLK_EN_POS)) /**< CLK_CN_INTERNAL_CLK_EN Mask */ 502 503 #define MXC_F_SDHC_CLK_CN_INTERNAL_CLK_STABLE_POS 1 /**< CLK_CN_INTERNAL_CLK_STABLE Position */ 504 #define MXC_F_SDHC_CLK_CN_INTERNAL_CLK_STABLE ((uint16_t)(0x1UL << MXC_F_SDHC_CLK_CN_INTERNAL_CLK_STABLE_POS)) /**< CLK_CN_INTERNAL_CLK_STABLE Mask */ 505 506 #define MXC_F_SDHC_CLK_CN_SD_CLK_EN_POS 2 /**< CLK_CN_SD_CLK_EN Position */ 507 #define MXC_F_SDHC_CLK_CN_SD_CLK_EN ((uint16_t)(0x1UL << MXC_F_SDHC_CLK_CN_SD_CLK_EN_POS)) /**< CLK_CN_SD_CLK_EN Mask */ 508 509 #define MXC_F_SDHC_CLK_CN_CLK_GEN_SEL_POS 5 /**< CLK_CN_CLK_GEN_SEL Position */ 510 #define MXC_F_SDHC_CLK_CN_CLK_GEN_SEL ((uint16_t)(0x1UL << MXC_F_SDHC_CLK_CN_CLK_GEN_SEL_POS)) /**< CLK_CN_CLK_GEN_SEL Mask */ 511 512 #define MXC_F_SDHC_CLK_CN_UPPER_SDCLK_FREQ_SEL_POS 6 /**< CLK_CN_UPPER_SDCLK_FREQ_SEL Position */ 513 #define MXC_F_SDHC_CLK_CN_UPPER_SDCLK_FREQ_SEL ((uint16_t)(0x3UL << MXC_F_SDHC_CLK_CN_UPPER_SDCLK_FREQ_SEL_POS)) /**< CLK_CN_UPPER_SDCLK_FREQ_SEL Mask */ 514 515 #define MXC_F_SDHC_CLK_CN_SDCLK_FREQ_SEL_POS 8 /**< CLK_CN_SDCLK_FREQ_SEL Position */ 516 #define MXC_F_SDHC_CLK_CN_SDCLK_FREQ_SEL ((uint16_t)(0xFFUL << MXC_F_SDHC_CLK_CN_SDCLK_FREQ_SEL_POS)) /**< CLK_CN_SDCLK_FREQ_SEL Mask */ 517 518 /**@} end of group SDHC_CLK_CN_Register */ 519 520 /** 521 * @ingroup sdhc_registers 522 * @defgroup SDHC_TO SDHC_TO 523 * @brief Timeout Control. 524 * @{ 525 */ 526 #define MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS 0 /**< TO_DATA_COUNT_VALUE Position */ 527 #define MXC_F_SDHC_TO_DATA_COUNT_VALUE ((uint8_t)(0xFUL << MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS)) /**< TO_DATA_COUNT_VALUE Mask */ 528 #define MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW13 ((uint8_t)0x0UL) /**< TO_DATA_COUNT_VALUE_2POW13 Value */ 529 #define MXC_S_SDHC_TO_DATA_COUNT_VALUE_2POW13 (MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW13 << MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS) /**< TO_DATA_COUNT_VALUE_2POW13 Setting */ 530 #define MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW14 ((uint8_t)0x1UL) /**< TO_DATA_COUNT_VALUE_2POW14 Value */ 531 #define MXC_S_SDHC_TO_DATA_COUNT_VALUE_2POW14 (MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW14 << MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS) /**< TO_DATA_COUNT_VALUE_2POW14 Setting */ 532 #define MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW15 ((uint8_t)0x2UL) /**< TO_DATA_COUNT_VALUE_2POW15 Value */ 533 #define MXC_S_SDHC_TO_DATA_COUNT_VALUE_2POW15 (MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW15 << MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS) /**< TO_DATA_COUNT_VALUE_2POW15 Setting */ 534 #define MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW16 ((uint8_t)0x3UL) /**< TO_DATA_COUNT_VALUE_2POW16 Value */ 535 #define MXC_S_SDHC_TO_DATA_COUNT_VALUE_2POW16 (MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW16 << MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS) /**< TO_DATA_COUNT_VALUE_2POW16 Setting */ 536 #define MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW17 ((uint8_t)0x4UL) /**< TO_DATA_COUNT_VALUE_2POW17 Value */ 537 #define MXC_S_SDHC_TO_DATA_COUNT_VALUE_2POW17 (MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW17 << MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS) /**< TO_DATA_COUNT_VALUE_2POW17 Setting */ 538 #define MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW18 ((uint8_t)0x5UL) /**< TO_DATA_COUNT_VALUE_2POW18 Value */ 539 #define MXC_S_SDHC_TO_DATA_COUNT_VALUE_2POW18 (MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW18 << MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS) /**< TO_DATA_COUNT_VALUE_2POW18 Setting */ 540 #define MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW19 ((uint8_t)0x6UL) /**< TO_DATA_COUNT_VALUE_2POW19 Value */ 541 #define MXC_S_SDHC_TO_DATA_COUNT_VALUE_2POW19 (MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW19 << MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS) /**< TO_DATA_COUNT_VALUE_2POW19 Setting */ 542 #define MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW20 ((uint8_t)0x7UL) /**< TO_DATA_COUNT_VALUE_2POW20 Value */ 543 #define MXC_S_SDHC_TO_DATA_COUNT_VALUE_2POW20 (MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW20 << MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS) /**< TO_DATA_COUNT_VALUE_2POW20 Setting */ 544 #define MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW21 ((uint8_t)0x8UL) /**< TO_DATA_COUNT_VALUE_2POW21 Value */ 545 #define MXC_S_SDHC_TO_DATA_COUNT_VALUE_2POW21 (MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW21 << MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS) /**< TO_DATA_COUNT_VALUE_2POW21 Setting */ 546 #define MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW22 ((uint8_t)0x9UL) /**< TO_DATA_COUNT_VALUE_2POW22 Value */ 547 #define MXC_S_SDHC_TO_DATA_COUNT_VALUE_2POW22 (MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW22 << MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS) /**< TO_DATA_COUNT_VALUE_2POW22 Setting */ 548 #define MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW23 ((uint8_t)0xAUL) /**< TO_DATA_COUNT_VALUE_2POW23 Value */ 549 #define MXC_S_SDHC_TO_DATA_COUNT_VALUE_2POW23 (MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW23 << MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS) /**< TO_DATA_COUNT_VALUE_2POW23 Setting */ 550 #define MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW24 ((uint8_t)0xBUL) /**< TO_DATA_COUNT_VALUE_2POW24 Value */ 551 #define MXC_S_SDHC_TO_DATA_COUNT_VALUE_2POW24 (MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW24 << MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS) /**< TO_DATA_COUNT_VALUE_2POW24 Setting */ 552 #define MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW25 ((uint8_t)0xCUL) /**< TO_DATA_COUNT_VALUE_2POW25 Value */ 553 #define MXC_S_SDHC_TO_DATA_COUNT_VALUE_2POW25 (MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW25 << MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS) /**< TO_DATA_COUNT_VALUE_2POW25 Setting */ 554 #define MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW26 ((uint8_t)0xDUL) /**< TO_DATA_COUNT_VALUE_2POW26 Value */ 555 #define MXC_S_SDHC_TO_DATA_COUNT_VALUE_2POW26 (MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW26 << MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS) /**< TO_DATA_COUNT_VALUE_2POW26 Setting */ 556 #define MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW27 ((uint8_t)0xEUL) /**< TO_DATA_COUNT_VALUE_2POW27 Value */ 557 #define MXC_S_SDHC_TO_DATA_COUNT_VALUE_2POW27 (MXC_V_SDHC_TO_DATA_COUNT_VALUE_2POW27 << MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS) /**< TO_DATA_COUNT_VALUE_2POW27 Setting */ 558 559 /**@} end of group SDHC_TO_Register */ 560 561 /** 562 * @ingroup sdhc_registers 563 * @defgroup SDHC_SW_RESET SDHC_SW_RESET 564 * @brief Software Reset. 565 * @{ 566 */ 567 #define MXC_F_SDHC_SW_RESET_RESET_ALL_POS 0 /**< SW_RESET_RESET_ALL Position */ 568 #define MXC_F_SDHC_SW_RESET_RESET_ALL ((uint8_t)(0x1UL << MXC_F_SDHC_SW_RESET_RESET_ALL_POS)) /**< SW_RESET_RESET_ALL Mask */ 569 570 #define MXC_F_SDHC_SW_RESET_RESET_CMD_POS 1 /**< SW_RESET_RESET_CMD Position */ 571 #define MXC_F_SDHC_SW_RESET_RESET_CMD ((uint8_t)(0x1UL << MXC_F_SDHC_SW_RESET_RESET_CMD_POS)) /**< SW_RESET_RESET_CMD Mask */ 572 573 #define MXC_F_SDHC_SW_RESET_RESET_DAT_POS 2 /**< SW_RESET_RESET_DAT Position */ 574 #define MXC_F_SDHC_SW_RESET_RESET_DAT ((uint8_t)(0x1UL << MXC_F_SDHC_SW_RESET_RESET_DAT_POS)) /**< SW_RESET_RESET_DAT Mask */ 575 576 /**@} end of group SDHC_SW_RESET_Register */ 577 578 /** 579 * @ingroup sdhc_registers 580 * @defgroup SDHC_INT_STAT SDHC_INT_STAT 581 * @brief Normal Interrupt Status. 582 * @{ 583 */ 584 #define MXC_F_SDHC_INT_STAT_CMD_COMP_POS 0 /**< INT_STAT_CMD_COMP Position */ 585 #define MXC_F_SDHC_INT_STAT_CMD_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_CMD_COMP_POS)) /**< INT_STAT_CMD_COMP Mask */ 586 587 #define MXC_F_SDHC_INT_STAT_TRANS_COMP_POS 1 /**< INT_STAT_TRANS_COMP Position */ 588 #define MXC_F_SDHC_INT_STAT_TRANS_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_TRANS_COMP_POS)) /**< INT_STAT_TRANS_COMP Mask */ 589 590 #define MXC_F_SDHC_INT_STAT_BLK_GAP_EVENT_POS 2 /**< INT_STAT_BLK_GAP_EVENT Position */ 591 #define MXC_F_SDHC_INT_STAT_BLK_GAP_EVENT ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_BLK_GAP_EVENT_POS)) /**< INT_STAT_BLK_GAP_EVENT Mask */ 592 593 #define MXC_F_SDHC_INT_STAT_DMA_POS 3 /**< INT_STAT_DMA Position */ 594 #define MXC_F_SDHC_INT_STAT_DMA ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_DMA_POS)) /**< INT_STAT_DMA Mask */ 595 596 #define MXC_F_SDHC_INT_STAT_BUFF_WR_READY_POS 4 /**< INT_STAT_BUFF_WR_READY Position */ 597 #define MXC_F_SDHC_INT_STAT_BUFF_WR_READY ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_BUFF_WR_READY_POS)) /**< INT_STAT_BUFF_WR_READY Mask */ 598 599 #define MXC_F_SDHC_INT_STAT_BUFF_RD_READY_POS 5 /**< INT_STAT_BUFF_RD_READY Position */ 600 #define MXC_F_SDHC_INT_STAT_BUFF_RD_READY ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_BUFF_RD_READY_POS)) /**< INT_STAT_BUFF_RD_READY Mask */ 601 602 #define MXC_F_SDHC_INT_STAT_CARD_INSERTION_POS 6 /**< INT_STAT_CARD_INSERTION Position */ 603 #define MXC_F_SDHC_INT_STAT_CARD_INSERTION ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_CARD_INSERTION_POS)) /**< INT_STAT_CARD_INSERTION Mask */ 604 605 #define MXC_F_SDHC_INT_STAT_CARD_REMOVAL_POS 7 /**< INT_STAT_CARD_REMOVAL Position */ 606 #define MXC_F_SDHC_INT_STAT_CARD_REMOVAL ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_CARD_REMOVAL_POS)) /**< INT_STAT_CARD_REMOVAL Mask */ 607 608 #define MXC_F_SDHC_INT_STAT_CARD_INTR_POS 8 /**< INT_STAT_CARD_INTR Position */ 609 #define MXC_F_SDHC_INT_STAT_CARD_INTR ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_CARD_INTR_POS)) /**< INT_STAT_CARD_INTR Mask */ 610 611 #define MXC_F_SDHC_INT_STAT_RETUNING_POS 12 /**< INT_STAT_RETUNING Position */ 612 #define MXC_F_SDHC_INT_STAT_RETUNING ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_RETUNING_POS)) /**< INT_STAT_RETUNING Mask */ 613 614 #define MXC_F_SDHC_INT_STAT_ERR_INTR_POS 15 /**< INT_STAT_ERR_INTR Position */ 615 #define MXC_F_SDHC_INT_STAT_ERR_INTR ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_ERR_INTR_POS)) /**< INT_STAT_ERR_INTR Mask */ 616 617 /**@} end of group SDHC_INT_STAT_Register */ 618 619 /** 620 * @ingroup sdhc_registers 621 * @defgroup SDHC_ER_INT_STAT SDHC_ER_INT_STAT 622 * @brief Error Interrupt Status. 623 * @{ 624 */ 625 #define MXC_F_SDHC_ER_INT_STAT_CMD_TO_POS 0 /**< ER_INT_STAT_CMD_TO Position */ 626 #define MXC_F_SDHC_ER_INT_STAT_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_CMD_TO_POS)) /**< ER_INT_STAT_CMD_TO Mask */ 627 628 #define MXC_F_SDHC_ER_INT_STAT_CMD_CRC_POS 1 /**< ER_INT_STAT_CMD_CRC Position */ 629 #define MXC_F_SDHC_ER_INT_STAT_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_CMD_CRC_POS)) /**< ER_INT_STAT_CMD_CRC Mask */ 630 631 #define MXC_F_SDHC_ER_INT_STAT_CMD_END_BIT_POS 2 /**< ER_INT_STAT_CMD_END_BIT Position */ 632 #define MXC_F_SDHC_ER_INT_STAT_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_CMD_END_BIT_POS)) /**< ER_INT_STAT_CMD_END_BIT Mask */ 633 634 #define MXC_F_SDHC_ER_INT_STAT_CMD_IDX_POS 3 /**< ER_INT_STAT_CMD_IDX Position */ 635 #define MXC_F_SDHC_ER_INT_STAT_CMD_IDX ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_CMD_IDX_POS)) /**< ER_INT_STAT_CMD_IDX Mask */ 636 637 #define MXC_F_SDHC_ER_INT_STAT_DATA_TO_POS 4 /**< ER_INT_STAT_DATA_TO Position */ 638 #define MXC_F_SDHC_ER_INT_STAT_DATA_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_DATA_TO_POS)) /**< ER_INT_STAT_DATA_TO Mask */ 639 640 #define MXC_F_SDHC_ER_INT_STAT_DATA_CRC_POS 5 /**< ER_INT_STAT_DATA_CRC Position */ 641 #define MXC_F_SDHC_ER_INT_STAT_DATA_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_DATA_CRC_POS)) /**< ER_INT_STAT_DATA_CRC Mask */ 642 643 #define MXC_F_SDHC_ER_INT_STAT_DATA_END_BIT_POS 6 /**< ER_INT_STAT_DATA_END_BIT Position */ 644 #define MXC_F_SDHC_ER_INT_STAT_DATA_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_DATA_END_BIT_POS)) /**< ER_INT_STAT_DATA_END_BIT Mask */ 645 646 #define MXC_F_SDHC_ER_INT_STAT_CURRENT_LIMIT_POS 7 /**< ER_INT_STAT_CURRENT_LIMIT Position */ 647 #define MXC_F_SDHC_ER_INT_STAT_CURRENT_LIMIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_CURRENT_LIMIT_POS)) /**< ER_INT_STAT_CURRENT_LIMIT Mask */ 648 649 #define MXC_F_SDHC_ER_INT_STAT_AUTO_CMD_12_POS 8 /**< ER_INT_STAT_AUTO_CMD_12 Position */ 650 #define MXC_F_SDHC_ER_INT_STAT_AUTO_CMD_12 ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_AUTO_CMD_12_POS)) /**< ER_INT_STAT_AUTO_CMD_12 Mask */ 651 652 #define MXC_F_SDHC_ER_INT_STAT_ADMA_POS 9 /**< ER_INT_STAT_ADMA Position */ 653 #define MXC_F_SDHC_ER_INT_STAT_ADMA ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_ADMA_POS)) /**< ER_INT_STAT_ADMA Mask */ 654 655 #define MXC_F_SDHC_ER_INT_STAT_DMA_POS 12 /**< ER_INT_STAT_DMA Position */ 656 #define MXC_F_SDHC_ER_INT_STAT_DMA ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_DMA_POS)) /**< ER_INT_STAT_DMA Mask */ 657 658 /**@} end of group SDHC_ER_INT_STAT_Register */ 659 660 /** 661 * @ingroup sdhc_registers 662 * @defgroup SDHC_INT_EN SDHC_INT_EN 663 * @brief Normal Interrupt Status Enable. 664 * @{ 665 */ 666 #define MXC_F_SDHC_INT_EN_CMD_COMP_POS 0 /**< INT_EN_CMD_COMP Position */ 667 #define MXC_F_SDHC_INT_EN_CMD_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_CMD_COMP_POS)) /**< INT_EN_CMD_COMP Mask */ 668 669 #define MXC_F_SDHC_INT_EN_TRANS_COMP_POS 1 /**< INT_EN_TRANS_COMP Position */ 670 #define MXC_F_SDHC_INT_EN_TRANS_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_TRANS_COMP_POS)) /**< INT_EN_TRANS_COMP Mask */ 671 672 #define MXC_F_SDHC_INT_EN_BLK_GAP_POS 2 /**< INT_EN_BLK_GAP Position */ 673 #define MXC_F_SDHC_INT_EN_BLK_GAP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_BLK_GAP_POS)) /**< INT_EN_BLK_GAP Mask */ 674 675 #define MXC_F_SDHC_INT_EN_DMA_POS 3 /**< INT_EN_DMA Position */ 676 #define MXC_F_SDHC_INT_EN_DMA ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_DMA_POS)) /**< INT_EN_DMA Mask */ 677 678 #define MXC_F_SDHC_INT_EN_BUFFER_WR_POS 4 /**< INT_EN_BUFFER_WR Position */ 679 #define MXC_F_SDHC_INT_EN_BUFFER_WR ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_BUFFER_WR_POS)) /**< INT_EN_BUFFER_WR Mask */ 680 681 #define MXC_F_SDHC_INT_EN_BUFFER_RD_POS 5 /**< INT_EN_BUFFER_RD Position */ 682 #define MXC_F_SDHC_INT_EN_BUFFER_RD ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_BUFFER_RD_POS)) /**< INT_EN_BUFFER_RD Mask */ 683 684 #define MXC_F_SDHC_INT_EN_CARD_INSERT_POS 6 /**< INT_EN_CARD_INSERT Position */ 685 #define MXC_F_SDHC_INT_EN_CARD_INSERT ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_CARD_INSERT_POS)) /**< INT_EN_CARD_INSERT Mask */ 686 687 #define MXC_F_SDHC_INT_EN_CARD_REMOVAL_POS 7 /**< INT_EN_CARD_REMOVAL Position */ 688 #define MXC_F_SDHC_INT_EN_CARD_REMOVAL ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_CARD_REMOVAL_POS)) /**< INT_EN_CARD_REMOVAL Mask */ 689 690 #define MXC_F_SDHC_INT_EN_CARD_INT_POS 8 /**< INT_EN_CARD_INT Position */ 691 #define MXC_F_SDHC_INT_EN_CARD_INT ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_CARD_INT_POS)) /**< INT_EN_CARD_INT Mask */ 692 693 #define MXC_F_SDHC_INT_EN_RETUNING_POS 12 /**< INT_EN_RETUNING Position */ 694 #define MXC_F_SDHC_INT_EN_RETUNING ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_RETUNING_POS)) /**< INT_EN_RETUNING Mask */ 695 696 /**@} end of group SDHC_INT_EN_Register */ 697 698 /** 699 * @ingroup sdhc_registers 700 * @defgroup SDHC_ER_INT_EN SDHC_ER_INT_EN 701 * @brief Error Interrupt Status Enable. 702 * @{ 703 */ 704 #define MXC_F_SDHC_ER_INT_EN_CMD_TO_POS 0 /**< ER_INT_EN_CMD_TO Position */ 705 #define MXC_F_SDHC_ER_INT_EN_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_CMD_TO_POS)) /**< ER_INT_EN_CMD_TO Mask */ 706 707 #define MXC_F_SDHC_ER_INT_EN_CMD_CRC_POS 1 /**< ER_INT_EN_CMD_CRC Position */ 708 #define MXC_F_SDHC_ER_INT_EN_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_CMD_CRC_POS)) /**< ER_INT_EN_CMD_CRC Mask */ 709 710 #define MXC_F_SDHC_ER_INT_EN_CMD_END_BIT_POS 2 /**< ER_INT_EN_CMD_END_BIT Position */ 711 #define MXC_F_SDHC_ER_INT_EN_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_CMD_END_BIT_POS)) /**< ER_INT_EN_CMD_END_BIT Mask */ 712 713 #define MXC_F_SDHC_ER_INT_EN_CMD_IDX_POS 3 /**< ER_INT_EN_CMD_IDX Position */ 714 #define MXC_F_SDHC_ER_INT_EN_CMD_IDX ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_CMD_IDX_POS)) /**< ER_INT_EN_CMD_IDX Mask */ 715 716 #define MXC_F_SDHC_ER_INT_EN_DATA_TO_POS 4 /**< ER_INT_EN_DATA_TO Position */ 717 #define MXC_F_SDHC_ER_INT_EN_DATA_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_DATA_TO_POS)) /**< ER_INT_EN_DATA_TO Mask */ 718 719 #define MXC_F_SDHC_ER_INT_EN_DATA_CRC_POS 5 /**< ER_INT_EN_DATA_CRC Position */ 720 #define MXC_F_SDHC_ER_INT_EN_DATA_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_DATA_CRC_POS)) /**< ER_INT_EN_DATA_CRC Mask */ 721 722 #define MXC_F_SDHC_ER_INT_EN_DATA_END_BIT_POS 6 /**< ER_INT_EN_DATA_END_BIT Position */ 723 #define MXC_F_SDHC_ER_INT_EN_DATA_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_DATA_END_BIT_POS)) /**< ER_INT_EN_DATA_END_BIT Mask */ 724 725 #define MXC_F_SDHC_ER_INT_EN_AUTO_CMD_12_POS 8 /**< ER_INT_EN_AUTO_CMD_12 Position */ 726 #define MXC_F_SDHC_ER_INT_EN_AUTO_CMD_12 ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_AUTO_CMD_12_POS)) /**< ER_INT_EN_AUTO_CMD_12 Mask */ 727 728 #define MXC_F_SDHC_ER_INT_EN_ADMA_POS 9 /**< ER_INT_EN_ADMA Position */ 729 #define MXC_F_SDHC_ER_INT_EN_ADMA ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_ADMA_POS)) /**< ER_INT_EN_ADMA Mask */ 730 731 #define MXC_F_SDHC_ER_INT_EN_TUNING_POS 10 /**< ER_INT_EN_TUNING Position */ 732 #define MXC_F_SDHC_ER_INT_EN_TUNING ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_TUNING_POS)) /**< ER_INT_EN_TUNING Mask */ 733 734 #define MXC_F_SDHC_ER_INT_EN_VENDOR_POS 12 /**< ER_INT_EN_VENDOR Position */ 735 #define MXC_F_SDHC_ER_INT_EN_VENDOR ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_VENDOR_POS)) /**< ER_INT_EN_VENDOR Mask */ 736 737 /**@} end of group SDHC_ER_INT_EN_Register */ 738 739 /** 740 * @ingroup sdhc_registers 741 * @defgroup SDHC_INT_SIGNAL SDHC_INT_SIGNAL 742 * @brief Normal Interrupt Signal Enable. 743 * @{ 744 */ 745 #define MXC_F_SDHC_INT_SIGNAL_CMD_COMP_POS 0 /**< INT_SIGNAL_CMD_COMP Position */ 746 #define MXC_F_SDHC_INT_SIGNAL_CMD_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_CMD_COMP_POS)) /**< INT_SIGNAL_CMD_COMP Mask */ 747 748 #define MXC_F_SDHC_INT_SIGNAL_TRANS_COMP_POS 1 /**< INT_SIGNAL_TRANS_COMP Position */ 749 #define MXC_F_SDHC_INT_SIGNAL_TRANS_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_TRANS_COMP_POS)) /**< INT_SIGNAL_TRANS_COMP Mask */ 750 751 #define MXC_F_SDHC_INT_SIGNAL_BLK_GAP_POS 2 /**< INT_SIGNAL_BLK_GAP Position */ 752 #define MXC_F_SDHC_INT_SIGNAL_BLK_GAP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_BLK_GAP_POS)) /**< INT_SIGNAL_BLK_GAP Mask */ 753 754 #define MXC_F_SDHC_INT_SIGNAL_DMA_POS 3 /**< INT_SIGNAL_DMA Position */ 755 #define MXC_F_SDHC_INT_SIGNAL_DMA ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_DMA_POS)) /**< INT_SIGNAL_DMA Mask */ 756 757 #define MXC_F_SDHC_INT_SIGNAL_BUFFER_WR_POS 4 /**< INT_SIGNAL_BUFFER_WR Position */ 758 #define MXC_F_SDHC_INT_SIGNAL_BUFFER_WR ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_BUFFER_WR_POS)) /**< INT_SIGNAL_BUFFER_WR Mask */ 759 760 #define MXC_F_SDHC_INT_SIGNAL_BUFFER_RD_POS 5 /**< INT_SIGNAL_BUFFER_RD Position */ 761 #define MXC_F_SDHC_INT_SIGNAL_BUFFER_RD ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_BUFFER_RD_POS)) /**< INT_SIGNAL_BUFFER_RD Mask */ 762 763 #define MXC_F_SDHC_INT_SIGNAL_CARD_INSERT_POS 6 /**< INT_SIGNAL_CARD_INSERT Position */ 764 #define MXC_F_SDHC_INT_SIGNAL_CARD_INSERT ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_CARD_INSERT_POS)) /**< INT_SIGNAL_CARD_INSERT Mask */ 765 766 #define MXC_F_SDHC_INT_SIGNAL_CARD_REMOVAL_POS 7 /**< INT_SIGNAL_CARD_REMOVAL Position */ 767 #define MXC_F_SDHC_INT_SIGNAL_CARD_REMOVAL ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_CARD_REMOVAL_POS)) /**< INT_SIGNAL_CARD_REMOVAL Mask */ 768 769 #define MXC_F_SDHC_INT_SIGNAL_CARD_INT_POS 8 /**< INT_SIGNAL_CARD_INT Position */ 770 #define MXC_F_SDHC_INT_SIGNAL_CARD_INT ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_CARD_INT_POS)) /**< INT_SIGNAL_CARD_INT Mask */ 771 772 #define MXC_F_SDHC_INT_SIGNAL_RETUNING_POS 12 /**< INT_SIGNAL_RETUNING Position */ 773 #define MXC_F_SDHC_INT_SIGNAL_RETUNING ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_RETUNING_POS)) /**< INT_SIGNAL_RETUNING Mask */ 774 775 /**@} end of group SDHC_INT_SIGNAL_Register */ 776 777 /** 778 * @ingroup sdhc_registers 779 * @defgroup SDHC_ER_INT_SIGNAL SDHC_ER_INT_SIGNAL 780 * @brief Error Interrupt Signal Enable. 781 * @{ 782 */ 783 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_TO_POS 0 /**< ER_INT_SIGNAL_CMD_TO Position */ 784 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_CMD_TO_POS)) /**< ER_INT_SIGNAL_CMD_TO Mask */ 785 786 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_CRC_POS 1 /**< ER_INT_SIGNAL_CMD_CRC Position */ 787 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_CMD_CRC_POS)) /**< ER_INT_SIGNAL_CMD_CRC Mask */ 788 789 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_END_BIT_POS 2 /**< ER_INT_SIGNAL_CMD_END_BIT Position */ 790 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_CMD_END_BIT_POS)) /**< ER_INT_SIGNAL_CMD_END_BIT Mask */ 791 792 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_IDX_POS 3 /**< ER_INT_SIGNAL_CMD_IDX Position */ 793 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_IDX ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_CMD_IDX_POS)) /**< ER_INT_SIGNAL_CMD_IDX Mask */ 794 795 #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_TO_POS 4 /**< ER_INT_SIGNAL_DATA_TO Position */ 796 #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_DATA_TO_POS)) /**< ER_INT_SIGNAL_DATA_TO Mask */ 797 798 #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_CRC_POS 5 /**< ER_INT_SIGNAL_DATA_CRC Position */ 799 #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_DATA_CRC_POS)) /**< ER_INT_SIGNAL_DATA_CRC Mask */ 800 801 #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_END_BIT_POS 6 /**< ER_INT_SIGNAL_DATA_END_BIT Position */ 802 #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_DATA_END_BIT_POS)) /**< ER_INT_SIGNAL_DATA_END_BIT Mask */ 803 804 #define MXC_F_SDHC_ER_INT_SIGNAL_CURRENT_LIMIT_POS 7 /**< ER_INT_SIGNAL_CURRENT_LIMIT Position */ 805 #define MXC_F_SDHC_ER_INT_SIGNAL_CURRENT_LIMIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_CURRENT_LIMIT_POS)) /**< ER_INT_SIGNAL_CURRENT_LIMIT Mask */ 806 807 #define MXC_F_SDHC_ER_INT_SIGNAL_AUTO_CMD_12_POS 8 /**< ER_INT_SIGNAL_AUTO_CMD_12 Position */ 808 #define MXC_F_SDHC_ER_INT_SIGNAL_AUTO_CMD_12 ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_AUTO_CMD_12_POS)) /**< ER_INT_SIGNAL_AUTO_CMD_12 Mask */ 809 810 #define MXC_F_SDHC_ER_INT_SIGNAL_ADMA_POS 9 /**< ER_INT_SIGNAL_ADMA Position */ 811 #define MXC_F_SDHC_ER_INT_SIGNAL_ADMA ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_ADMA_POS)) /**< ER_INT_SIGNAL_ADMA Mask */ 812 813 #define MXC_F_SDHC_ER_INT_SIGNAL_TUNING_POS 10 /**< ER_INT_SIGNAL_TUNING Position */ 814 #define MXC_F_SDHC_ER_INT_SIGNAL_TUNING ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_TUNING_POS)) /**< ER_INT_SIGNAL_TUNING Mask */ 815 816 #define MXC_F_SDHC_ER_INT_SIGNAL_TAR_RESP_POS 12 /**< ER_INT_SIGNAL_TAR_RESP Position */ 817 #define MXC_F_SDHC_ER_INT_SIGNAL_TAR_RESP ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_TAR_RESP_POS)) /**< ER_INT_SIGNAL_TAR_RESP Mask */ 818 819 /**@} end of group SDHC_ER_INT_SIGNAL_Register */ 820 821 /** 822 * @ingroup sdhc_registers 823 * @defgroup SDHC_AUTO_CMD_ER SDHC_AUTO_CMD_ER 824 * @brief Auto CMD Error Status. 825 * @{ 826 */ 827 #define MXC_F_SDHC_AUTO_CMD_ER_NOT_EXCUTED_POS 0 /**< AUTO_CMD_ER_NOT_EXCUTED Position */ 828 #define MXC_F_SDHC_AUTO_CMD_ER_NOT_EXCUTED ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_NOT_EXCUTED_POS)) /**< AUTO_CMD_ER_NOT_EXCUTED Mask */ 829 830 #define MXC_F_SDHC_AUTO_CMD_ER_TO_POS 1 /**< AUTO_CMD_ER_TO Position */ 831 #define MXC_F_SDHC_AUTO_CMD_ER_TO ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_TO_POS)) /**< AUTO_CMD_ER_TO Mask */ 832 833 #define MXC_F_SDHC_AUTO_CMD_ER_CRC_POS 2 /**< AUTO_CMD_ER_CRC Position */ 834 #define MXC_F_SDHC_AUTO_CMD_ER_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_CRC_POS)) /**< AUTO_CMD_ER_CRC Mask */ 835 836 #define MXC_F_SDHC_AUTO_CMD_ER_END_BIT_POS 3 /**< AUTO_CMD_ER_END_BIT Position */ 837 #define MXC_F_SDHC_AUTO_CMD_ER_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_END_BIT_POS)) /**< AUTO_CMD_ER_END_BIT Mask */ 838 839 #define MXC_F_SDHC_AUTO_CMD_ER_INDEX_POS 4 /**< AUTO_CMD_ER_INDEX Position */ 840 #define MXC_F_SDHC_AUTO_CMD_ER_INDEX ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_INDEX_POS)) /**< AUTO_CMD_ER_INDEX Mask */ 841 842 #define MXC_F_SDHC_AUTO_CMD_ER_NOT_ISSUED_POS 7 /**< AUTO_CMD_ER_NOT_ISSUED Position */ 843 #define MXC_F_SDHC_AUTO_CMD_ER_NOT_ISSUED ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_NOT_ISSUED_POS)) /**< AUTO_CMD_ER_NOT_ISSUED Mask */ 844 845 /**@} end of group SDHC_AUTO_CMD_ER_Register */ 846 847 /** 848 * @ingroup sdhc_registers 849 * @defgroup SDHC_HOST_CN_2 SDHC_HOST_CN_2 850 * @brief Host Control 2. 851 * @{ 852 */ 853 #define MXC_F_SDHC_HOST_CN_2_UHS_POS 0 /**< HOST_CN_2_UHS Position */ 854 #define MXC_F_SDHC_HOST_CN_2_UHS ((uint16_t)(0x7UL << MXC_F_SDHC_HOST_CN_2_UHS_POS)) /**< HOST_CN_2_UHS Mask */ 855 #define MXC_V_SDHC_HOST_CN_2_UHS_SDR12 ((uint16_t)0x0UL) /**< HOST_CN_2_UHS_SDR12 Value */ 856 #define MXC_S_SDHC_HOST_CN_2_UHS_SDR12 (MXC_V_SDHC_HOST_CN_2_UHS_SDR12 << MXC_F_SDHC_HOST_CN_2_UHS_POS) /**< HOST_CN_2_UHS_SDR12 Setting */ 857 #define MXC_V_SDHC_HOST_CN_2_UHS_SDR25 ((uint16_t)0x1UL) /**< HOST_CN_2_UHS_SDR25 Value */ 858 #define MXC_S_SDHC_HOST_CN_2_UHS_SDR25 (MXC_V_SDHC_HOST_CN_2_UHS_SDR25 << MXC_F_SDHC_HOST_CN_2_UHS_POS) /**< HOST_CN_2_UHS_SDR25 Setting */ 859 #define MXC_V_SDHC_HOST_CN_2_UHS_SDR50 ((uint16_t)0x2UL) /**< HOST_CN_2_UHS_SDR50 Value */ 860 #define MXC_S_SDHC_HOST_CN_2_UHS_SDR50 (MXC_V_SDHC_HOST_CN_2_UHS_SDR50 << MXC_F_SDHC_HOST_CN_2_UHS_POS) /**< HOST_CN_2_UHS_SDR50 Setting */ 861 #define MXC_V_SDHC_HOST_CN_2_UHS_DDR50 ((uint16_t)0x4UL) /**< HOST_CN_2_UHS_DDR50 Value */ 862 #define MXC_S_SDHC_HOST_CN_2_UHS_DDR50 (MXC_V_SDHC_HOST_CN_2_UHS_DDR50 << MXC_F_SDHC_HOST_CN_2_UHS_POS) /**< HOST_CN_2_UHS_DDR50 Setting */ 863 864 #define MXC_F_SDHC_HOST_CN_2_1_8V_SIGNAL_POS 3 /**< HOST_CN_2_1_8V_SIGNAL Position */ 865 #define MXC_F_SDHC_HOST_CN_2_1_8V_SIGNAL ((uint16_t)(0x1UL << MXC_F_SDHC_HOST_CN_2_1_8V_SIGNAL_POS)) /**< HOST_CN_2_1_8V_SIGNAL Mask */ 866 867 #define MXC_F_SDHC_HOST_CN_2_DRIVER_STRENGTH_POS 4 /**< HOST_CN_2_DRIVER_STRENGTH Position */ 868 #define MXC_F_SDHC_HOST_CN_2_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_HOST_CN_2_DRIVER_STRENGTH_POS)) /**< HOST_CN_2_DRIVER_STRENGTH Mask */ 869 #define MXC_V_SDHC_HOST_CN_2_DRIVER_STRENGTH_TYPEB ((uint16_t)0x0UL) /**< HOST_CN_2_DRIVER_STRENGTH_TYPEB Value */ 870 #define MXC_S_SDHC_HOST_CN_2_DRIVER_STRENGTH_TYPEB (MXC_V_SDHC_HOST_CN_2_DRIVER_STRENGTH_TYPEB << MXC_F_SDHC_HOST_CN_2_DRIVER_STRENGTH_POS) /**< HOST_CN_2_DRIVER_STRENGTH_TYPEB Setting */ 871 #define MXC_V_SDHC_HOST_CN_2_DRIVER_STRENGTH_TYPEA ((uint16_t)0x1UL) /**< HOST_CN_2_DRIVER_STRENGTH_TYPEA Value */ 872 #define MXC_S_SDHC_HOST_CN_2_DRIVER_STRENGTH_TYPEA (MXC_V_SDHC_HOST_CN_2_DRIVER_STRENGTH_TYPEA << MXC_F_SDHC_HOST_CN_2_DRIVER_STRENGTH_POS) /**< HOST_CN_2_DRIVER_STRENGTH_TYPEA Setting */ 873 #define MXC_V_SDHC_HOST_CN_2_DRIVER_STRENGTH_TYPEC ((uint16_t)0x2UL) /**< HOST_CN_2_DRIVER_STRENGTH_TYPEC Value */ 874 #define MXC_S_SDHC_HOST_CN_2_DRIVER_STRENGTH_TYPEC (MXC_V_SDHC_HOST_CN_2_DRIVER_STRENGTH_TYPEC << MXC_F_SDHC_HOST_CN_2_DRIVER_STRENGTH_POS) /**< HOST_CN_2_DRIVER_STRENGTH_TYPEC Setting */ 875 #define MXC_V_SDHC_HOST_CN_2_DRIVER_STRENGTH_TYPRD ((uint16_t)0x3UL) /**< HOST_CN_2_DRIVER_STRENGTH_TYPRD Value */ 876 #define MXC_S_SDHC_HOST_CN_2_DRIVER_STRENGTH_TYPRD (MXC_V_SDHC_HOST_CN_2_DRIVER_STRENGTH_TYPRD << MXC_F_SDHC_HOST_CN_2_DRIVER_STRENGTH_POS) /**< HOST_CN_2_DRIVER_STRENGTH_TYPRD Setting */ 877 878 #define MXC_F_SDHC_HOST_CN_2_EXCUTE_POS 6 /**< HOST_CN_2_EXCUTE Position */ 879 #define MXC_F_SDHC_HOST_CN_2_EXCUTE ((uint16_t)(0x1UL << MXC_F_SDHC_HOST_CN_2_EXCUTE_POS)) /**< HOST_CN_2_EXCUTE Mask */ 880 881 #define MXC_F_SDHC_HOST_CN_2_SAMPLING_CLK_POS 7 /**< HOST_CN_2_SAMPLING_CLK Position */ 882 #define MXC_F_SDHC_HOST_CN_2_SAMPLING_CLK ((uint16_t)(0x1UL << MXC_F_SDHC_HOST_CN_2_SAMPLING_CLK_POS)) /**< HOST_CN_2_SAMPLING_CLK Mask */ 883 884 #define MXC_F_SDHC_HOST_CN_2_ASYNCH_INT_POS 14 /**< HOST_CN_2_ASYNCH_INT Position */ 885 #define MXC_F_SDHC_HOST_CN_2_ASYNCH_INT ((uint16_t)(0x1UL << MXC_F_SDHC_HOST_CN_2_ASYNCH_INT_POS)) /**< HOST_CN_2_ASYNCH_INT Mask */ 886 887 #define MXC_F_SDHC_HOST_CN_2_PRESET_VAL_EN_POS 15 /**< HOST_CN_2_PRESET_VAL_EN Position */ 888 #define MXC_F_SDHC_HOST_CN_2_PRESET_VAL_EN ((uint16_t)(0x1UL << MXC_F_SDHC_HOST_CN_2_PRESET_VAL_EN_POS)) /**< HOST_CN_2_PRESET_VAL_EN Mask */ 889 890 /**@} end of group SDHC_HOST_CN_2_Register */ 891 892 /** 893 * @ingroup sdhc_registers 894 * @defgroup SDHC_CFG_0 SDHC_CFG_0 895 * @brief Capabilities 0-31. 896 * @{ 897 */ 898 #define MXC_F_SDHC_CFG_0_TO_FREQ_POS 0 /**< CFG_0_TO_FREQ Position */ 899 #define MXC_F_SDHC_CFG_0_TO_FREQ ((uint32_t)(0x3FUL << MXC_F_SDHC_CFG_0_TO_FREQ_POS)) /**< CFG_0_TO_FREQ Mask */ 900 #define MXC_V_SDHC_CFG_0_TO_FREQ_1MHZ ((uint32_t)0x1UL) /**< CFG_0_TO_FREQ_1MHZ Value */ 901 #define MXC_S_SDHC_CFG_0_TO_FREQ_1MHZ (MXC_V_SDHC_CFG_0_TO_FREQ_1MHZ << MXC_F_SDHC_CFG_0_TO_FREQ_POS) /**< CFG_0_TO_FREQ_1MHZ Setting */ 902 903 #define MXC_F_SDHC_CFG_0_CLK_UNIT_POS 7 /**< CFG_0_CLK_UNIT Position */ 904 #define MXC_F_SDHC_CFG_0_CLK_UNIT ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_CLK_UNIT_POS)) /**< CFG_0_CLK_UNIT Mask */ 905 906 #define MXC_F_SDHC_CFG_0_CLK_FREQ_POS 8 /**< CFG_0_CLK_FREQ Position */ 907 #define MXC_F_SDHC_CFG_0_CLK_FREQ ((uint32_t)(0xFFUL << MXC_F_SDHC_CFG_0_CLK_FREQ_POS)) /**< CFG_0_CLK_FREQ Mask */ 908 909 #define MXC_F_SDHC_CFG_0_MAX_BLK_LEN_POS 16 /**< CFG_0_MAX_BLK_LEN Position */ 910 #define MXC_F_SDHC_CFG_0_MAX_BLK_LEN ((uint32_t)(0x3UL << MXC_F_SDHC_CFG_0_MAX_BLK_LEN_POS)) /**< CFG_0_MAX_BLK_LEN Mask */ 911 #define MXC_V_SDHC_CFG_0_MAX_BLK_LEN_2048_BYTES ((uint32_t)0x2UL) /**< CFG_0_MAX_BLK_LEN_2048_BYTES Value */ 912 #define MXC_S_SDHC_CFG_0_MAX_BLK_LEN_2048_BYTES (MXC_V_SDHC_CFG_0_MAX_BLK_LEN_2048_BYTES << MXC_F_SDHC_CFG_0_MAX_BLK_LEN_POS) /**< CFG_0_MAX_BLK_LEN_2048_BYTES Setting */ 913 914 #define MXC_F_SDHC_CFG_0_8_BIT_POS 18 /**< CFG_0_8_BIT Position */ 915 #define MXC_F_SDHC_CFG_0_8_BIT ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_8_BIT_POS)) /**< CFG_0_8_BIT Mask */ 916 917 #define MXC_F_SDHC_CFG_0_ADMA2_POS 19 /**< CFG_0_ADMA2 Position */ 918 #define MXC_F_SDHC_CFG_0_ADMA2 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_ADMA2_POS)) /**< CFG_0_ADMA2 Mask */ 919 920 #define MXC_F_SDHC_CFG_0_HS_POS 21 /**< CFG_0_HS Position */ 921 #define MXC_F_SDHC_CFG_0_HS ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_HS_POS)) /**< CFG_0_HS Mask */ 922 923 #define MXC_F_SDHC_CFG_0_SDMA_POS 22 /**< CFG_0_SDMA Position */ 924 #define MXC_F_SDHC_CFG_0_SDMA ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_SDMA_POS)) /**< CFG_0_SDMA Mask */ 925 926 #define MXC_F_SDHC_CFG_0_SUSPEND_POS 23 /**< CFG_0_SUSPEND Position */ 927 #define MXC_F_SDHC_CFG_0_SUSPEND ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_SUSPEND_POS)) /**< CFG_0_SUSPEND Mask */ 928 929 #define MXC_F_SDHC_CFG_0_3_3V_POS 24 /**< CFG_0_3_3V Position */ 930 #define MXC_F_SDHC_CFG_0_3_3V ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_3_3V_POS)) /**< CFG_0_3_3V Mask */ 931 932 #define MXC_F_SDHC_CFG_0_3_0V_POS 25 /**< CFG_0_3_0V Position */ 933 #define MXC_F_SDHC_CFG_0_3_0V ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_3_0V_POS)) /**< CFG_0_3_0V Mask */ 934 935 #define MXC_F_SDHC_CFG_0_1_8V_POS 26 /**< CFG_0_1_8V Position */ 936 #define MXC_F_SDHC_CFG_0_1_8V ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_1_8V_POS)) /**< CFG_0_1_8V Mask */ 937 938 #define MXC_F_SDHC_CFG_0_64_BIT_SYS_BUS_POS 28 /**< CFG_0_64_BIT_SYS_BUS Position */ 939 #define MXC_F_SDHC_CFG_0_64_BIT_SYS_BUS ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_64_BIT_SYS_BUS_POS)) /**< CFG_0_64_BIT_SYS_BUS Mask */ 940 941 #define MXC_F_SDHC_CFG_0_ASYNC_INT_POS 29 /**< CFG_0_ASYNC_INT Position */ 942 #define MXC_F_SDHC_CFG_0_ASYNC_INT ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_ASYNC_INT_POS)) /**< CFG_0_ASYNC_INT Mask */ 943 944 #define MXC_F_SDHC_CFG_0_SLOT_TYPE_POS 30 /**< CFG_0_SLOT_TYPE Position */ 945 #define MXC_F_SDHC_CFG_0_SLOT_TYPE ((uint32_t)(0x3UL << MXC_F_SDHC_CFG_0_SLOT_TYPE_POS)) /**< CFG_0_SLOT_TYPE Mask */ 946 947 /**@} end of group SDHC_CFG_0_Register */ 948 949 /** 950 * @ingroup sdhc_registers 951 * @defgroup SDHC_CFG_1 SDHC_CFG_1 952 * @brief Capabilities 32-63. 953 * @{ 954 */ 955 #define MXC_F_SDHC_CFG_1_SDR50_POS 0 /**< CFG_1_SDR50 Position */ 956 #define MXC_F_SDHC_CFG_1_SDR50 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_SDR50_POS)) /**< CFG_1_SDR50 Mask */ 957 958 #define MXC_F_SDHC_CFG_1_SDR104_POS 1 /**< CFG_1_SDR104 Position */ 959 #define MXC_F_SDHC_CFG_1_SDR104 ((uint32_t)(0x0UL << MXC_F_SDHC_CFG_1_SDR104_POS)) /**< CFG_1_SDR104 Mask */ 960 961 #define MXC_F_SDHC_CFG_1_DDR50_POS 2 /**< CFG_1_DDR50 Position */ 962 #define MXC_F_SDHC_CFG_1_DDR50 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DDR50_POS)) /**< CFG_1_DDR50 Mask */ 963 964 #define MXC_F_SDHC_CFG_1_DRIVER_A_POS 4 /**< CFG_1_DRIVER_A Position */ 965 #define MXC_F_SDHC_CFG_1_DRIVER_A ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_A_POS)) /**< CFG_1_DRIVER_A Mask */ 966 967 #define MXC_F_SDHC_CFG_1_DRIVER_C_POS 5 /**< CFG_1_DRIVER_C Position */ 968 #define MXC_F_SDHC_CFG_1_DRIVER_C ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_C_POS)) /**< CFG_1_DRIVER_C Mask */ 969 970 #define MXC_F_SDHC_CFG_1_DRIVER_D_POS 6 /**< CFG_1_DRIVER_D Position */ 971 #define MXC_F_SDHC_CFG_1_DRIVER_D ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_D_POS)) /**< CFG_1_DRIVER_D Mask */ 972 973 #define MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS 8 /**< CFG_1_TIMER_CNT_TUNING Position */ 974 #define MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING ((uint32_t)(0xFUL << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)) /**< CFG_1_TIMER_CNT_TUNING Mask */ 975 #define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_DIS ((uint32_t)0x0UL) /**< CFG_1_TIMER_CNT_TUNING_DIS Value */ 976 #define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_DIS (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_DIS << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS) /**< CFG_1_TIMER_CNT_TUNING_DIS Setting */ 977 #define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_1SEC ((uint32_t)0x1UL) /**< CFG_1_TIMER_CNT_TUNING_1SEC Value */ 978 #define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_1SEC (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_1SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS) /**< CFG_1_TIMER_CNT_TUNING_1SEC Setting */ 979 #define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_2SEC ((uint32_t)0x2UL) /**< CFG_1_TIMER_CNT_TUNING_2SEC Value */ 980 #define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_2SEC (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_2SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS) /**< CFG_1_TIMER_CNT_TUNING_2SEC Setting */ 981 #define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_4SEC ((uint32_t)0x3UL) /**< CFG_1_TIMER_CNT_TUNING_4SEC Value */ 982 #define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_4SEC (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_4SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS) /**< CFG_1_TIMER_CNT_TUNING_4SEC Setting */ 983 #define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_8SEC ((uint32_t)0x4UL) /**< CFG_1_TIMER_CNT_TUNING_8SEC Value */ 984 #define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_8SEC (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_8SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS) /**< CFG_1_TIMER_CNT_TUNING_8SEC Setting */ 985 #define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_16SEC ((uint32_t)0x5UL) /**< CFG_1_TIMER_CNT_TUNING_16SEC Value */ 986 #define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_16SEC (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_16SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS) /**< CFG_1_TIMER_CNT_TUNING_16SEC Setting */ 987 #define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_32SEC ((uint32_t)0x6UL) /**< CFG_1_TIMER_CNT_TUNING_32SEC Value */ 988 #define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_32SEC (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_32SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS) /**< CFG_1_TIMER_CNT_TUNING_32SEC Setting */ 989 #define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_64SEC ((uint32_t)0x7UL) /**< CFG_1_TIMER_CNT_TUNING_64SEC Value */ 990 #define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_64SEC (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_64SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS) /**< CFG_1_TIMER_CNT_TUNING_64SEC Setting */ 991 #define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_128SEC ((uint32_t)0x8UL) /**< CFG_1_TIMER_CNT_TUNING_128SEC Value */ 992 #define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_128SEC (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_128SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS) /**< CFG_1_TIMER_CNT_TUNING_128SEC Setting */ 993 #define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_256SEC ((uint32_t)0x9UL) /**< CFG_1_TIMER_CNT_TUNING_256SEC Value */ 994 #define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_256SEC (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_256SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS) /**< CFG_1_TIMER_CNT_TUNING_256SEC Setting */ 995 #define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_512SEC ((uint32_t)0xAUL) /**< CFG_1_TIMER_CNT_TUNING_512SEC Value */ 996 #define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_512SEC (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_512SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS) /**< CFG_1_TIMER_CNT_TUNING_512SEC Setting */ 997 #define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_1024SEC ((uint32_t)0xBUL) /**< CFG_1_TIMER_CNT_TUNING_1024SEC Value */ 998 #define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_1024SEC (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_1024SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS) /**< CFG_1_TIMER_CNT_TUNING_1024SEC Setting */ 999 1000 #define MXC_F_SDHC_CFG_1_TUNING_SDR50_POS 13 /**< CFG_1_TUNING_SDR50 Position */ 1001 #define MXC_F_SDHC_CFG_1_TUNING_SDR50 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_TUNING_SDR50_POS)) /**< CFG_1_TUNING_SDR50 Mask */ 1002 1003 #define MXC_F_SDHC_CFG_1_RETUNING_POS 14 /**< CFG_1_RETUNING Position */ 1004 #define MXC_F_SDHC_CFG_1_RETUNING ((uint32_t)(0x3UL << MXC_F_SDHC_CFG_1_RETUNING_POS)) /**< CFG_1_RETUNING Mask */ 1005 1006 #define MXC_F_SDHC_CFG_1_CLK_MULTI_POS 16 /**< CFG_1_CLK_MULTI Position */ 1007 #define MXC_F_SDHC_CFG_1_CLK_MULTI ((uint32_t)(0xFFUL << MXC_F_SDHC_CFG_1_CLK_MULTI_POS)) /**< CFG_1_CLK_MULTI Mask */ 1008 1009 /**@} end of group SDHC_CFG_1_Register */ 1010 1011 /** 1012 * @ingroup sdhc_registers 1013 * @defgroup SDHC_MAX_CURR_CFG SDHC_MAX_CURR_CFG 1014 * @brief Maximum Current Capabilities. 1015 * @{ 1016 */ 1017 #define MXC_F_SDHC_MAX_CURR_CFG_3_3V_POS 0 /**< MAX_CURR_CFG_3_3V Position */ 1018 #define MXC_F_SDHC_MAX_CURR_CFG_3_3V ((uint32_t)(0xFFUL << MXC_F_SDHC_MAX_CURR_CFG_3_3V_POS)) /**< MAX_CURR_CFG_3_3V Mask */ 1019 1020 #define MXC_F_SDHC_MAX_CURR_CFG_3_0V_POS 8 /**< MAX_CURR_CFG_3_0V Position */ 1021 #define MXC_F_SDHC_MAX_CURR_CFG_3_0V ((uint32_t)(0xFFUL << MXC_F_SDHC_MAX_CURR_CFG_3_0V_POS)) /**< MAX_CURR_CFG_3_0V Mask */ 1022 1023 #define MXC_F_SDHC_MAX_CURR_CFG_1_8V_POS 16 /**< MAX_CURR_CFG_1_8V Position */ 1024 #define MXC_F_SDHC_MAX_CURR_CFG_1_8V ((uint32_t)(0xFFUL << MXC_F_SDHC_MAX_CURR_CFG_1_8V_POS)) /**< MAX_CURR_CFG_1_8V Mask */ 1025 1026 /**@} end of group SDHC_MAX_CURR_CFG_Register */ 1027 1028 /** 1029 * @ingroup sdhc_registers 1030 * @defgroup SDHC_FORCE_CMD SDHC_FORCE_CMD 1031 * @brief Force Event for Auto CMD Error Status. 1032 * @{ 1033 */ 1034 #define MXC_F_SDHC_FORCE_CMD_NOT_EXCU_POS 0 /**< FORCE_CMD_NOT_EXCU Position */ 1035 #define MXC_F_SDHC_FORCE_CMD_NOT_EXCU ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_NOT_EXCU_POS)) /**< FORCE_CMD_NOT_EXCU Mask */ 1036 1037 #define MXC_F_SDHC_FORCE_CMD_TO_POS 1 /**< FORCE_CMD_TO Position */ 1038 #define MXC_F_SDHC_FORCE_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_TO_POS)) /**< FORCE_CMD_TO Mask */ 1039 1040 #define MXC_F_SDHC_FORCE_CMD_CRC_POS 2 /**< FORCE_CMD_CRC Position */ 1041 #define MXC_F_SDHC_FORCE_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_CRC_POS)) /**< FORCE_CMD_CRC Mask */ 1042 1043 #define MXC_F_SDHC_FORCE_CMD_END_BIT_POS 3 /**< FORCE_CMD_END_BIT Position */ 1044 #define MXC_F_SDHC_FORCE_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_END_BIT_POS)) /**< FORCE_CMD_END_BIT Mask */ 1045 1046 #define MXC_F_SDHC_FORCE_CMD_INDEX_POS 4 /**< FORCE_CMD_INDEX Position */ 1047 #define MXC_F_SDHC_FORCE_CMD_INDEX ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_INDEX_POS)) /**< FORCE_CMD_INDEX Mask */ 1048 1049 #define MXC_F_SDHC_FORCE_CMD_NOT_ISSUED_POS 7 /**< FORCE_CMD_NOT_ISSUED Position */ 1050 #define MXC_F_SDHC_FORCE_CMD_NOT_ISSUED ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_NOT_ISSUED_POS)) /**< FORCE_CMD_NOT_ISSUED Mask */ 1051 1052 /**@} end of group SDHC_FORCE_CMD_Register */ 1053 1054 /** 1055 * @ingroup sdhc_registers 1056 * @defgroup SDHC_FORCE_EVENT_INT_STAT SDHC_FORCE_EVENT_INT_STAT 1057 * @brief Force Event for Error Interrupt Status. 1058 * @{ 1059 */ 1060 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_TO_POS 0 /**< FORCE_EVENT_INT_STAT_CMD_TO Position */ 1061 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_TO_POS)) /**< FORCE_EVENT_INT_STAT_CMD_TO Mask */ 1062 1063 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_CRC_POS 1 /**< FORCE_EVENT_INT_STAT_CMD_CRC Position */ 1064 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_CRC_POS)) /**< FORCE_EVENT_INT_STAT_CMD_CRC Mask */ 1065 1066 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_END_BIT_POS 2 /**< FORCE_EVENT_INT_STAT_CMD_END_BIT Position */ 1067 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_END_BIT_POS)) /**< FORCE_EVENT_INT_STAT_CMD_END_BIT Mask */ 1068 1069 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_INDEX_POS 3 /**< FORCE_EVENT_INT_STAT_CMD_INDEX Position */ 1070 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_INDEX ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_INDEX_POS)) /**< FORCE_EVENT_INT_STAT_CMD_INDEX Mask */ 1071 1072 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_TO_POS 4 /**< FORCE_EVENT_INT_STAT_DATA_TO Position */ 1073 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_TO ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_TO_POS)) /**< FORCE_EVENT_INT_STAT_DATA_TO Mask */ 1074 1075 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_CRC_POS 5 /**< FORCE_EVENT_INT_STAT_DATA_CRC Position */ 1076 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_CRC_POS)) /**< FORCE_EVENT_INT_STAT_DATA_CRC Mask */ 1077 1078 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_END_BIT_POS 6 /**< FORCE_EVENT_INT_STAT_DATA_END_BIT Position */ 1079 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_END_BIT_POS)) /**< FORCE_EVENT_INT_STAT_DATA_END_BIT Mask */ 1080 1081 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CURR_LIMIT_POS 7 /**< FORCE_EVENT_INT_STAT_CURR_LIMIT Position */ 1082 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CURR_LIMIT ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_CURR_LIMIT_POS)) /**< FORCE_EVENT_INT_STAT_CURR_LIMIT Mask */ 1083 1084 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_AUTO_CMD_POS 8 /**< FORCE_EVENT_INT_STAT_AUTO_CMD Position */ 1085 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_AUTO_CMD ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_AUTO_CMD_POS)) /**< FORCE_EVENT_INT_STAT_AUTO_CMD Mask */ 1086 1087 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_ADMA_POS 9 /**< FORCE_EVENT_INT_STAT_ADMA Position */ 1088 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_ADMA ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_ADMA_POS)) /**< FORCE_EVENT_INT_STAT_ADMA Mask */ 1089 1090 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_STAT_VENDOR_POS 12 /**< FORCE_EVENT_INT_STAT_STAT_VENDOR Position */ 1091 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_STAT_VENDOR ((uint16_t)(0xFUL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_STAT_VENDOR_POS)) /**< FORCE_EVENT_INT_STAT_STAT_VENDOR Mask */ 1092 1093 /**@} end of group SDHC_FORCE_EVENT_INT_STAT_Register */ 1094 1095 /** 1096 * @ingroup sdhc_registers 1097 * @defgroup SDHC_ADMA_ER SDHC_ADMA_ER 1098 * @brief ADMA Error Status. 1099 * @{ 1100 */ 1101 #define MXC_F_SDHC_ADMA_ER_STATE_POS 0 /**< ADMA_ER_STATE Position */ 1102 #define MXC_F_SDHC_ADMA_ER_STATE ((uint8_t)(0x3UL << MXC_F_SDHC_ADMA_ER_STATE_POS)) /**< ADMA_ER_STATE Mask */ 1103 1104 #define MXC_F_SDHC_ADMA_ER_LEN_MISMATCH_POS 2 /**< ADMA_ER_LEN_MISMATCH Position */ 1105 #define MXC_F_SDHC_ADMA_ER_LEN_MISMATCH ((uint8_t)(0x1UL << MXC_F_SDHC_ADMA_ER_LEN_MISMATCH_POS)) /**< ADMA_ER_LEN_MISMATCH Mask */ 1106 1107 /**@} end of group SDHC_ADMA_ER_Register */ 1108 1109 /** 1110 * @ingroup sdhc_registers 1111 * @defgroup SDHC_ADMA_ADDR_0 SDHC_ADMA_ADDR_0 1112 * @brief ADMA System Address 0-31. 1113 * @{ 1114 */ 1115 #define MXC_F_SDHC_ADMA_ADDR_0_ADDR_POS 0 /**< ADMA_ADDR_0_ADDR Position */ 1116 #define MXC_F_SDHC_ADMA_ADDR_0_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_ADMA_ADDR_0_ADDR_POS)) /**< ADMA_ADDR_0_ADDR Mask */ 1117 1118 /**@} end of group SDHC_ADMA_ADDR_0_Register */ 1119 1120 /** 1121 * @ingroup sdhc_registers 1122 * @defgroup SDHC_ADMA_ADDR_1 SDHC_ADMA_ADDR_1 1123 * @brief ADMA System Address 32-63. 1124 * @{ 1125 */ 1126 #define MXC_F_SDHC_ADMA_ADDR_1_ADDR_POS 0 /**< ADMA_ADDR_1_ADDR Position */ 1127 #define MXC_F_SDHC_ADMA_ADDR_1_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_ADMA_ADDR_1_ADDR_POS)) /**< ADMA_ADDR_1_ADDR Mask */ 1128 1129 /**@} end of group SDHC_ADMA_ADDR_1_Register */ 1130 1131 /** 1132 * @ingroup sdhc_registers 1133 * @defgroup SDHC_PRESET_0 SDHC_PRESET_0 1134 * @brief Preset Value for Initialization. 1135 * @{ 1136 */ 1137 #define MXC_F_SDHC_PRESET_0_SDCLK_FREQ_POS 0 /**< PRESET_0_SDCLK_FREQ Position */ 1138 #define MXC_F_SDHC_PRESET_0_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_0_SDCLK_FREQ_POS)) /**< PRESET_0_SDCLK_FREQ Mask */ 1139 1140 #define MXC_F_SDHC_PRESET_0_CLK_GEN_POS 10 /**< PRESET_0_CLK_GEN Position */ 1141 #define MXC_F_SDHC_PRESET_0_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_0_CLK_GEN_POS)) /**< PRESET_0_CLK_GEN Mask */ 1142 1143 #define MXC_F_SDHC_PRESET_0_DRIVER_STRENGTH_POS 14 /**< PRESET_0_DRIVER_STRENGTH Position */ 1144 #define MXC_F_SDHC_PRESET_0_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_0_DRIVER_STRENGTH_POS)) /**< PRESET_0_DRIVER_STRENGTH Mask */ 1145 #define MXC_V_SDHC_PRESET_0_DRIVER_STRENGTH_TYPEB ((uint16_t)0x0UL) /**< PRESET_0_DRIVER_STRENGTH_TYPEB Value */ 1146 #define MXC_S_SDHC_PRESET_0_DRIVER_STRENGTH_TYPEB (MXC_V_SDHC_PRESET_0_DRIVER_STRENGTH_TYPEB << MXC_F_SDHC_PRESET_0_DRIVER_STRENGTH_POS) /**< PRESET_0_DRIVER_STRENGTH_TYPEB Setting */ 1147 #define MXC_V_SDHC_PRESET_0_DRIVER_STRENGTH_TYPEA ((uint16_t)0x1UL) /**< PRESET_0_DRIVER_STRENGTH_TYPEA Value */ 1148 #define MXC_S_SDHC_PRESET_0_DRIVER_STRENGTH_TYPEA (MXC_V_SDHC_PRESET_0_DRIVER_STRENGTH_TYPEA << MXC_F_SDHC_PRESET_0_DRIVER_STRENGTH_POS) /**< PRESET_0_DRIVER_STRENGTH_TYPEA Setting */ 1149 #define MXC_V_SDHC_PRESET_0_DRIVER_STRENGTH_TYPEC ((uint16_t)0x2UL) /**< PRESET_0_DRIVER_STRENGTH_TYPEC Value */ 1150 #define MXC_S_SDHC_PRESET_0_DRIVER_STRENGTH_TYPEC (MXC_V_SDHC_PRESET_0_DRIVER_STRENGTH_TYPEC << MXC_F_SDHC_PRESET_0_DRIVER_STRENGTH_POS) /**< PRESET_0_DRIVER_STRENGTH_TYPEC Setting */ 1151 #define MXC_V_SDHC_PRESET_0_DRIVER_STRENGTH_TYPED ((uint16_t)0x3UL) /**< PRESET_0_DRIVER_STRENGTH_TYPED Value */ 1152 #define MXC_S_SDHC_PRESET_0_DRIVER_STRENGTH_TYPED (MXC_V_SDHC_PRESET_0_DRIVER_STRENGTH_TYPED << MXC_F_SDHC_PRESET_0_DRIVER_STRENGTH_POS) /**< PRESET_0_DRIVER_STRENGTH_TYPED Setting */ 1153 1154 /**@} end of group SDHC_PRESET_0_Register */ 1155 1156 /** 1157 * @ingroup sdhc_registers 1158 * @defgroup SDHC_PRESET_1 SDHC_PRESET_1 1159 * @brief Preset Value for Default Speed. 1160 * @{ 1161 */ 1162 #define MXC_F_SDHC_PRESET_1_SDCLK_FREQ_POS 0 /**< PRESET_1_SDCLK_FREQ Position */ 1163 #define MXC_F_SDHC_PRESET_1_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_1_SDCLK_FREQ_POS)) /**< PRESET_1_SDCLK_FREQ Mask */ 1164 1165 #define MXC_F_SDHC_PRESET_1_CLK_GEN_POS 10 /**< PRESET_1_CLK_GEN Position */ 1166 #define MXC_F_SDHC_PRESET_1_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_1_CLK_GEN_POS)) /**< PRESET_1_CLK_GEN Mask */ 1167 1168 #define MXC_F_SDHC_PRESET_1_DRIVER_STRENGTH_POS 14 /**< PRESET_1_DRIVER_STRENGTH Position */ 1169 #define MXC_F_SDHC_PRESET_1_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_1_DRIVER_STRENGTH_POS)) /**< PRESET_1_DRIVER_STRENGTH Mask */ 1170 #define MXC_V_SDHC_PRESET_1_DRIVER_STRENGTH_TYPEB ((uint16_t)0x0UL) /**< PRESET_1_DRIVER_STRENGTH_TYPEB Value */ 1171 #define MXC_S_SDHC_PRESET_1_DRIVER_STRENGTH_TYPEB (MXC_V_SDHC_PRESET_1_DRIVER_STRENGTH_TYPEB << MXC_F_SDHC_PRESET_1_DRIVER_STRENGTH_POS) /**< PRESET_1_DRIVER_STRENGTH_TYPEB Setting */ 1172 #define MXC_V_SDHC_PRESET_1_DRIVER_STRENGTH_TYPEA ((uint16_t)0x1UL) /**< PRESET_1_DRIVER_STRENGTH_TYPEA Value */ 1173 #define MXC_S_SDHC_PRESET_1_DRIVER_STRENGTH_TYPEA (MXC_V_SDHC_PRESET_1_DRIVER_STRENGTH_TYPEA << MXC_F_SDHC_PRESET_1_DRIVER_STRENGTH_POS) /**< PRESET_1_DRIVER_STRENGTH_TYPEA Setting */ 1174 #define MXC_V_SDHC_PRESET_1_DRIVER_STRENGTH_TYPEC ((uint16_t)0x2UL) /**< PRESET_1_DRIVER_STRENGTH_TYPEC Value */ 1175 #define MXC_S_SDHC_PRESET_1_DRIVER_STRENGTH_TYPEC (MXC_V_SDHC_PRESET_1_DRIVER_STRENGTH_TYPEC << MXC_F_SDHC_PRESET_1_DRIVER_STRENGTH_POS) /**< PRESET_1_DRIVER_STRENGTH_TYPEC Setting */ 1176 #define MXC_V_SDHC_PRESET_1_DRIVER_STRENGTH_TYPED ((uint16_t)0x3UL) /**< PRESET_1_DRIVER_STRENGTH_TYPED Value */ 1177 #define MXC_S_SDHC_PRESET_1_DRIVER_STRENGTH_TYPED (MXC_V_SDHC_PRESET_1_DRIVER_STRENGTH_TYPED << MXC_F_SDHC_PRESET_1_DRIVER_STRENGTH_POS) /**< PRESET_1_DRIVER_STRENGTH_TYPED Setting */ 1178 1179 /**@} end of group SDHC_PRESET_1_Register */ 1180 1181 /** 1182 * @ingroup sdhc_registers 1183 * @defgroup SDHC_PRESET_2 SDHC_PRESET_2 1184 * @brief Preset Value for High Speed. 1185 * @{ 1186 */ 1187 #define MXC_F_SDHC_PRESET_2_SDCLK_FREQ_POS 0 /**< PRESET_2_SDCLK_FREQ Position */ 1188 #define MXC_F_SDHC_PRESET_2_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_2_SDCLK_FREQ_POS)) /**< PRESET_2_SDCLK_FREQ Mask */ 1189 1190 #define MXC_F_SDHC_PRESET_2_CLK_GEN_POS 10 /**< PRESET_2_CLK_GEN Position */ 1191 #define MXC_F_SDHC_PRESET_2_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_2_CLK_GEN_POS)) /**< PRESET_2_CLK_GEN Mask */ 1192 1193 #define MXC_F_SDHC_PRESET_2_DRIVER_STRENGTH_POS 14 /**< PRESET_2_DRIVER_STRENGTH Position */ 1194 #define MXC_F_SDHC_PRESET_2_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_2_DRIVER_STRENGTH_POS)) /**< PRESET_2_DRIVER_STRENGTH Mask */ 1195 #define MXC_V_SDHC_PRESET_2_DRIVER_STRENGTH_TYPEB ((uint16_t)0x0UL) /**< PRESET_2_DRIVER_STRENGTH_TYPEB Value */ 1196 #define MXC_S_SDHC_PRESET_2_DRIVER_STRENGTH_TYPEB (MXC_V_SDHC_PRESET_2_DRIVER_STRENGTH_TYPEB << MXC_F_SDHC_PRESET_2_DRIVER_STRENGTH_POS) /**< PRESET_2_DRIVER_STRENGTH_TYPEB Setting */ 1197 #define MXC_V_SDHC_PRESET_2_DRIVER_STRENGTH_TYPEA ((uint16_t)0x1UL) /**< PRESET_2_DRIVER_STRENGTH_TYPEA Value */ 1198 #define MXC_S_SDHC_PRESET_2_DRIVER_STRENGTH_TYPEA (MXC_V_SDHC_PRESET_2_DRIVER_STRENGTH_TYPEA << MXC_F_SDHC_PRESET_2_DRIVER_STRENGTH_POS) /**< PRESET_2_DRIVER_STRENGTH_TYPEA Setting */ 1199 #define MXC_V_SDHC_PRESET_2_DRIVER_STRENGTH_TYPEC ((uint16_t)0x2UL) /**< PRESET_2_DRIVER_STRENGTH_TYPEC Value */ 1200 #define MXC_S_SDHC_PRESET_2_DRIVER_STRENGTH_TYPEC (MXC_V_SDHC_PRESET_2_DRIVER_STRENGTH_TYPEC << MXC_F_SDHC_PRESET_2_DRIVER_STRENGTH_POS) /**< PRESET_2_DRIVER_STRENGTH_TYPEC Setting */ 1201 #define MXC_V_SDHC_PRESET_2_DRIVER_STRENGTH_TYPED ((uint16_t)0x3UL) /**< PRESET_2_DRIVER_STRENGTH_TYPED Value */ 1202 #define MXC_S_SDHC_PRESET_2_DRIVER_STRENGTH_TYPED (MXC_V_SDHC_PRESET_2_DRIVER_STRENGTH_TYPED << MXC_F_SDHC_PRESET_2_DRIVER_STRENGTH_POS) /**< PRESET_2_DRIVER_STRENGTH_TYPED Setting */ 1203 1204 /**@} end of group SDHC_PRESET_2_Register */ 1205 1206 /** 1207 * @ingroup sdhc_registers 1208 * @defgroup SDHC_PRESET_3 SDHC_PRESET_3 1209 * @brief Preset Value for SDR12. 1210 * @{ 1211 */ 1212 #define MXC_F_SDHC_PRESET_3_SDCLK_FREQ_POS 0 /**< PRESET_3_SDCLK_FREQ Position */ 1213 #define MXC_F_SDHC_PRESET_3_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_3_SDCLK_FREQ_POS)) /**< PRESET_3_SDCLK_FREQ Mask */ 1214 1215 #define MXC_F_SDHC_PRESET_3_CLK_GEN_POS 10 /**< PRESET_3_CLK_GEN Position */ 1216 #define MXC_F_SDHC_PRESET_3_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_3_CLK_GEN_POS)) /**< PRESET_3_CLK_GEN Mask */ 1217 1218 #define MXC_F_SDHC_PRESET_3_DRIVER_STRENGTH_POS 14 /**< PRESET_3_DRIVER_STRENGTH Position */ 1219 #define MXC_F_SDHC_PRESET_3_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_3_DRIVER_STRENGTH_POS)) /**< PRESET_3_DRIVER_STRENGTH Mask */ 1220 #define MXC_V_SDHC_PRESET_3_DRIVER_STRENGTH_TYPEB ((uint16_t)0x0UL) /**< PRESET_3_DRIVER_STRENGTH_TYPEB Value */ 1221 #define MXC_S_SDHC_PRESET_3_DRIVER_STRENGTH_TYPEB (MXC_V_SDHC_PRESET_3_DRIVER_STRENGTH_TYPEB << MXC_F_SDHC_PRESET_3_DRIVER_STRENGTH_POS) /**< PRESET_3_DRIVER_STRENGTH_TYPEB Setting */ 1222 #define MXC_V_SDHC_PRESET_3_DRIVER_STRENGTH_TYPEA ((uint16_t)0x1UL) /**< PRESET_3_DRIVER_STRENGTH_TYPEA Value */ 1223 #define MXC_S_SDHC_PRESET_3_DRIVER_STRENGTH_TYPEA (MXC_V_SDHC_PRESET_3_DRIVER_STRENGTH_TYPEA << MXC_F_SDHC_PRESET_3_DRIVER_STRENGTH_POS) /**< PRESET_3_DRIVER_STRENGTH_TYPEA Setting */ 1224 #define MXC_V_SDHC_PRESET_3_DRIVER_STRENGTH_TYPEC ((uint16_t)0x2UL) /**< PRESET_3_DRIVER_STRENGTH_TYPEC Value */ 1225 #define MXC_S_SDHC_PRESET_3_DRIVER_STRENGTH_TYPEC (MXC_V_SDHC_PRESET_3_DRIVER_STRENGTH_TYPEC << MXC_F_SDHC_PRESET_3_DRIVER_STRENGTH_POS) /**< PRESET_3_DRIVER_STRENGTH_TYPEC Setting */ 1226 #define MXC_V_SDHC_PRESET_3_DRIVER_STRENGTH_TYPED ((uint16_t)0x3UL) /**< PRESET_3_DRIVER_STRENGTH_TYPED Value */ 1227 #define MXC_S_SDHC_PRESET_3_DRIVER_STRENGTH_TYPED (MXC_V_SDHC_PRESET_3_DRIVER_STRENGTH_TYPED << MXC_F_SDHC_PRESET_3_DRIVER_STRENGTH_POS) /**< PRESET_3_DRIVER_STRENGTH_TYPED Setting */ 1228 1229 /**@} end of group SDHC_PRESET_3_Register */ 1230 1231 /** 1232 * @ingroup sdhc_registers 1233 * @defgroup SDHC_PRESET_4 SDHC_PRESET_4 1234 * @brief Preset Value for SDR25. 1235 * @{ 1236 */ 1237 #define MXC_F_SDHC_PRESET_4_SDCLK_FREQ_POS 0 /**< PRESET_4_SDCLK_FREQ Position */ 1238 #define MXC_F_SDHC_PRESET_4_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_4_SDCLK_FREQ_POS)) /**< PRESET_4_SDCLK_FREQ Mask */ 1239 1240 #define MXC_F_SDHC_PRESET_4_CLK_GEN_POS 10 /**< PRESET_4_CLK_GEN Position */ 1241 #define MXC_F_SDHC_PRESET_4_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_4_CLK_GEN_POS)) /**< PRESET_4_CLK_GEN Mask */ 1242 1243 #define MXC_F_SDHC_PRESET_4_DRIVER_STRENGTH_POS 14 /**< PRESET_4_DRIVER_STRENGTH Position */ 1244 #define MXC_F_SDHC_PRESET_4_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_4_DRIVER_STRENGTH_POS)) /**< PRESET_4_DRIVER_STRENGTH Mask */ 1245 #define MXC_V_SDHC_PRESET_4_DRIVER_STRENGTH_TYPEB ((uint16_t)0x0UL) /**< PRESET_4_DRIVER_STRENGTH_TYPEB Value */ 1246 #define MXC_S_SDHC_PRESET_4_DRIVER_STRENGTH_TYPEB (MXC_V_SDHC_PRESET_4_DRIVER_STRENGTH_TYPEB << MXC_F_SDHC_PRESET_4_DRIVER_STRENGTH_POS) /**< PRESET_4_DRIVER_STRENGTH_TYPEB Setting */ 1247 #define MXC_V_SDHC_PRESET_4_DRIVER_STRENGTH_TYPEA ((uint16_t)0x1UL) /**< PRESET_4_DRIVER_STRENGTH_TYPEA Value */ 1248 #define MXC_S_SDHC_PRESET_4_DRIVER_STRENGTH_TYPEA (MXC_V_SDHC_PRESET_4_DRIVER_STRENGTH_TYPEA << MXC_F_SDHC_PRESET_4_DRIVER_STRENGTH_POS) /**< PRESET_4_DRIVER_STRENGTH_TYPEA Setting */ 1249 #define MXC_V_SDHC_PRESET_4_DRIVER_STRENGTH_TYPEC ((uint16_t)0x2UL) /**< PRESET_4_DRIVER_STRENGTH_TYPEC Value */ 1250 #define MXC_S_SDHC_PRESET_4_DRIVER_STRENGTH_TYPEC (MXC_V_SDHC_PRESET_4_DRIVER_STRENGTH_TYPEC << MXC_F_SDHC_PRESET_4_DRIVER_STRENGTH_POS) /**< PRESET_4_DRIVER_STRENGTH_TYPEC Setting */ 1251 #define MXC_V_SDHC_PRESET_4_DRIVER_STRENGTH_TYPED ((uint16_t)0x3UL) /**< PRESET_4_DRIVER_STRENGTH_TYPED Value */ 1252 #define MXC_S_SDHC_PRESET_4_DRIVER_STRENGTH_TYPED (MXC_V_SDHC_PRESET_4_DRIVER_STRENGTH_TYPED << MXC_F_SDHC_PRESET_4_DRIVER_STRENGTH_POS) /**< PRESET_4_DRIVER_STRENGTH_TYPED Setting */ 1253 1254 /**@} end of group SDHC_PRESET_4_Register */ 1255 1256 /** 1257 * @ingroup sdhc_registers 1258 * @defgroup SDHC_PRESET_5 SDHC_PRESET_5 1259 * @brief Preset Value for SDR50. 1260 * @{ 1261 */ 1262 #define MXC_F_SDHC_PRESET_5_SDCLK_FREQ_POS 0 /**< PRESET_5_SDCLK_FREQ Position */ 1263 #define MXC_F_SDHC_PRESET_5_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_5_SDCLK_FREQ_POS)) /**< PRESET_5_SDCLK_FREQ Mask */ 1264 1265 #define MXC_F_SDHC_PRESET_5_CLK_GEN_POS 10 /**< PRESET_5_CLK_GEN Position */ 1266 #define MXC_F_SDHC_PRESET_5_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_5_CLK_GEN_POS)) /**< PRESET_5_CLK_GEN Mask */ 1267 1268 #define MXC_F_SDHC_PRESET_5_DRIVER_STRENGTH_POS 14 /**< PRESET_5_DRIVER_STRENGTH Position */ 1269 #define MXC_F_SDHC_PRESET_5_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_5_DRIVER_STRENGTH_POS)) /**< PRESET_5_DRIVER_STRENGTH Mask */ 1270 #define MXC_V_SDHC_PRESET_5_DRIVER_STRENGTH_TYPEB ((uint16_t)0x0UL) /**< PRESET_5_DRIVER_STRENGTH_TYPEB Value */ 1271 #define MXC_S_SDHC_PRESET_5_DRIVER_STRENGTH_TYPEB (MXC_V_SDHC_PRESET_5_DRIVER_STRENGTH_TYPEB << MXC_F_SDHC_PRESET_5_DRIVER_STRENGTH_POS) /**< PRESET_5_DRIVER_STRENGTH_TYPEB Setting */ 1272 #define MXC_V_SDHC_PRESET_5_DRIVER_STRENGTH_TYPEA ((uint16_t)0x1UL) /**< PRESET_5_DRIVER_STRENGTH_TYPEA Value */ 1273 #define MXC_S_SDHC_PRESET_5_DRIVER_STRENGTH_TYPEA (MXC_V_SDHC_PRESET_5_DRIVER_STRENGTH_TYPEA << MXC_F_SDHC_PRESET_5_DRIVER_STRENGTH_POS) /**< PRESET_5_DRIVER_STRENGTH_TYPEA Setting */ 1274 #define MXC_V_SDHC_PRESET_5_DRIVER_STRENGTH_TYPEC ((uint16_t)0x2UL) /**< PRESET_5_DRIVER_STRENGTH_TYPEC Value */ 1275 #define MXC_S_SDHC_PRESET_5_DRIVER_STRENGTH_TYPEC (MXC_V_SDHC_PRESET_5_DRIVER_STRENGTH_TYPEC << MXC_F_SDHC_PRESET_5_DRIVER_STRENGTH_POS) /**< PRESET_5_DRIVER_STRENGTH_TYPEC Setting */ 1276 #define MXC_V_SDHC_PRESET_5_DRIVER_STRENGTH_TYPED ((uint16_t)0x3UL) /**< PRESET_5_DRIVER_STRENGTH_TYPED Value */ 1277 #define MXC_S_SDHC_PRESET_5_DRIVER_STRENGTH_TYPED (MXC_V_SDHC_PRESET_5_DRIVER_STRENGTH_TYPED << MXC_F_SDHC_PRESET_5_DRIVER_STRENGTH_POS) /**< PRESET_5_DRIVER_STRENGTH_TYPED Setting */ 1278 1279 /**@} end of group SDHC_PRESET_5_Register */ 1280 1281 /** 1282 * @ingroup sdhc_registers 1283 * @defgroup SDHC_PRESET_6 SDHC_PRESET_6 1284 * @brief Preset Value for SDR104. 1285 * @{ 1286 */ 1287 #define MXC_F_SDHC_PRESET_6_SDCLK_FREQ_POS 0 /**< PRESET_6_SDCLK_FREQ Position */ 1288 #define MXC_F_SDHC_PRESET_6_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_6_SDCLK_FREQ_POS)) /**< PRESET_6_SDCLK_FREQ Mask */ 1289 1290 #define MXC_F_SDHC_PRESET_6_CLK_GEN_POS 10 /**< PRESET_6_CLK_GEN Position */ 1291 #define MXC_F_SDHC_PRESET_6_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_6_CLK_GEN_POS)) /**< PRESET_6_CLK_GEN Mask */ 1292 1293 #define MXC_F_SDHC_PRESET_6_DRIVER_STRENGTH_POS 14 /**< PRESET_6_DRIVER_STRENGTH Position */ 1294 #define MXC_F_SDHC_PRESET_6_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_6_DRIVER_STRENGTH_POS)) /**< PRESET_6_DRIVER_STRENGTH Mask */ 1295 #define MXC_V_SDHC_PRESET_6_DRIVER_STRENGTH_TYPEB ((uint16_t)0x0UL) /**< PRESET_6_DRIVER_STRENGTH_TYPEB Value */ 1296 #define MXC_S_SDHC_PRESET_6_DRIVER_STRENGTH_TYPEB (MXC_V_SDHC_PRESET_6_DRIVER_STRENGTH_TYPEB << MXC_F_SDHC_PRESET_6_DRIVER_STRENGTH_POS) /**< PRESET_6_DRIVER_STRENGTH_TYPEB Setting */ 1297 #define MXC_V_SDHC_PRESET_6_DRIVER_STRENGTH_TYPEA ((uint16_t)0x1UL) /**< PRESET_6_DRIVER_STRENGTH_TYPEA Value */ 1298 #define MXC_S_SDHC_PRESET_6_DRIVER_STRENGTH_TYPEA (MXC_V_SDHC_PRESET_6_DRIVER_STRENGTH_TYPEA << MXC_F_SDHC_PRESET_6_DRIVER_STRENGTH_POS) /**< PRESET_6_DRIVER_STRENGTH_TYPEA Setting */ 1299 #define MXC_V_SDHC_PRESET_6_DRIVER_STRENGTH_TYPEC ((uint16_t)0x2UL) /**< PRESET_6_DRIVER_STRENGTH_TYPEC Value */ 1300 #define MXC_S_SDHC_PRESET_6_DRIVER_STRENGTH_TYPEC (MXC_V_SDHC_PRESET_6_DRIVER_STRENGTH_TYPEC << MXC_F_SDHC_PRESET_6_DRIVER_STRENGTH_POS) /**< PRESET_6_DRIVER_STRENGTH_TYPEC Setting */ 1301 #define MXC_V_SDHC_PRESET_6_DRIVER_STRENGTH_TYPED ((uint16_t)0x3UL) /**< PRESET_6_DRIVER_STRENGTH_TYPED Value */ 1302 #define MXC_S_SDHC_PRESET_6_DRIVER_STRENGTH_TYPED (MXC_V_SDHC_PRESET_6_DRIVER_STRENGTH_TYPED << MXC_F_SDHC_PRESET_6_DRIVER_STRENGTH_POS) /**< PRESET_6_DRIVER_STRENGTH_TYPED Setting */ 1303 1304 /**@} end of group SDHC_PRESET_6_Register */ 1305 1306 /** 1307 * @ingroup sdhc_registers 1308 * @defgroup SDHC_PRESET_7 SDHC_PRESET_7 1309 * @brief Preset Value for DDR50. 1310 * @{ 1311 */ 1312 #define MXC_F_SDHC_PRESET_7_SDCLK_FREQ_POS 0 /**< PRESET_7_SDCLK_FREQ Position */ 1313 #define MXC_F_SDHC_PRESET_7_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_7_SDCLK_FREQ_POS)) /**< PRESET_7_SDCLK_FREQ Mask */ 1314 1315 #define MXC_F_SDHC_PRESET_7_CLK_GEN_POS 10 /**< PRESET_7_CLK_GEN Position */ 1316 #define MXC_F_SDHC_PRESET_7_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_7_CLK_GEN_POS)) /**< PRESET_7_CLK_GEN Mask */ 1317 1318 #define MXC_F_SDHC_PRESET_7_DRIVER_STRENGTH_POS 14 /**< PRESET_7_DRIVER_STRENGTH Position */ 1319 #define MXC_F_SDHC_PRESET_7_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_7_DRIVER_STRENGTH_POS)) /**< PRESET_7_DRIVER_STRENGTH Mask */ 1320 #define MXC_V_SDHC_PRESET_7_DRIVER_STRENGTH_TYPEB ((uint16_t)0x0UL) /**< PRESET_7_DRIVER_STRENGTH_TYPEB Value */ 1321 #define MXC_S_SDHC_PRESET_7_DRIVER_STRENGTH_TYPEB (MXC_V_SDHC_PRESET_7_DRIVER_STRENGTH_TYPEB << MXC_F_SDHC_PRESET_7_DRIVER_STRENGTH_POS) /**< PRESET_7_DRIVER_STRENGTH_TYPEB Setting */ 1322 #define MXC_V_SDHC_PRESET_7_DRIVER_STRENGTH_TYPEA ((uint16_t)0x1UL) /**< PRESET_7_DRIVER_STRENGTH_TYPEA Value */ 1323 #define MXC_S_SDHC_PRESET_7_DRIVER_STRENGTH_TYPEA (MXC_V_SDHC_PRESET_7_DRIVER_STRENGTH_TYPEA << MXC_F_SDHC_PRESET_7_DRIVER_STRENGTH_POS) /**< PRESET_7_DRIVER_STRENGTH_TYPEA Setting */ 1324 #define MXC_V_SDHC_PRESET_7_DRIVER_STRENGTH_TYPEC ((uint16_t)0x2UL) /**< PRESET_7_DRIVER_STRENGTH_TYPEC Value */ 1325 #define MXC_S_SDHC_PRESET_7_DRIVER_STRENGTH_TYPEC (MXC_V_SDHC_PRESET_7_DRIVER_STRENGTH_TYPEC << MXC_F_SDHC_PRESET_7_DRIVER_STRENGTH_POS) /**< PRESET_7_DRIVER_STRENGTH_TYPEC Setting */ 1326 #define MXC_V_SDHC_PRESET_7_DRIVER_STRENGTH_TYPED ((uint16_t)0x3UL) /**< PRESET_7_DRIVER_STRENGTH_TYPED Value */ 1327 #define MXC_S_SDHC_PRESET_7_DRIVER_STRENGTH_TYPED (MXC_V_SDHC_PRESET_7_DRIVER_STRENGTH_TYPED << MXC_F_SDHC_PRESET_7_DRIVER_STRENGTH_POS) /**< PRESET_7_DRIVER_STRENGTH_TYPED Setting */ 1328 1329 /**@} end of group SDHC_PRESET_7_Register */ 1330 1331 /** 1332 * @ingroup sdhc_registers 1333 * @defgroup SDHC_SLOT_INT SDHC_SLOT_INT 1334 * @brief Slot Interrupt Status. 1335 * @{ 1336 */ 1337 #define MXC_F_SDHC_SLOT_INT_INT_SIGNALS_POS 0 /**< SLOT_INT_INT_SIGNALS Position */ 1338 #define MXC_F_SDHC_SLOT_INT_INT_SIGNALS ((uint16_t)(0x1UL << MXC_F_SDHC_SLOT_INT_INT_SIGNALS_POS)) /**< SLOT_INT_INT_SIGNALS Mask */ 1339 1340 /**@} end of group SDHC_SLOT_INT_Register */ 1341 1342 /** 1343 * @ingroup sdhc_registers 1344 * @defgroup SDHC_HOST_CN_VER SDHC_HOST_CN_VER 1345 * @brief Host Controller Version. 1346 * @{ 1347 */ 1348 #define MXC_F_SDHC_HOST_CN_VER_SPEC_VER_POS 0 /**< HOST_CN_VER_SPEC_VER Position */ 1349 #define MXC_F_SDHC_HOST_CN_VER_SPEC_VER ((uint16_t)(0xFFUL << MXC_F_SDHC_HOST_CN_VER_SPEC_VER_POS)) /**< HOST_CN_VER_SPEC_VER Mask */ 1350 1351 #define MXC_F_SDHC_HOST_CN_VER_VEND_VER_POS 8 /**< HOST_CN_VER_VEND_VER Position */ 1352 #define MXC_F_SDHC_HOST_CN_VER_VEND_VER ((uint16_t)(0xFFUL << MXC_F_SDHC_HOST_CN_VER_VEND_VER_POS)) /**< HOST_CN_VER_VEND_VER Mask */ 1353 1354 /**@} end of group SDHC_HOST_CN_VER_Register */ 1355 1356 #ifdef __cplusplus 1357 } 1358 #endif 1359 1360 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SDHC_REGS_H_ 1361
