1 /** 2 * @file pwrseq_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup pwrseq_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_PWRSEQ_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_PWRSEQ_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup pwrseq 67 * @defgroup pwrseq_registers PWRSEQ_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. 69 * @details Power Sequencer / Low Power Control Register. 70 */ 71 72 /** 73 * @ingroup pwrseq_registers 74 * Structure type to access the PWRSEQ Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> PWRSEQ CTRL Register */ 78 __IO uint32_t gpio0_wk_fl; /**< <tt>\b 0x04:</tt> PWRSEQ GPIO0_WK_FL Register */ 79 __IO uint32_t gpio0_wk_en; /**< <tt>\b 0x08:</tt> PWRSEQ GPIO0_WK_EN Register */ 80 __IO uint32_t gpio1_wk_fl; /**< <tt>\b 0x0C:</tt> PWRSEQ GPIO1_WK_FL Register */ 81 __IO uint32_t gpio1_wk_en; /**< <tt>\b 0x10:</tt> PWRSEQ GPIO1_WK_EN Register */ 82 __IO uint32_t gpio2_wk_fl; /**< <tt>\b 0x14:</tt> PWRSEQ GPIO2_WK_FL Register */ 83 __IO uint32_t gpio2_wk_en; /**< <tt>\b 0x18:</tt> PWRSEQ GPIO2_WK_EN Register */ 84 __IO uint32_t gpio3_wk_fl; /**< <tt>\b 0x1C:</tt> PWRSEQ GPIO3_WK_FL Register */ 85 __IO uint32_t gpio3_wk_en; /**< <tt>\b 0x20:</tt> PWRSEQ GPIO3_WK_EN Register */ 86 __R uint32_t rsv_0x24_0x2f[3]; 87 __IO uint32_t usb_wk_fl; /**< <tt>\b 0x30:</tt> PWRSEQ USB_WK_FL Register */ 88 __IO uint32_t usb_wk_en; /**< <tt>\b 0x34:</tt> PWRSEQ USB_WK_EN Register */ 89 __R uint32_t rsv_0x38_0x3f[2]; 90 __IO uint32_t mem_pwr; /**< <tt>\b 0x40:</tt> PWRSEQ MEM_PWR Register */ 91 } mxc_pwrseq_regs_t; 92 93 /* Register offsets for module PWRSEQ */ 94 /** 95 * @ingroup pwrseq_registers 96 * @defgroup PWRSEQ_Register_Offsets Register Offsets 97 * @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. 98 * @{ 99 */ 100 #define MXC_R_PWRSEQ_CTRL ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0000</tt> */ 101 #define MXC_R_PWRSEQ_GPIO0_WK_FL ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0004</tt> */ 102 #define MXC_R_PWRSEQ_GPIO0_WK_EN ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0008</tt> */ 103 #define MXC_R_PWRSEQ_GPIO1_WK_FL ((uint32_t)0x0000000CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x000C</tt> */ 104 #define MXC_R_PWRSEQ_GPIO1_WK_EN ((uint32_t)0x00000010UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0010</tt> */ 105 #define MXC_R_PWRSEQ_GPIO2_WK_FL ((uint32_t)0x00000014UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0014</tt> */ 106 #define MXC_R_PWRSEQ_GPIO2_WK_EN ((uint32_t)0x00000018UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0018</tt> */ 107 #define MXC_R_PWRSEQ_GPIO3_WK_FL ((uint32_t)0x0000001CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x001C</tt> */ 108 #define MXC_R_PWRSEQ_GPIO3_WK_EN ((uint32_t)0x00000020UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0020</tt> */ 109 #define MXC_R_PWRSEQ_USB_WK_FL ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0030</tt> */ 110 #define MXC_R_PWRSEQ_USB_WK_EN ((uint32_t)0x00000034UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0034</tt> */ 111 #define MXC_R_PWRSEQ_MEM_PWR ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0040</tt> */ 112 /**@} end of group pwrseq_registers */ 113 114 /** 115 * @ingroup pwrseq_registers 116 * @defgroup PWRSEQ_CTRL PWRSEQ_CTRL 117 * @brief Low Power Control Register. 118 * @{ 119 */ 120 #define MXC_F_PWRSEQ_CTRL_RAMRET_POS 0 /**< CTRL_RAMRET Position */ 121 #define MXC_F_PWRSEQ_CTRL_RAMRET ((uint32_t)(0x3UL << MXC_F_PWRSEQ_CTRL_RAMRET_POS)) /**< CTRL_RAMRET Mask */ 122 #define MXC_V_PWRSEQ_CTRL_RAMRET_DIS ((uint32_t)0x0UL) /**< CTRL_RAMRET_DIS Value */ 123 #define MXC_S_PWRSEQ_CTRL_RAMRET_DIS (MXC_V_PWRSEQ_CTRL_RAMRET_DIS << MXC_F_PWRSEQ_CTRL_RAMRET_POS) /**< CTRL_RAMRET_DIS Setting */ 124 #define MXC_V_PWRSEQ_CTRL_RAMRET_EN1 ((uint32_t)0x1UL) /**< CTRL_RAMRET_EN1 Value */ 125 #define MXC_S_PWRSEQ_CTRL_RAMRET_EN1 (MXC_V_PWRSEQ_CTRL_RAMRET_EN1 << MXC_F_PWRSEQ_CTRL_RAMRET_POS) /**< CTRL_RAMRET_EN1 Setting */ 126 #define MXC_V_PWRSEQ_CTRL_RAMRET_EN2 ((uint32_t)0x2UL) /**< CTRL_RAMRET_EN2 Value */ 127 #define MXC_S_PWRSEQ_CTRL_RAMRET_EN2 (MXC_V_PWRSEQ_CTRL_RAMRET_EN2 << MXC_F_PWRSEQ_CTRL_RAMRET_POS) /**< CTRL_RAMRET_EN2 Setting */ 128 #define MXC_V_PWRSEQ_CTRL_RAMRET_EN3 ((uint32_t)0x3UL) /**< CTRL_RAMRET_EN3 Value */ 129 #define MXC_S_PWRSEQ_CTRL_RAMRET_EN3 (MXC_V_PWRSEQ_CTRL_RAMRET_EN3 << MXC_F_PWRSEQ_CTRL_RAMRET_POS) /**< CTRL_RAMRET_EN3 Setting */ 130 131 #define MXC_F_PWRSEQ_CTRL_RREGEN_POS 8 /**< CTRL_RREGEN Position */ 132 #define MXC_F_PWRSEQ_CTRL_RREGEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_RREGEN_POS)) /**< CTRL_RREGEN Mask */ 133 #define MXC_V_PWRSEQ_CTRL_RREGEN_DIS ((uint32_t)0x0UL) /**< CTRL_RREGEN_DIS Value */ 134 #define MXC_S_PWRSEQ_CTRL_RREGEN_DIS (MXC_V_PWRSEQ_CTRL_RREGEN_DIS << MXC_F_PWRSEQ_CTRL_RREGEN_POS) /**< CTRL_RREGEN_DIS Setting */ 135 #define MXC_V_PWRSEQ_CTRL_RREGEN_EN ((uint32_t)0x1UL) /**< CTRL_RREGEN_EN Value */ 136 #define MXC_S_PWRSEQ_CTRL_RREGEN_EN (MXC_V_PWRSEQ_CTRL_RREGEN_EN << MXC_F_PWRSEQ_CTRL_RREGEN_POS) /**< CTRL_RREGEN_EN Setting */ 137 138 #define MXC_F_PWRSEQ_CTRL_BKGRND_POS 9 /**< CTRL_BKGRND Position */ 139 #define MXC_F_PWRSEQ_CTRL_BKGRND ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_BKGRND_POS)) /**< CTRL_BKGRND Mask */ 140 #define MXC_V_PWRSEQ_CTRL_BKGRND_DIS ((uint32_t)0x0UL) /**< CTRL_BKGRND_DIS Value */ 141 #define MXC_S_PWRSEQ_CTRL_BKGRND_DIS (MXC_V_PWRSEQ_CTRL_BKGRND_DIS << MXC_F_PWRSEQ_CTRL_BKGRND_POS) /**< CTRL_BKGRND_DIS Setting */ 142 #define MXC_V_PWRSEQ_CTRL_BKGRND_EN ((uint32_t)0x1UL) /**< CTRL_BKGRND_EN Value */ 143 #define MXC_S_PWRSEQ_CTRL_BKGRND_EN (MXC_V_PWRSEQ_CTRL_BKGRND_EN << MXC_F_PWRSEQ_CTRL_BKGRND_POS) /**< CTRL_BKGRND_EN Setting */ 144 145 #define MXC_F_PWRSEQ_CTRL_FWKM_POS 10 /**< CTRL_FWKM Position */ 146 #define MXC_F_PWRSEQ_CTRL_FWKM ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_FWKM_POS)) /**< CTRL_FWKM Mask */ 147 #define MXC_V_PWRSEQ_CTRL_FWKM_DIS ((uint32_t)0x0UL) /**< CTRL_FWKM_DIS Value */ 148 #define MXC_S_PWRSEQ_CTRL_FWKM_DIS (MXC_V_PWRSEQ_CTRL_FWKM_DIS << MXC_F_PWRSEQ_CTRL_FWKM_POS) /**< CTRL_FWKM_DIS Setting */ 149 #define MXC_V_PWRSEQ_CTRL_FWKM_EN ((uint32_t)0x1UL) /**< CTRL_FWKM_EN Value */ 150 #define MXC_S_PWRSEQ_CTRL_FWKM_EN (MXC_V_PWRSEQ_CTRL_FWKM_EN << MXC_F_PWRSEQ_CTRL_FWKM_POS) /**< CTRL_FWKM_EN Setting */ 151 152 #define MXC_F_PWRSEQ_CTRL_BGOFF_POS 11 /**< CTRL_BGOFF Position */ 153 #define MXC_F_PWRSEQ_CTRL_BGOFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_BGOFF_POS)) /**< CTRL_BGOFF Mask */ 154 #define MXC_V_PWRSEQ_CTRL_BGOFF_ON ((uint32_t)0x0UL) /**< CTRL_BGOFF_ON Value */ 155 #define MXC_S_PWRSEQ_CTRL_BGOFF_ON (MXC_V_PWRSEQ_CTRL_BGOFF_ON << MXC_F_PWRSEQ_CTRL_BGOFF_POS) /**< CTRL_BGOFF_ON Setting */ 156 #define MXC_V_PWRSEQ_CTRL_BGOFF_OFF ((uint32_t)0x1UL) /**< CTRL_BGOFF_OFF Value */ 157 #define MXC_S_PWRSEQ_CTRL_BGOFF_OFF (MXC_V_PWRSEQ_CTRL_BGOFF_OFF << MXC_F_PWRSEQ_CTRL_BGOFF_POS) /**< CTRL_BGOFF_OFF Setting */ 158 159 #define MXC_F_PWRSEQ_CTRL_PORVCOREMD_POS 12 /**< CTRL_PORVCOREMD Position */ 160 #define MXC_F_PWRSEQ_CTRL_PORVCOREMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_PORVCOREMD_POS)) /**< CTRL_PORVCOREMD Mask */ 161 #define MXC_V_PWRSEQ_CTRL_PORVCOREMD_EN ((uint32_t)0x0UL) /**< CTRL_PORVCOREMD_EN Value */ 162 #define MXC_S_PWRSEQ_CTRL_PORVCOREMD_EN (MXC_V_PWRSEQ_CTRL_PORVCOREMD_EN << MXC_F_PWRSEQ_CTRL_PORVCOREMD_POS) /**< CTRL_PORVCOREMD_EN Setting */ 163 #define MXC_V_PWRSEQ_CTRL_PORVCOREMD_DIS ((uint32_t)0x1UL) /**< CTRL_PORVCOREMD_DIS Value */ 164 #define MXC_S_PWRSEQ_CTRL_PORVCOREMD_DIS (MXC_V_PWRSEQ_CTRL_PORVCOREMD_DIS << MXC_F_PWRSEQ_CTRL_PORVCOREMD_POS) /**< CTRL_PORVCOREMD_DIS Setting */ 165 166 #define MXC_F_PWRSEQ_CTRL_VCOREMD_POS 20 /**< CTRL_VCOREMD Position */ 167 #define MXC_F_PWRSEQ_CTRL_VCOREMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_VCOREMD_POS)) /**< CTRL_VCOREMD Mask */ 168 #define MXC_V_PWRSEQ_CTRL_VCOREMD_EN ((uint32_t)0x0UL) /**< CTRL_VCOREMD_EN Value */ 169 #define MXC_S_PWRSEQ_CTRL_VCOREMD_EN (MXC_V_PWRSEQ_CTRL_VCOREMD_EN << MXC_F_PWRSEQ_CTRL_VCOREMD_POS) /**< CTRL_VCOREMD_EN Setting */ 170 #define MXC_V_PWRSEQ_CTRL_VCOREMD_DIS ((uint32_t)0x1UL) /**< CTRL_VCOREMD_DIS Value */ 171 #define MXC_S_PWRSEQ_CTRL_VCOREMD_DIS (MXC_V_PWRSEQ_CTRL_VCOREMD_DIS << MXC_F_PWRSEQ_CTRL_VCOREMD_POS) /**< CTRL_VCOREMD_DIS Setting */ 172 173 #define MXC_F_PWRSEQ_CTRL_VRTCMD_POS 21 /**< CTRL_VRTCMD Position */ 174 #define MXC_F_PWRSEQ_CTRL_VRTCMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_VRTCMD_POS)) /**< CTRL_VRTCMD Mask */ 175 #define MXC_V_PWRSEQ_CTRL_VRTCMD_EN ((uint32_t)0x0UL) /**< CTRL_VRTCMD_EN Value */ 176 #define MXC_S_PWRSEQ_CTRL_VRTCMD_EN (MXC_V_PWRSEQ_CTRL_VRTCMD_EN << MXC_F_PWRSEQ_CTRL_VRTCMD_POS) /**< CTRL_VRTCMD_EN Setting */ 177 #define MXC_V_PWRSEQ_CTRL_VRTCMD_DIS ((uint32_t)0x1UL) /**< CTRL_VRTCMD_DIS Value */ 178 #define MXC_S_PWRSEQ_CTRL_VRTCMD_DIS (MXC_V_PWRSEQ_CTRL_VRTCMD_DIS << MXC_F_PWRSEQ_CTRL_VRTCMD_POS) /**< CTRL_VRTCMD_DIS Setting */ 179 180 #define MXC_F_PWRSEQ_CTRL_VDDAMD_POS 22 /**< CTRL_VDDAMD Position */ 181 #define MXC_F_PWRSEQ_CTRL_VDDAMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_VDDAMD_POS)) /**< CTRL_VDDAMD Mask */ 182 #define MXC_V_PWRSEQ_CTRL_VDDAMD_EN ((uint32_t)0x0UL) /**< CTRL_VDDAMD_EN Value */ 183 #define MXC_S_PWRSEQ_CTRL_VDDAMD_EN (MXC_V_PWRSEQ_CTRL_VDDAMD_EN << MXC_F_PWRSEQ_CTRL_VDDAMD_POS) /**< CTRL_VDDAMD_EN Setting */ 184 #define MXC_V_PWRSEQ_CTRL_VDDAMD_DIS ((uint32_t)0x1UL) /**< CTRL_VDDAMD_DIS Value */ 185 #define MXC_S_PWRSEQ_CTRL_VDDAMD_DIS (MXC_V_PWRSEQ_CTRL_VDDAMD_DIS << MXC_F_PWRSEQ_CTRL_VDDAMD_POS) /**< CTRL_VDDAMD_DIS Setting */ 186 187 #define MXC_F_PWRSEQ_CTRL_VDDIOMD_POS 23 /**< CTRL_VDDIOMD Position */ 188 #define MXC_F_PWRSEQ_CTRL_VDDIOMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_VDDIOMD_POS)) /**< CTRL_VDDIOMD Mask */ 189 #define MXC_V_PWRSEQ_CTRL_VDDIOMD_EN ((uint32_t)0x0UL) /**< CTRL_VDDIOMD_EN Value */ 190 #define MXC_S_PWRSEQ_CTRL_VDDIOMD_EN (MXC_V_PWRSEQ_CTRL_VDDIOMD_EN << MXC_F_PWRSEQ_CTRL_VDDIOMD_POS) /**< CTRL_VDDIOMD_EN Setting */ 191 #define MXC_V_PWRSEQ_CTRL_VDDIOMD_DIS ((uint32_t)0x1UL) /**< CTRL_VDDIOMD_DIS Value */ 192 #define MXC_S_PWRSEQ_CTRL_VDDIOMD_DIS (MXC_V_PWRSEQ_CTRL_VDDIOMD_DIS << MXC_F_PWRSEQ_CTRL_VDDIOMD_POS) /**< CTRL_VDDIOMD_DIS Setting */ 193 194 #define MXC_F_PWRSEQ_CTRL_VDDIOHMD_POS 24 /**< CTRL_VDDIOHMD Position */ 195 #define MXC_F_PWRSEQ_CTRL_VDDIOHMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_VDDIOHMD_POS)) /**< CTRL_VDDIOHMD Mask */ 196 #define MXC_V_PWRSEQ_CTRL_VDDIOHMD_EN ((uint32_t)0x0UL) /**< CTRL_VDDIOHMD_EN Value */ 197 #define MXC_S_PWRSEQ_CTRL_VDDIOHMD_EN (MXC_V_PWRSEQ_CTRL_VDDIOHMD_EN << MXC_F_PWRSEQ_CTRL_VDDIOHMD_POS) /**< CTRL_VDDIOHMD_EN Setting */ 198 #define MXC_V_PWRSEQ_CTRL_VDDIOHMD_DIS ((uint32_t)0x1UL) /**< CTRL_VDDIOHMD_DIS Value */ 199 #define MXC_S_PWRSEQ_CTRL_VDDIOHMD_DIS (MXC_V_PWRSEQ_CTRL_VDDIOHMD_DIS << MXC_F_PWRSEQ_CTRL_VDDIOHMD_POS) /**< CTRL_VDDIOHMD_DIS Setting */ 200 201 #define MXC_F_PWRSEQ_CTRL_PORVDDIOMD_POS 25 /**< CTRL_PORVDDIOMD Position */ 202 #define MXC_F_PWRSEQ_CTRL_PORVDDIOMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_PORVDDIOMD_POS)) /**< CTRL_PORVDDIOMD Mask */ 203 #define MXC_V_PWRSEQ_CTRL_PORVDDIOMD_EN ((uint32_t)0x0UL) /**< CTRL_PORVDDIOMD_EN Value */ 204 #define MXC_S_PWRSEQ_CTRL_PORVDDIOMD_EN (MXC_V_PWRSEQ_CTRL_PORVDDIOMD_EN << MXC_F_PWRSEQ_CTRL_PORVDDIOMD_POS) /**< CTRL_PORVDDIOMD_EN Setting */ 205 #define MXC_V_PWRSEQ_CTRL_PORVDDIOMD_DIS ((uint32_t)0x1UL) /**< CTRL_PORVDDIOMD_DIS Value */ 206 #define MXC_S_PWRSEQ_CTRL_PORVDDIOMD_DIS (MXC_V_PWRSEQ_CTRL_PORVDDIOMD_DIS << MXC_F_PWRSEQ_CTRL_PORVDDIOMD_POS) /**< CTRL_PORVDDIOMD_DIS Setting */ 207 208 #define MXC_F_PWRSEQ_CTRL_PORVDDIOHMD_POS 26 /**< CTRL_PORVDDIOHMD Position */ 209 #define MXC_F_PWRSEQ_CTRL_PORVDDIOHMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_PORVDDIOHMD_POS)) /**< CTRL_PORVDDIOHMD Mask */ 210 #define MXC_V_PWRSEQ_CTRL_PORVDDIOHMD_EN ((uint32_t)0x0UL) /**< CTRL_PORVDDIOHMD_EN Value */ 211 #define MXC_S_PWRSEQ_CTRL_PORVDDIOHMD_EN (MXC_V_PWRSEQ_CTRL_PORVDDIOHMD_EN << MXC_F_PWRSEQ_CTRL_PORVDDIOHMD_POS) /**< CTRL_PORVDDIOHMD_EN Setting */ 212 #define MXC_V_PWRSEQ_CTRL_PORVDDIOHMD_DIS ((uint32_t)0x1UL) /**< CTRL_PORVDDIOHMD_DIS Value */ 213 #define MXC_S_PWRSEQ_CTRL_PORVDDIOHMD_DIS (MXC_V_PWRSEQ_CTRL_PORVDDIOHMD_DIS << MXC_F_PWRSEQ_CTRL_PORVDDIOHMD_POS) /**< CTRL_PORVDDIOHMD_DIS Setting */ 214 215 #define MXC_F_PWRSEQ_CTRL_VDDBMD_POS 27 /**< CTRL_VDDBMD Position */ 216 #define MXC_F_PWRSEQ_CTRL_VDDBMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_VDDBMD_POS)) /**< CTRL_VDDBMD Mask */ 217 #define MXC_V_PWRSEQ_CTRL_VDDBMD_EN ((uint32_t)0x0UL) /**< CTRL_VDDBMD_EN Value */ 218 #define MXC_S_PWRSEQ_CTRL_VDDBMD_EN (MXC_V_PWRSEQ_CTRL_VDDBMD_EN << MXC_F_PWRSEQ_CTRL_VDDBMD_POS) /**< CTRL_VDDBMD_EN Setting */ 219 #define MXC_V_PWRSEQ_CTRL_VDDBMD_DIS ((uint32_t)0x1UL) /**< CTRL_VDDBMD_DIS Value */ 220 #define MXC_S_PWRSEQ_CTRL_VDDBMD_DIS (MXC_V_PWRSEQ_CTRL_VDDBMD_DIS << MXC_F_PWRSEQ_CTRL_VDDBMD_POS) /**< CTRL_VDDBMD_DIS Setting */ 221 222 /**@} end of group PWRSEQ_CTRL_Register */ 223 224 /** 225 * @ingroup pwrseq_registers 226 * @defgroup PWRSEQ_GPIO0_WK_FL PWRSEQ_GPIO0_WK_FL 227 * @brief Low Power I/O Wakeup Status Register 0. This register indicates the low power 228 * wakeup status for GPIO0. 229 * @{ 230 */ 231 #define MXC_F_PWRSEQ_GPIO0_WK_FL_WAKEST_POS 0 /**< GPIO0_WK_FL_WAKEST Position */ 232 #define MXC_F_PWRSEQ_GPIO0_WK_FL_WAKEST ((uint32_t)(0xFFFFFFFFUL << MXC_F_PWRSEQ_GPIO0_WK_FL_WAKEST_POS)) /**< GPIO0_WK_FL_WAKEST Mask */ 233 234 /**@} end of group PWRSEQ_GPIO0_WK_FL_Register */ 235 236 /** 237 * @ingroup pwrseq_registers 238 * @defgroup PWRSEQ_GPIO0_WK_EN PWRSEQ_GPIO0_WK_EN 239 * @brief Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup 240 * functionality for GPIO0. 241 * @{ 242 */ 243 #define MXC_F_PWRSEQ_GPIO0_WK_EN_WAKEEN_POS 0 /**< GPIO0_WK_EN_WAKEEN Position */ 244 #define MXC_F_PWRSEQ_GPIO0_WK_EN_WAKEEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_PWRSEQ_GPIO0_WK_EN_WAKEEN_POS)) /**< GPIO0_WK_EN_WAKEEN Mask */ 245 246 /**@} end of group PWRSEQ_GPIO0_WK_EN_Register */ 247 248 /** 249 * @ingroup pwrseq_registers 250 * @defgroup PWRSEQ_GPIO1_WK_FL PWRSEQ_GPIO1_WK_FL 251 * @brief Low Power I/O Wakeup Status Register 1. This register indicates the low power 252 * wakeup status for GPIO1. 253 * @{ 254 */ 255 #define MXC_F_PWRSEQ_GPIO1_WK_FL_WAKEST_POS 0 /**< GPIO1_WK_FL_WAKEST Position */ 256 #define MXC_F_PWRSEQ_GPIO1_WK_FL_WAKEST ((uint32_t)(0xFFFFFFFFUL << MXC_F_PWRSEQ_GPIO1_WK_FL_WAKEST_POS)) /**< GPIO1_WK_FL_WAKEST Mask */ 257 258 /**@} end of group PWRSEQ_GPIO1_WK_FL_Register */ 259 260 /** 261 * @ingroup pwrseq_registers 262 * @defgroup PWRSEQ_GPIO1_WK_EN PWRSEQ_GPIO1_WK_EN 263 * @brief Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup 264 * functionality for GPIO1. 265 * @{ 266 */ 267 #define MXC_F_PWRSEQ_GPIO1_WK_EN_WAKEEN_POS 0 /**< GPIO1_WK_EN_WAKEEN Position */ 268 #define MXC_F_PWRSEQ_GPIO1_WK_EN_WAKEEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_PWRSEQ_GPIO1_WK_EN_WAKEEN_POS)) /**< GPIO1_WK_EN_WAKEEN Mask */ 269 270 /**@} end of group PWRSEQ_GPIO1_WK_EN_Register */ 271 272 /** 273 * @ingroup pwrseq_registers 274 * @defgroup PWRSEQ_GPIO2_WK_FL PWRSEQ_GPIO2_WK_FL 275 * @brief Low Power I/O Wakeup Status Register 0. This register indicates the low power 276 * wakeup status for GPIO2. 277 * @{ 278 */ 279 #define MXC_F_PWRSEQ_GPIO2_WK_FL_WAKEST_POS 0 /**< GPIO2_WK_FL_WAKEST Position */ 280 #define MXC_F_PWRSEQ_GPIO2_WK_FL_WAKEST ((uint32_t)(0xFFFFFFFFUL << MXC_F_PWRSEQ_GPIO2_WK_FL_WAKEST_POS)) /**< GPIO2_WK_FL_WAKEST Mask */ 281 282 /**@} end of group PWRSEQ_GPIO2_WK_FL_Register */ 283 284 /** 285 * @ingroup pwrseq_registers 286 * @defgroup PWRSEQ_GPIO2_WK_EN PWRSEQ_GPIO2_WK_EN 287 * @brief Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup 288 * functionality for GPIO0. 289 * @{ 290 */ 291 #define MXC_F_PWRSEQ_GPIO2_WK_EN_WAKEEN_POS 0 /**< GPIO2_WK_EN_WAKEEN Position */ 292 #define MXC_F_PWRSEQ_GPIO2_WK_EN_WAKEEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_PWRSEQ_GPIO2_WK_EN_WAKEEN_POS)) /**< GPIO2_WK_EN_WAKEEN Mask */ 293 294 /**@} end of group PWRSEQ_GPIO2_WK_EN_Register */ 295 296 /** 297 * @ingroup pwrseq_registers 298 * @defgroup PWRSEQ_GPIO3_WK_FL PWRSEQ_GPIO3_WK_FL 299 * @brief Low Power I/O Wakeup Status Register 0. This register indicates the low power 300 * wakeup status for GPIO3. 301 * @{ 302 */ 303 #define MXC_F_PWRSEQ_GPIO3_WK_FL_WAKEST_POS 0 /**< GPIO3_WK_FL_WAKEST Position */ 304 #define MXC_F_PWRSEQ_GPIO3_WK_FL_WAKEST ((uint32_t)(0x3FFUL << MXC_F_PWRSEQ_GPIO3_WK_FL_WAKEST_POS)) /**< GPIO3_WK_FL_WAKEST Mask */ 305 306 /**@} end of group PWRSEQ_GPIO3_WK_FL_Register */ 307 308 /** 309 * @ingroup pwrseq_registers 310 * @defgroup PWRSEQ_GPIO3_WK_EN PWRSEQ_GPIO3_WK_EN 311 * @brief Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup 312 * functionality for GPIO3. 313 * @{ 314 */ 315 #define MXC_F_PWRSEQ_GPIO3_WK_EN_WAKEEN_POS 0 /**< GPIO3_WK_EN_WAKEEN Position */ 316 #define MXC_F_PWRSEQ_GPIO3_WK_EN_WAKEEN ((uint32_t)(0x3FFUL << MXC_F_PWRSEQ_GPIO3_WK_EN_WAKEEN_POS)) /**< GPIO3_WK_EN_WAKEEN Mask */ 317 318 /**@} end of group PWRSEQ_GPIO3_WK_EN_Register */ 319 320 /** 321 * @ingroup pwrseq_registers 322 * @defgroup PWRSEQ_USB_WK_FL PWRSEQ_USB_WK_FL 323 * @brief Low Power Peripheral Wakeup Status Register. 324 * @{ 325 */ 326 #define MXC_F_PWRSEQ_USB_WK_FL_USBLSWKST_POS 0 /**< USB_WK_FL_USBLSWKST Position */ 327 #define MXC_F_PWRSEQ_USB_WK_FL_USBLSWKST ((uint32_t)(0x3UL << MXC_F_PWRSEQ_USB_WK_FL_USBLSWKST_POS)) /**< USB_WK_FL_USBLSWKST Mask */ 328 #define MXC_V_PWRSEQ_USB_WK_FL_USBLSWKST_DPLUS ((uint32_t)0x0UL) /**< USB_WK_FL_USBLSWKST_DPLUS Value */ 329 #define MXC_S_PWRSEQ_USB_WK_FL_USBLSWKST_DPLUS (MXC_V_PWRSEQ_USB_WK_FL_USBLSWKST_DPLUS << MXC_F_PWRSEQ_USB_WK_FL_USBLSWKST_POS) /**< USB_WK_FL_USBLSWKST_DPLUS Setting */ 330 #define MXC_V_PWRSEQ_USB_WK_FL_USBLSWKST_DMINUS ((uint32_t)0x1UL) /**< USB_WK_FL_USBLSWKST_DMINUS Value */ 331 #define MXC_S_PWRSEQ_USB_WK_FL_USBLSWKST_DMINUS (MXC_V_PWRSEQ_USB_WK_FL_USBLSWKST_DMINUS << MXC_F_PWRSEQ_USB_WK_FL_USBLSWKST_POS) /**< USB_WK_FL_USBLSWKST_DMINUS Setting */ 332 333 #define MXC_F_PWRSEQ_USB_WK_FL_USBVBUSWKST_POS 2 /**< USB_WK_FL_USBVBUSWKST Position */ 334 #define MXC_F_PWRSEQ_USB_WK_FL_USBVBUSWKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_USB_WK_FL_USBVBUSWKST_POS)) /**< USB_WK_FL_USBVBUSWKST Mask */ 335 #define MXC_V_PWRSEQ_USB_WK_FL_USBVBUSWKST_NORMAL ((uint32_t)0x0UL) /**< USB_WK_FL_USBVBUSWKST_NORMAL Value */ 336 #define MXC_S_PWRSEQ_USB_WK_FL_USBVBUSWKST_NORMAL (MXC_V_PWRSEQ_USB_WK_FL_USBVBUSWKST_NORMAL << MXC_F_PWRSEQ_USB_WK_FL_USBVBUSWKST_POS) /**< USB_WK_FL_USBVBUSWKST_NORMAL Setting */ 337 #define MXC_V_PWRSEQ_USB_WK_FL_USBVBUSWKST_STCHNG ((uint32_t)0x1UL) /**< USB_WK_FL_USBVBUSWKST_STCHNG Value */ 338 #define MXC_S_PWRSEQ_USB_WK_FL_USBVBUSWKST_STCHNG (MXC_V_PWRSEQ_USB_WK_FL_USBVBUSWKST_STCHNG << MXC_F_PWRSEQ_USB_WK_FL_USBVBUSWKST_POS) /**< USB_WK_FL_USBVBUSWKST_STCHNG Setting */ 339 340 /**@} end of group PWRSEQ_USB_WK_FL_Register */ 341 342 /** 343 * @ingroup pwrseq_registers 344 * @defgroup PWRSEQ_USB_WK_EN PWRSEQ_USB_WK_EN 345 * @brief Low Power Peripheral Wakeup Enable Register. 346 * @{ 347 */ 348 #define MXC_F_PWRSEQ_USB_WK_EN_USBLSWKEN_POS 0 /**< USB_WK_EN_USBLSWKEN Position */ 349 #define MXC_F_PWRSEQ_USB_WK_EN_USBLSWKEN ((uint32_t)(0x3UL << MXC_F_PWRSEQ_USB_WK_EN_USBLSWKEN_POS)) /**< USB_WK_EN_USBLSWKEN Mask */ 350 #define MXC_V_PWRSEQ_USB_WK_EN_USBLSWKEN_DIS ((uint32_t)0x0UL) /**< USB_WK_EN_USBLSWKEN_DIS Value */ 351 #define MXC_S_PWRSEQ_USB_WK_EN_USBLSWKEN_DIS (MXC_V_PWRSEQ_USB_WK_EN_USBLSWKEN_DIS << MXC_F_PWRSEQ_USB_WK_EN_USBLSWKEN_POS) /**< USB_WK_EN_USBLSWKEN_DIS Setting */ 352 #define MXC_V_PWRSEQ_USB_WK_EN_USBLSWKEN_EN ((uint32_t)0x3UL) /**< USB_WK_EN_USBLSWKEN_EN Value */ 353 #define MXC_S_PWRSEQ_USB_WK_EN_USBLSWKEN_EN (MXC_V_PWRSEQ_USB_WK_EN_USBLSWKEN_EN << MXC_F_PWRSEQ_USB_WK_EN_USBLSWKEN_POS) /**< USB_WK_EN_USBLSWKEN_EN Setting */ 354 355 #define MXC_F_PWRSEQ_USB_WK_EN_USBVBUSWKEN_POS 2 /**< USB_WK_EN_USBVBUSWKEN Position */ 356 #define MXC_F_PWRSEQ_USB_WK_EN_USBVBUSWKEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_USB_WK_EN_USBVBUSWKEN_POS)) /**< USB_WK_EN_USBVBUSWKEN Mask */ 357 #define MXC_V_PWRSEQ_USB_WK_EN_USBVBUSWKEN_DIS ((uint32_t)0x0UL) /**< USB_WK_EN_USBVBUSWKEN_DIS Value */ 358 #define MXC_S_PWRSEQ_USB_WK_EN_USBVBUSWKEN_DIS (MXC_V_PWRSEQ_USB_WK_EN_USBVBUSWKEN_DIS << MXC_F_PWRSEQ_USB_WK_EN_USBVBUSWKEN_POS) /**< USB_WK_EN_USBVBUSWKEN_DIS Setting */ 359 #define MXC_V_PWRSEQ_USB_WK_EN_USBVBUSWKEN_EN ((uint32_t)0x1UL) /**< USB_WK_EN_USBVBUSWKEN_EN Value */ 360 #define MXC_S_PWRSEQ_USB_WK_EN_USBVBUSWKEN_EN (MXC_V_PWRSEQ_USB_WK_EN_USBVBUSWKEN_EN << MXC_F_PWRSEQ_USB_WK_EN_USBVBUSWKEN_POS) /**< USB_WK_EN_USBVBUSWKEN_EN Setting */ 361 362 /**@} end of group PWRSEQ_USB_WK_EN_Register */ 363 364 /** 365 * @ingroup pwrseq_registers 366 * @defgroup PWRSEQ_MEM_PWR PWRSEQ_MEM_PWR 367 * @brief Low Power Memory Shutdown Control. 368 * @{ 369 */ 370 #define MXC_F_PWRSEQ_MEM_PWR_SRAM0SD_POS 0 /**< MEM_PWR_SRAM0SD Position */ 371 #define MXC_F_PWRSEQ_MEM_PWR_SRAM0SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_SRAM0SD_POS)) /**< MEM_PWR_SRAM0SD Mask */ 372 #define MXC_V_PWRSEQ_MEM_PWR_SRAM0SD_NORMAL ((uint32_t)0x0UL) /**< MEM_PWR_SRAM0SD_NORMAL Value */ 373 #define MXC_S_PWRSEQ_MEM_PWR_SRAM0SD_NORMAL (MXC_V_PWRSEQ_MEM_PWR_SRAM0SD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_SRAM0SD_POS) /**< MEM_PWR_SRAM0SD_NORMAL Setting */ 374 #define MXC_V_PWRSEQ_MEM_PWR_SRAM0SD_SHUTDOWN ((uint32_t)0x1UL) /**< MEM_PWR_SRAM0SD_SHUTDOWN Value */ 375 #define MXC_S_PWRSEQ_MEM_PWR_SRAM0SD_SHUTDOWN (MXC_V_PWRSEQ_MEM_PWR_SRAM0SD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_SRAM0SD_POS) /**< MEM_PWR_SRAM0SD_SHUTDOWN Setting */ 376 377 #define MXC_F_PWRSEQ_MEM_PWR_SRAM1SD_POS 1 /**< MEM_PWR_SRAM1SD Position */ 378 #define MXC_F_PWRSEQ_MEM_PWR_SRAM1SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_SRAM1SD_POS)) /**< MEM_PWR_SRAM1SD Mask */ 379 #define MXC_V_PWRSEQ_MEM_PWR_SRAM1SD_NORMAL ((uint32_t)0x0UL) /**< MEM_PWR_SRAM1SD_NORMAL Value */ 380 #define MXC_S_PWRSEQ_MEM_PWR_SRAM1SD_NORMAL (MXC_V_PWRSEQ_MEM_PWR_SRAM1SD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_SRAM1SD_POS) /**< MEM_PWR_SRAM1SD_NORMAL Setting */ 381 #define MXC_V_PWRSEQ_MEM_PWR_SRAM1SD_SHUTDOWN ((uint32_t)0x1UL) /**< MEM_PWR_SRAM1SD_SHUTDOWN Value */ 382 #define MXC_S_PWRSEQ_MEM_PWR_SRAM1SD_SHUTDOWN (MXC_V_PWRSEQ_MEM_PWR_SRAM1SD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_SRAM1SD_POS) /**< MEM_PWR_SRAM1SD_SHUTDOWN Setting */ 383 384 #define MXC_F_PWRSEQ_MEM_PWR_SRAM2SD_POS 2 /**< MEM_PWR_SRAM2SD Position */ 385 #define MXC_F_PWRSEQ_MEM_PWR_SRAM2SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_SRAM2SD_POS)) /**< MEM_PWR_SRAM2SD Mask */ 386 #define MXC_V_PWRSEQ_MEM_PWR_SRAM2SD_NORMAL ((uint32_t)0x0UL) /**< MEM_PWR_SRAM2SD_NORMAL Value */ 387 #define MXC_S_PWRSEQ_MEM_PWR_SRAM2SD_NORMAL (MXC_V_PWRSEQ_MEM_PWR_SRAM2SD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_SRAM2SD_POS) /**< MEM_PWR_SRAM2SD_NORMAL Setting */ 388 #define MXC_V_PWRSEQ_MEM_PWR_SRAM2SD_SHUTDOWN ((uint32_t)0x1UL) /**< MEM_PWR_SRAM2SD_SHUTDOWN Value */ 389 #define MXC_S_PWRSEQ_MEM_PWR_SRAM2SD_SHUTDOWN (MXC_V_PWRSEQ_MEM_PWR_SRAM2SD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_SRAM2SD_POS) /**< MEM_PWR_SRAM2SD_SHUTDOWN Setting */ 390 391 #define MXC_F_PWRSEQ_MEM_PWR_SRAM3SD_POS 3 /**< MEM_PWR_SRAM3SD Position */ 392 #define MXC_F_PWRSEQ_MEM_PWR_SRAM3SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_SRAM3SD_POS)) /**< MEM_PWR_SRAM3SD Mask */ 393 #define MXC_V_PWRSEQ_MEM_PWR_SRAM3SD_NORMAL ((uint32_t)0x0UL) /**< MEM_PWR_SRAM3SD_NORMAL Value */ 394 #define MXC_S_PWRSEQ_MEM_PWR_SRAM3SD_NORMAL (MXC_V_PWRSEQ_MEM_PWR_SRAM3SD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_SRAM3SD_POS) /**< MEM_PWR_SRAM3SD_NORMAL Setting */ 395 #define MXC_V_PWRSEQ_MEM_PWR_SRAM3SD_SHUTDOWN ((uint32_t)0x1UL) /**< MEM_PWR_SRAM3SD_SHUTDOWN Value */ 396 #define MXC_S_PWRSEQ_MEM_PWR_SRAM3SD_SHUTDOWN (MXC_V_PWRSEQ_MEM_PWR_SRAM3SD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_SRAM3SD_POS) /**< MEM_PWR_SRAM3SD_SHUTDOWN Setting */ 397 398 #define MXC_F_PWRSEQ_MEM_PWR_SRAM4SD_POS 4 /**< MEM_PWR_SRAM4SD Position */ 399 #define MXC_F_PWRSEQ_MEM_PWR_SRAM4SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_SRAM4SD_POS)) /**< MEM_PWR_SRAM4SD Mask */ 400 #define MXC_V_PWRSEQ_MEM_PWR_SRAM4SD_NORMAL ((uint32_t)0x0UL) /**< MEM_PWR_SRAM4SD_NORMAL Value */ 401 #define MXC_S_PWRSEQ_MEM_PWR_SRAM4SD_NORMAL (MXC_V_PWRSEQ_MEM_PWR_SRAM4SD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_SRAM4SD_POS) /**< MEM_PWR_SRAM4SD_NORMAL Setting */ 402 #define MXC_V_PWRSEQ_MEM_PWR_SRAM4SD_SHUTDOWN ((uint32_t)0x1UL) /**< MEM_PWR_SRAM4SD_SHUTDOWN Value */ 403 #define MXC_S_PWRSEQ_MEM_PWR_SRAM4SD_SHUTDOWN (MXC_V_PWRSEQ_MEM_PWR_SRAM4SD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_SRAM4SD_POS) /**< MEM_PWR_SRAM4SD_SHUTDOWN Setting */ 404 405 #define MXC_F_PWRSEQ_MEM_PWR_SRAM5SD_POS 5 /**< MEM_PWR_SRAM5SD Position */ 406 #define MXC_F_PWRSEQ_MEM_PWR_SRAM5SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_SRAM5SD_POS)) /**< MEM_PWR_SRAM5SD Mask */ 407 #define MXC_V_PWRSEQ_MEM_PWR_SRAM5SD_NORMAL ((uint32_t)0x0UL) /**< MEM_PWR_SRAM5SD_NORMAL Value */ 408 #define MXC_S_PWRSEQ_MEM_PWR_SRAM5SD_NORMAL (MXC_V_PWRSEQ_MEM_PWR_SRAM5SD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_SRAM5SD_POS) /**< MEM_PWR_SRAM5SD_NORMAL Setting */ 409 #define MXC_V_PWRSEQ_MEM_PWR_SRAM5SD_SHUTDOWN ((uint32_t)0x1UL) /**< MEM_PWR_SRAM5SD_SHUTDOWN Value */ 410 #define MXC_S_PWRSEQ_MEM_PWR_SRAM5SD_SHUTDOWN (MXC_V_PWRSEQ_MEM_PWR_SRAM5SD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_SRAM5SD_POS) /**< MEM_PWR_SRAM5SD_SHUTDOWN Setting */ 411 412 #define MXC_F_PWRSEQ_MEM_PWR_SRAM6SD_POS 6 /**< MEM_PWR_SRAM6SD Position */ 413 #define MXC_F_PWRSEQ_MEM_PWR_SRAM6SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_SRAM6SD_POS)) /**< MEM_PWR_SRAM6SD Mask */ 414 #define MXC_V_PWRSEQ_MEM_PWR_SRAM6SD_NORMAL ((uint32_t)0x0UL) /**< MEM_PWR_SRAM6SD_NORMAL Value */ 415 #define MXC_S_PWRSEQ_MEM_PWR_SRAM6SD_NORMAL (MXC_V_PWRSEQ_MEM_PWR_SRAM6SD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_SRAM6SD_POS) /**< MEM_PWR_SRAM6SD_NORMAL Setting */ 416 #define MXC_V_PWRSEQ_MEM_PWR_SRAM6SD_SHUTDOWN ((uint32_t)0x1UL) /**< MEM_PWR_SRAM6SD_SHUTDOWN Value */ 417 #define MXC_S_PWRSEQ_MEM_PWR_SRAM6SD_SHUTDOWN (MXC_V_PWRSEQ_MEM_PWR_SRAM6SD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_SRAM6SD_POS) /**< MEM_PWR_SRAM6SD_SHUTDOWN Setting */ 418 419 #define MXC_F_PWRSEQ_MEM_PWR_ICACHESD_POS 7 /**< MEM_PWR_ICACHESD Position */ 420 #define MXC_F_PWRSEQ_MEM_PWR_ICACHESD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_ICACHESD_POS)) /**< MEM_PWR_ICACHESD Mask */ 421 #define MXC_V_PWRSEQ_MEM_PWR_ICACHESD_NORMAL ((uint32_t)0x0UL) /**< MEM_PWR_ICACHESD_NORMAL Value */ 422 #define MXC_S_PWRSEQ_MEM_PWR_ICACHESD_NORMAL (MXC_V_PWRSEQ_MEM_PWR_ICACHESD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_ICACHESD_POS) /**< MEM_PWR_ICACHESD_NORMAL Setting */ 423 #define MXC_V_PWRSEQ_MEM_PWR_ICACHESD_SHUTDOWN ((uint32_t)0x1UL) /**< MEM_PWR_ICACHESD_SHUTDOWN Value */ 424 #define MXC_S_PWRSEQ_MEM_PWR_ICACHESD_SHUTDOWN (MXC_V_PWRSEQ_MEM_PWR_ICACHESD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_ICACHESD_POS) /**< MEM_PWR_ICACHESD_SHUTDOWN Setting */ 425 426 #define MXC_F_PWRSEQ_MEM_PWR_ICACHEXIPSD_POS 8 /**< MEM_PWR_ICACHEXIPSD Position */ 427 #define MXC_F_PWRSEQ_MEM_PWR_ICACHEXIPSD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_ICACHEXIPSD_POS)) /**< MEM_PWR_ICACHEXIPSD Mask */ 428 #define MXC_V_PWRSEQ_MEM_PWR_ICACHEXIPSD_NORMAL ((uint32_t)0x0UL) /**< MEM_PWR_ICACHEXIPSD_NORMAL Value */ 429 #define MXC_S_PWRSEQ_MEM_PWR_ICACHEXIPSD_NORMAL (MXC_V_PWRSEQ_MEM_PWR_ICACHEXIPSD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_ICACHEXIPSD_POS) /**< MEM_PWR_ICACHEXIPSD_NORMAL Setting */ 430 #define MXC_V_PWRSEQ_MEM_PWR_ICACHEXIPSD_SHUTDOWN ((uint32_t)0x1UL) /**< MEM_PWR_ICACHEXIPSD_SHUTDOWN Value */ 431 #define MXC_S_PWRSEQ_MEM_PWR_ICACHEXIPSD_SHUTDOWN (MXC_V_PWRSEQ_MEM_PWR_ICACHEXIPSD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_ICACHEXIPSD_POS) /**< MEM_PWR_ICACHEXIPSD_SHUTDOWN Setting */ 432 433 #define MXC_F_PWRSEQ_MEM_PWR_SCACHESD_POS 9 /**< MEM_PWR_SCACHESD Position */ 434 #define MXC_F_PWRSEQ_MEM_PWR_SCACHESD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_SCACHESD_POS)) /**< MEM_PWR_SCACHESD Mask */ 435 #define MXC_V_PWRSEQ_MEM_PWR_SCACHESD_NORMAL ((uint32_t)0x0UL) /**< MEM_PWR_SCACHESD_NORMAL Value */ 436 #define MXC_S_PWRSEQ_MEM_PWR_SCACHESD_NORMAL (MXC_V_PWRSEQ_MEM_PWR_SCACHESD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_SCACHESD_POS) /**< MEM_PWR_SCACHESD_NORMAL Setting */ 437 #define MXC_V_PWRSEQ_MEM_PWR_SCACHESD_SHUTDOWN ((uint32_t)0x1UL) /**< MEM_PWR_SCACHESD_SHUTDOWN Value */ 438 #define MXC_S_PWRSEQ_MEM_PWR_SCACHESD_SHUTDOWN (MXC_V_PWRSEQ_MEM_PWR_SCACHESD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_SCACHESD_POS) /**< MEM_PWR_SCACHESD_SHUTDOWN Setting */ 439 440 #define MXC_F_PWRSEQ_MEM_PWR_CRYPTOSD_POS 10 /**< MEM_PWR_CRYPTOSD Position */ 441 #define MXC_F_PWRSEQ_MEM_PWR_CRYPTOSD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_CRYPTOSD_POS)) /**< MEM_PWR_CRYPTOSD Mask */ 442 #define MXC_V_PWRSEQ_MEM_PWR_CRYPTOSD_NORMAL ((uint32_t)0x0UL) /**< MEM_PWR_CRYPTOSD_NORMAL Value */ 443 #define MXC_S_PWRSEQ_MEM_PWR_CRYPTOSD_NORMAL (MXC_V_PWRSEQ_MEM_PWR_CRYPTOSD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_CRYPTOSD_POS) /**< MEM_PWR_CRYPTOSD_NORMAL Setting */ 444 #define MXC_V_PWRSEQ_MEM_PWR_CRYPTOSD_SHUTDOWN ((uint32_t)0x1UL) /**< MEM_PWR_CRYPTOSD_SHUTDOWN Value */ 445 #define MXC_S_PWRSEQ_MEM_PWR_CRYPTOSD_SHUTDOWN (MXC_V_PWRSEQ_MEM_PWR_CRYPTOSD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_CRYPTOSD_POS) /**< MEM_PWR_CRYPTOSD_SHUTDOWN Setting */ 446 447 #define MXC_F_PWRSEQ_MEM_PWR_USBFIFOSD_POS 11 /**< MEM_PWR_USBFIFOSD Position */ 448 #define MXC_F_PWRSEQ_MEM_PWR_USBFIFOSD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_USBFIFOSD_POS)) /**< MEM_PWR_USBFIFOSD Mask */ 449 #define MXC_V_PWRSEQ_MEM_PWR_USBFIFOSD_NORMAL ((uint32_t)0x0UL) /**< MEM_PWR_USBFIFOSD_NORMAL Value */ 450 #define MXC_S_PWRSEQ_MEM_PWR_USBFIFOSD_NORMAL (MXC_V_PWRSEQ_MEM_PWR_USBFIFOSD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_USBFIFOSD_POS) /**< MEM_PWR_USBFIFOSD_NORMAL Setting */ 451 #define MXC_V_PWRSEQ_MEM_PWR_USBFIFOSD_SHUTDOWN ((uint32_t)0x1UL) /**< MEM_PWR_USBFIFOSD_SHUTDOWN Value */ 452 #define MXC_S_PWRSEQ_MEM_PWR_USBFIFOSD_SHUTDOWN (MXC_V_PWRSEQ_MEM_PWR_USBFIFOSD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_USBFIFOSD_POS) /**< MEM_PWR_USBFIFOSD_SHUTDOWN Setting */ 453 454 #define MXC_F_PWRSEQ_MEM_PWR_ROMSD_POS 12 /**< MEM_PWR_ROMSD Position */ 455 #define MXC_F_PWRSEQ_MEM_PWR_ROMSD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_ROMSD_POS)) /**< MEM_PWR_ROMSD Mask */ 456 #define MXC_V_PWRSEQ_MEM_PWR_ROMSD_NORMAL ((uint32_t)0x0UL) /**< MEM_PWR_ROMSD_NORMAL Value */ 457 #define MXC_S_PWRSEQ_MEM_PWR_ROMSD_NORMAL (MXC_V_PWRSEQ_MEM_PWR_ROMSD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_ROMSD_POS) /**< MEM_PWR_ROMSD_NORMAL Setting */ 458 #define MXC_V_PWRSEQ_MEM_PWR_ROMSD_SHUTDOWN ((uint32_t)0x1UL) /**< MEM_PWR_ROMSD_SHUTDOWN Value */ 459 #define MXC_S_PWRSEQ_MEM_PWR_ROMSD_SHUTDOWN (MXC_V_PWRSEQ_MEM_PWR_ROMSD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_ROMSD_POS) /**< MEM_PWR_ROMSD_SHUTDOWN Setting */ 460 461 /**@} end of group PWRSEQ_MEM_PWR_Register */ 462 463 #ifdef __cplusplus 464 } 465 #endif 466 467 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_PWRSEQ_REGS_H_ 468
