1 /** 2 * @file ptg_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the PTG Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup ptg_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_PTG_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_PTG_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup ptg 67 * @defgroup ptg_registers PTG_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the PTG Peripheral Module. 69 * @details Pulse Train Generation 70 */ 71 72 /** 73 * @ingroup ptg_registers 74 * Structure type to access the PTG Registers. 75 */ 76 typedef struct { 77 __IO uint32_t enable; /**< <tt>\b 0x0000:</tt> PTG ENABLE Register */ 78 __IO uint32_t resync; /**< <tt>\b 0x0004:</tt> PTG RESYNC Register */ 79 __IO uint32_t intfl; /**< <tt>\b 0x0008:</tt> PTG INTFL Register */ 80 __IO uint32_t inten; /**< <tt>\b 0x000C:</tt> PTG INTEN Register */ 81 __O uint32_t safe_en; /**< <tt>\b 0x0010:</tt> PTG SAFE_EN Register */ 82 __O uint32_t safe_dis; /**< <tt>\b 0x0014:</tt> PTG SAFE_DIS Register */ 83 } mxc_ptg_regs_t; 84 85 /* Register offsets for module PTG */ 86 /** 87 * @ingroup ptg_registers 88 * @defgroup PTG_Register_Offsets Register Offsets 89 * @brief PTG Peripheral Register Offsets from the PTG Base Peripheral Address. 90 * @{ 91 */ 92 #define MXC_R_PTG_ENABLE ((uint32_t)0x00000000UL) /**< Offset from PTG Base Address: <tt> 0x0000</tt> */ 93 #define MXC_R_PTG_RESYNC ((uint32_t)0x00000004UL) /**< Offset from PTG Base Address: <tt> 0x0004</tt> */ 94 #define MXC_R_PTG_INTFL ((uint32_t)0x00000008UL) /**< Offset from PTG Base Address: <tt> 0x0008</tt> */ 95 #define MXC_R_PTG_INTEN ((uint32_t)0x0000000CUL) /**< Offset from PTG Base Address: <tt> 0x000C</tt> */ 96 #define MXC_R_PTG_SAFE_EN ((uint32_t)0x00000010UL) /**< Offset from PTG Base Address: <tt> 0x0010</tt> */ 97 #define MXC_R_PTG_SAFE_DIS ((uint32_t)0x00000014UL) /**< Offset from PTG Base Address: <tt> 0x0014</tt> */ 98 /**@} end of group ptg_registers */ 99 100 /** 101 * @ingroup ptg_registers 102 * @defgroup PTG_ENABLE PTG_ENABLE 103 * @brief Global Enable/Disable Controls for All Pulse Trains 104 * @{ 105 */ 106 #define MXC_F_PTG_ENABLE_PT0_POS 0 /**< ENABLE_PT0 Position */ 107 #define MXC_F_PTG_ENABLE_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT0_POS)) /**< ENABLE_PT0 Mask */ 108 109 #define MXC_F_PTG_ENABLE_PT1_POS 1 /**< ENABLE_PT1 Position */ 110 #define MXC_F_PTG_ENABLE_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT1_POS)) /**< ENABLE_PT1 Mask */ 111 112 #define MXC_F_PTG_ENABLE_PT2_POS 2 /**< ENABLE_PT2 Position */ 113 #define MXC_F_PTG_ENABLE_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT2_POS)) /**< ENABLE_PT2 Mask */ 114 115 #define MXC_F_PTG_ENABLE_PT3_POS 3 /**< ENABLE_PT3 Position */ 116 #define MXC_F_PTG_ENABLE_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT3_POS)) /**< ENABLE_PT3 Mask */ 117 118 #define MXC_F_PTG_ENABLE_PT4_POS 4 /**< ENABLE_PT4 Position */ 119 #define MXC_F_PTG_ENABLE_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT4_POS)) /**< ENABLE_PT4 Mask */ 120 121 #define MXC_F_PTG_ENABLE_PT5_POS 5 /**< ENABLE_PT5 Position */ 122 #define MXC_F_PTG_ENABLE_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT5_POS)) /**< ENABLE_PT5 Mask */ 123 124 #define MXC_F_PTG_ENABLE_PT6_POS 6 /**< ENABLE_PT6 Position */ 125 #define MXC_F_PTG_ENABLE_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT6_POS)) /**< ENABLE_PT6 Mask */ 126 127 #define MXC_F_PTG_ENABLE_PT7_POS 7 /**< ENABLE_PT7 Position */ 128 #define MXC_F_PTG_ENABLE_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT7_POS)) /**< ENABLE_PT7 Mask */ 129 130 #define MXC_F_PTG_ENABLE_PT8_POS 8 /**< ENABLE_PT8 Position */ 131 #define MXC_F_PTG_ENABLE_PT8 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT8_POS)) /**< ENABLE_PT8 Mask */ 132 133 #define MXC_F_PTG_ENABLE_PT9_POS 9 /**< ENABLE_PT9 Position */ 134 #define MXC_F_PTG_ENABLE_PT9 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT9_POS)) /**< ENABLE_PT9 Mask */ 135 136 #define MXC_F_PTG_ENABLE_PT10_POS 10 /**< ENABLE_PT10 Position */ 137 #define MXC_F_PTG_ENABLE_PT10 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT10_POS)) /**< ENABLE_PT10 Mask */ 138 139 #define MXC_F_PTG_ENABLE_PT11_POS 11 /**< ENABLE_PT11 Position */ 140 #define MXC_F_PTG_ENABLE_PT11 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT11_POS)) /**< ENABLE_PT11 Mask */ 141 142 #define MXC_F_PTG_ENABLE_PT12_POS 12 /**< ENABLE_PT12 Position */ 143 #define MXC_F_PTG_ENABLE_PT12 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT12_POS)) /**< ENABLE_PT12 Mask */ 144 145 #define MXC_F_PTG_ENABLE_PT13_POS 13 /**< ENABLE_PT13 Position */ 146 #define MXC_F_PTG_ENABLE_PT13 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT13_POS)) /**< ENABLE_PT13 Mask */ 147 148 #define MXC_F_PTG_ENABLE_PT14_POS 14 /**< ENABLE_PT14 Position */ 149 #define MXC_F_PTG_ENABLE_PT14 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT14_POS)) /**< ENABLE_PT14 Mask */ 150 151 #define MXC_F_PTG_ENABLE_PT15_POS 15 /**< ENABLE_PT15 Position */ 152 #define MXC_F_PTG_ENABLE_PT15 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT15_POS)) /**< ENABLE_PT15 Mask */ 153 154 /**@} end of group PTG_ENABLE_Register */ 155 156 /** 157 * @ingroup ptg_registers 158 * @defgroup PTG_RESYNC PTG_RESYNC 159 * @brief Global Resync (All Pulse Trains) Control 160 * @{ 161 */ 162 #define MXC_F_PTG_RESYNC_PT0_POS 0 /**< RESYNC_PT0 Position */ 163 #define MXC_F_PTG_RESYNC_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT0_POS)) /**< RESYNC_PT0 Mask */ 164 165 #define MXC_F_PTG_RESYNC_PT1_POS 1 /**< RESYNC_PT1 Position */ 166 #define MXC_F_PTG_RESYNC_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT1_POS)) /**< RESYNC_PT1 Mask */ 167 168 #define MXC_F_PTG_RESYNC_PT2_POS 2 /**< RESYNC_PT2 Position */ 169 #define MXC_F_PTG_RESYNC_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT2_POS)) /**< RESYNC_PT2 Mask */ 170 171 #define MXC_F_PTG_RESYNC_PT3_POS 3 /**< RESYNC_PT3 Position */ 172 #define MXC_F_PTG_RESYNC_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT3_POS)) /**< RESYNC_PT3 Mask */ 173 174 #define MXC_F_PTG_RESYNC_PT4_POS 4 /**< RESYNC_PT4 Position */ 175 #define MXC_F_PTG_RESYNC_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT4_POS)) /**< RESYNC_PT4 Mask */ 176 177 #define MXC_F_PTG_RESYNC_PT5_POS 5 /**< RESYNC_PT5 Position */ 178 #define MXC_F_PTG_RESYNC_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT5_POS)) /**< RESYNC_PT5 Mask */ 179 180 #define MXC_F_PTG_RESYNC_PT6_POS 6 /**< RESYNC_PT6 Position */ 181 #define MXC_F_PTG_RESYNC_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT6_POS)) /**< RESYNC_PT6 Mask */ 182 183 #define MXC_F_PTG_RESYNC_PT7_POS 7 /**< RESYNC_PT7 Position */ 184 #define MXC_F_PTG_RESYNC_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT7_POS)) /**< RESYNC_PT7 Mask */ 185 186 #define MXC_F_PTG_RESYNC_PT8_POS 8 /**< RESYNC_PT8 Position */ 187 #define MXC_F_PTG_RESYNC_PT8 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT8_POS)) /**< RESYNC_PT8 Mask */ 188 189 #define MXC_F_PTG_RESYNC_PT9_POS 9 /**< RESYNC_PT9 Position */ 190 #define MXC_F_PTG_RESYNC_PT9 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT9_POS)) /**< RESYNC_PT9 Mask */ 191 192 #define MXC_F_PTG_RESYNC_PT10_POS 10 /**< RESYNC_PT10 Position */ 193 #define MXC_F_PTG_RESYNC_PT10 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT10_POS)) /**< RESYNC_PT10 Mask */ 194 195 #define MXC_F_PTG_RESYNC_PT11_POS 11 /**< RESYNC_PT11 Position */ 196 #define MXC_F_PTG_RESYNC_PT11 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT11_POS)) /**< RESYNC_PT11 Mask */ 197 198 #define MXC_F_PTG_RESYNC_PT12_POS 12 /**< RESYNC_PT12 Position */ 199 #define MXC_F_PTG_RESYNC_PT12 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT12_POS)) /**< RESYNC_PT12 Mask */ 200 201 #define MXC_F_PTG_RESYNC_PT13_POS 13 /**< RESYNC_PT13 Position */ 202 #define MXC_F_PTG_RESYNC_PT13 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT13_POS)) /**< RESYNC_PT13 Mask */ 203 204 #define MXC_F_PTG_RESYNC_PT14_POS 14 /**< RESYNC_PT14 Position */ 205 #define MXC_F_PTG_RESYNC_PT14 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT14_POS)) /**< RESYNC_PT14 Mask */ 206 207 #define MXC_F_PTG_RESYNC_PT15_POS 15 /**< RESYNC_PT15 Position */ 208 #define MXC_F_PTG_RESYNC_PT15 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT15_POS)) /**< RESYNC_PT15 Mask */ 209 210 /**@} end of group PTG_RESYNC_Register */ 211 212 /** 213 * @ingroup ptg_registers 214 * @defgroup PTG_INTFL PTG_INTFL 215 * @brief Pulse Train Interrupt Flags 216 * @{ 217 */ 218 #define MXC_F_PTG_INTFL_PT0_POS 0 /**< INTFL_PT0 Position */ 219 #define MXC_F_PTG_INTFL_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT0_POS)) /**< INTFL_PT0 Mask */ 220 221 #define MXC_F_PTG_INTFL_PT1_POS 1 /**< INTFL_PT1 Position */ 222 #define MXC_F_PTG_INTFL_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT1_POS)) /**< INTFL_PT1 Mask */ 223 224 #define MXC_F_PTG_INTFL_PT2_POS 2 /**< INTFL_PT2 Position */ 225 #define MXC_F_PTG_INTFL_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT2_POS)) /**< INTFL_PT2 Mask */ 226 227 #define MXC_F_PTG_INTFL_PT3_POS 3 /**< INTFL_PT3 Position */ 228 #define MXC_F_PTG_INTFL_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT3_POS)) /**< INTFL_PT3 Mask */ 229 230 #define MXC_F_PTG_INTFL_PT4_POS 4 /**< INTFL_PT4 Position */ 231 #define MXC_F_PTG_INTFL_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT4_POS)) /**< INTFL_PT4 Mask */ 232 233 #define MXC_F_PTG_INTFL_PT5_POS 5 /**< INTFL_PT5 Position */ 234 #define MXC_F_PTG_INTFL_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT5_POS)) /**< INTFL_PT5 Mask */ 235 236 #define MXC_F_PTG_INTFL_PT6_POS 6 /**< INTFL_PT6 Position */ 237 #define MXC_F_PTG_INTFL_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT6_POS)) /**< INTFL_PT6 Mask */ 238 239 #define MXC_F_PTG_INTFL_PT7_POS 7 /**< INTFL_PT7 Position */ 240 #define MXC_F_PTG_INTFL_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT7_POS)) /**< INTFL_PT7 Mask */ 241 242 #define MXC_F_PTG_INTFL_PT8_POS 8 /**< INTFL_PT8 Position */ 243 #define MXC_F_PTG_INTFL_PT8 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT8_POS)) /**< INTFL_PT8 Mask */ 244 245 #define MXC_F_PTG_INTFL_PT9_POS 9 /**< INTFL_PT9 Position */ 246 #define MXC_F_PTG_INTFL_PT9 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT9_POS)) /**< INTFL_PT9 Mask */ 247 248 #define MXC_F_PTG_INTFL_PT10_POS 10 /**< INTFL_PT10 Position */ 249 #define MXC_F_PTG_INTFL_PT10 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT10_POS)) /**< INTFL_PT10 Mask */ 250 251 #define MXC_F_PTG_INTFL_PT11_POS 11 /**< INTFL_PT11 Position */ 252 #define MXC_F_PTG_INTFL_PT11 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT11_POS)) /**< INTFL_PT11 Mask */ 253 254 #define MXC_F_PTG_INTFL_PT12_POS 12 /**< INTFL_PT12 Position */ 255 #define MXC_F_PTG_INTFL_PT12 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT12_POS)) /**< INTFL_PT12 Mask */ 256 257 #define MXC_F_PTG_INTFL_PT13_POS 13 /**< INTFL_PT13 Position */ 258 #define MXC_F_PTG_INTFL_PT13 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT13_POS)) /**< INTFL_PT13 Mask */ 259 260 #define MXC_F_PTG_INTFL_PT14_POS 14 /**< INTFL_PT14 Position */ 261 #define MXC_F_PTG_INTFL_PT14 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT14_POS)) /**< INTFL_PT14 Mask */ 262 263 #define MXC_F_PTG_INTFL_PT15_POS 15 /**< INTFL_PT15 Position */ 264 #define MXC_F_PTG_INTFL_PT15 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT15_POS)) /**< INTFL_PT15 Mask */ 265 266 /**@} end of group PTG_INTFL_Register */ 267 268 /** 269 * @ingroup ptg_registers 270 * @defgroup PTG_INTEN PTG_INTEN 271 * @brief Pulse Train Interrupt Enable/Disable 272 * @{ 273 */ 274 #define MXC_F_PTG_INTEN_PT0_POS 0 /**< INTEN_PT0 Position */ 275 #define MXC_F_PTG_INTEN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT0_POS)) /**< INTEN_PT0 Mask */ 276 277 #define MXC_F_PTG_INTEN_PT1_POS 1 /**< INTEN_PT1 Position */ 278 #define MXC_F_PTG_INTEN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT1_POS)) /**< INTEN_PT1 Mask */ 279 280 #define MXC_F_PTG_INTEN_PT2_POS 2 /**< INTEN_PT2 Position */ 281 #define MXC_F_PTG_INTEN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT2_POS)) /**< INTEN_PT2 Mask */ 282 283 #define MXC_F_PTG_INTEN_PT3_POS 3 /**< INTEN_PT3 Position */ 284 #define MXC_F_PTG_INTEN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT3_POS)) /**< INTEN_PT3 Mask */ 285 286 #define MXC_F_PTG_INTEN_PT4_POS 4 /**< INTEN_PT4 Position */ 287 #define MXC_F_PTG_INTEN_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT4_POS)) /**< INTEN_PT4 Mask */ 288 289 #define MXC_F_PTG_INTEN_PT5_POS 5 /**< INTEN_PT5 Position */ 290 #define MXC_F_PTG_INTEN_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT5_POS)) /**< INTEN_PT5 Mask */ 291 292 #define MXC_F_PTG_INTEN_PT6_POS 6 /**< INTEN_PT6 Position */ 293 #define MXC_F_PTG_INTEN_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT6_POS)) /**< INTEN_PT6 Mask */ 294 295 #define MXC_F_PTG_INTEN_PT7_POS 7 /**< INTEN_PT7 Position */ 296 #define MXC_F_PTG_INTEN_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT7_POS)) /**< INTEN_PT7 Mask */ 297 298 #define MXC_F_PTG_INTEN_PT8_POS 8 /**< INTEN_PT8 Position */ 299 #define MXC_F_PTG_INTEN_PT8 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT8_POS)) /**< INTEN_PT8 Mask */ 300 301 #define MXC_F_PTG_INTEN_PT9_POS 9 /**< INTEN_PT9 Position */ 302 #define MXC_F_PTG_INTEN_PT9 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT9_POS)) /**< INTEN_PT9 Mask */ 303 304 #define MXC_F_PTG_INTEN_PT10_POS 10 /**< INTEN_PT10 Position */ 305 #define MXC_F_PTG_INTEN_PT10 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT10_POS)) /**< INTEN_PT10 Mask */ 306 307 #define MXC_F_PTG_INTEN_PT11_POS 11 /**< INTEN_PT11 Position */ 308 #define MXC_F_PTG_INTEN_PT11 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT11_POS)) /**< INTEN_PT11 Mask */ 309 310 #define MXC_F_PTG_INTEN_PT12_POS 12 /**< INTEN_PT12 Position */ 311 #define MXC_F_PTG_INTEN_PT12 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT12_POS)) /**< INTEN_PT12 Mask */ 312 313 #define MXC_F_PTG_INTEN_PT13_POS 13 /**< INTEN_PT13 Position */ 314 #define MXC_F_PTG_INTEN_PT13 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT13_POS)) /**< INTEN_PT13 Mask */ 315 316 #define MXC_F_PTG_INTEN_PT14_POS 14 /**< INTEN_PT14 Position */ 317 #define MXC_F_PTG_INTEN_PT14 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT14_POS)) /**< INTEN_PT14 Mask */ 318 319 #define MXC_F_PTG_INTEN_PT15_POS 15 /**< INTEN_PT15 Position */ 320 #define MXC_F_PTG_INTEN_PT15 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT15_POS)) /**< INTEN_PT15 Mask */ 321 322 /**@} end of group PTG_INTEN_Register */ 323 324 /** 325 * @ingroup ptg_registers 326 * @defgroup PTG_SAFE_EN PTG_SAFE_EN 327 * @brief Pulse Train Global Safe Enable. 328 * @{ 329 */ 330 #define MXC_F_PTG_SAFE_EN_PT0_POS 0 /**< SAFE_EN_PT0 Position */ 331 #define MXC_F_PTG_SAFE_EN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT0_POS)) /**< SAFE_EN_PT0 Mask */ 332 333 #define MXC_F_PTG_SAFE_EN_PT1_POS 1 /**< SAFE_EN_PT1 Position */ 334 #define MXC_F_PTG_SAFE_EN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT1_POS)) /**< SAFE_EN_PT1 Mask */ 335 336 #define MXC_F_PTG_SAFE_EN_PT2_POS 2 /**< SAFE_EN_PT2 Position */ 337 #define MXC_F_PTG_SAFE_EN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT2_POS)) /**< SAFE_EN_PT2 Mask */ 338 339 #define MXC_F_PTG_SAFE_EN_PT3_POS 3 /**< SAFE_EN_PT3 Position */ 340 #define MXC_F_PTG_SAFE_EN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT3_POS)) /**< SAFE_EN_PT3 Mask */ 341 342 #define MXC_F_PTG_SAFE_EN_PT4_POS 4 /**< SAFE_EN_PT4 Position */ 343 #define MXC_F_PTG_SAFE_EN_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT4_POS)) /**< SAFE_EN_PT4 Mask */ 344 345 #define MXC_F_PTG_SAFE_EN_PT5_POS 5 /**< SAFE_EN_PT5 Position */ 346 #define MXC_F_PTG_SAFE_EN_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT5_POS)) /**< SAFE_EN_PT5 Mask */ 347 348 #define MXC_F_PTG_SAFE_EN_PT6_POS 6 /**< SAFE_EN_PT6 Position */ 349 #define MXC_F_PTG_SAFE_EN_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT6_POS)) /**< SAFE_EN_PT6 Mask */ 350 351 #define MXC_F_PTG_SAFE_EN_PT7_POS 7 /**< SAFE_EN_PT7 Position */ 352 #define MXC_F_PTG_SAFE_EN_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT7_POS)) /**< SAFE_EN_PT7 Mask */ 353 354 #define MXC_F_PTG_SAFE_EN_PT8_POS 8 /**< SAFE_EN_PT8 Position */ 355 #define MXC_F_PTG_SAFE_EN_PT8 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT8_POS)) /**< SAFE_EN_PT8 Mask */ 356 357 #define MXC_F_PTG_SAFE_EN_PT9_POS 9 /**< SAFE_EN_PT9 Position */ 358 #define MXC_F_PTG_SAFE_EN_PT9 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT9_POS)) /**< SAFE_EN_PT9 Mask */ 359 360 #define MXC_F_PTG_SAFE_EN_PT10_POS 10 /**< SAFE_EN_PT10 Position */ 361 #define MXC_F_PTG_SAFE_EN_PT10 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT10_POS)) /**< SAFE_EN_PT10 Mask */ 362 363 #define MXC_F_PTG_SAFE_EN_PT11_POS 11 /**< SAFE_EN_PT11 Position */ 364 #define MXC_F_PTG_SAFE_EN_PT11 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT11_POS)) /**< SAFE_EN_PT11 Mask */ 365 366 #define MXC_F_PTG_SAFE_EN_PT12_POS 12 /**< SAFE_EN_PT12 Position */ 367 #define MXC_F_PTG_SAFE_EN_PT12 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT12_POS)) /**< SAFE_EN_PT12 Mask */ 368 369 #define MXC_F_PTG_SAFE_EN_PT13_POS 13 /**< SAFE_EN_PT13 Position */ 370 #define MXC_F_PTG_SAFE_EN_PT13 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT13_POS)) /**< SAFE_EN_PT13 Mask */ 371 372 #define MXC_F_PTG_SAFE_EN_PT14_POS 14 /**< SAFE_EN_PT14 Position */ 373 #define MXC_F_PTG_SAFE_EN_PT14 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT14_POS)) /**< SAFE_EN_PT14 Mask */ 374 375 #define MXC_F_PTG_SAFE_EN_PT15_POS 15 /**< SAFE_EN_PT15 Position */ 376 #define MXC_F_PTG_SAFE_EN_PT15 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT15_POS)) /**< SAFE_EN_PT15 Mask */ 377 378 /**@} end of group PTG_SAFE_EN_Register */ 379 380 /** 381 * @ingroup ptg_registers 382 * @defgroup PTG_SAFE_DIS PTG_SAFE_DIS 383 * @brief Pulse Train Global Safe Disable. 384 * @{ 385 */ 386 #define MXC_F_PTG_SAFE_DIS_PT0_POS 0 /**< SAFE_DIS_PT0 Position */ 387 #define MXC_F_PTG_SAFE_DIS_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT0_POS)) /**< SAFE_DIS_PT0 Mask */ 388 389 #define MXC_F_PTG_SAFE_DIS_PT1_POS 1 /**< SAFE_DIS_PT1 Position */ 390 #define MXC_F_PTG_SAFE_DIS_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT1_POS)) /**< SAFE_DIS_PT1 Mask */ 391 392 #define MXC_F_PTG_SAFE_DIS_PT2_POS 2 /**< SAFE_DIS_PT2 Position */ 393 #define MXC_F_PTG_SAFE_DIS_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT2_POS)) /**< SAFE_DIS_PT2 Mask */ 394 395 #define MXC_F_PTG_SAFE_DIS_PT3_POS 3 /**< SAFE_DIS_PT3 Position */ 396 #define MXC_F_PTG_SAFE_DIS_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT3_POS)) /**< SAFE_DIS_PT3 Mask */ 397 398 #define MXC_F_PTG_SAFE_DIS_PT4_POS 4 /**< SAFE_DIS_PT4 Position */ 399 #define MXC_F_PTG_SAFE_DIS_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT4_POS)) /**< SAFE_DIS_PT4 Mask */ 400 401 #define MXC_F_PTG_SAFE_DIS_PT5_POS 5 /**< SAFE_DIS_PT5 Position */ 402 #define MXC_F_PTG_SAFE_DIS_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT5_POS)) /**< SAFE_DIS_PT5 Mask */ 403 404 #define MXC_F_PTG_SAFE_DIS_PT6_POS 6 /**< SAFE_DIS_PT6 Position */ 405 #define MXC_F_PTG_SAFE_DIS_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT6_POS)) /**< SAFE_DIS_PT6 Mask */ 406 407 #define MXC_F_PTG_SAFE_DIS_PT7_POS 7 /**< SAFE_DIS_PT7 Position */ 408 #define MXC_F_PTG_SAFE_DIS_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT7_POS)) /**< SAFE_DIS_PT7 Mask */ 409 410 #define MXC_F_PTG_SAFE_DIS_PT8_POS 8 /**< SAFE_DIS_PT8 Position */ 411 #define MXC_F_PTG_SAFE_DIS_PT8 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT8_POS)) /**< SAFE_DIS_PT8 Mask */ 412 413 #define MXC_F_PTG_SAFE_DIS_PT9_POS 9 /**< SAFE_DIS_PT9 Position */ 414 #define MXC_F_PTG_SAFE_DIS_PT9 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT9_POS)) /**< SAFE_DIS_PT9 Mask */ 415 416 #define MXC_F_PTG_SAFE_DIS_PT10_POS 10 /**< SAFE_DIS_PT10 Position */ 417 #define MXC_F_PTG_SAFE_DIS_PT10 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT10_POS)) /**< SAFE_DIS_PT10 Mask */ 418 419 #define MXC_F_PTG_SAFE_DIS_PT11_POS 11 /**< SAFE_DIS_PT11 Position */ 420 #define MXC_F_PTG_SAFE_DIS_PT11 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT11_POS)) /**< SAFE_DIS_PT11 Mask */ 421 422 #define MXC_F_PTG_SAFE_DIS_PT12_POS 12 /**< SAFE_DIS_PT12 Position */ 423 #define MXC_F_PTG_SAFE_DIS_PT12 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT12_POS)) /**< SAFE_DIS_PT12 Mask */ 424 425 #define MXC_F_PTG_SAFE_DIS_PT13_POS 13 /**< SAFE_DIS_PT13 Position */ 426 #define MXC_F_PTG_SAFE_DIS_PT13 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT13_POS)) /**< SAFE_DIS_PT13 Mask */ 427 428 #define MXC_F_PTG_SAFE_DIS_PT14_POS 14 /**< SAFE_DIS_PT14 Position */ 429 #define MXC_F_PTG_SAFE_DIS_PT14 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT14_POS)) /**< SAFE_DIS_PT14 Mask */ 430 431 #define MXC_F_PTG_SAFE_DIS_PT15_POS 15 /**< SAFE_DIS_PT15 Position */ 432 #define MXC_F_PTG_SAFE_DIS_PT15 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT15_POS)) /**< SAFE_DIS_PT15 Mask */ 433 434 /**@} end of group PTG_SAFE_DIS_Register */ 435 436 #ifdef __cplusplus 437 } 438 #endif 439 440 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_PTG_REGS_H_ 441
