1 /** 2 * @file hpb_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the HPB Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup hpb_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_HPB_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_HPB_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup hpb 67 * @defgroup hpb_registers HPB_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the HPB Peripheral Module. 69 * @details HyperBus Memory Controller 70 */ 71 72 /** 73 * @ingroup hpb_registers 74 * Structure type to access the HPB Registers. 75 */ 76 typedef struct { 77 __IO uint32_t status; /**< <tt>\b 0x00:</tt> HPB STATUS Register */ 78 __IO uint32_t inten; /**< <tt>\b 0x04:</tt> HPB INTEN Register */ 79 __IO uint32_t intfl; /**< <tt>\b 0x08:</tt> HPB INTFL Register */ 80 __R uint32_t rsv_0xc; 81 __IO uint32_t mbr[2]; /**< <tt>\b 0x10:</tt> HPB MBR Register */ 82 __R uint32_t rsv_0x18_0x1f[2]; 83 __IO uint32_t mcr[2]; /**< <tt>\b 0x20:</tt> HPB MCR Register */ 84 __R uint32_t rsv_0x28_0x2f[2]; 85 __IO uint32_t mtr[2]; /**< <tt>\b 0x30:</tt> HPB MTR Register */ 86 } mxc_hpb_regs_t; 87 88 /* Register offsets for module HPB */ 89 /** 90 * @ingroup hpb_registers 91 * @defgroup HPB_Register_Offsets Register Offsets 92 * @brief HPB Peripheral Register Offsets from the HPB Base Peripheral Address. 93 * @{ 94 */ 95 #define MXC_R_HPB_STATUS ((uint32_t)0x00000000UL) /**< Offset from HPB Base Address: <tt> 0x0000</tt> */ 96 #define MXC_R_HPB_INTEN ((uint32_t)0x00000004UL) /**< Offset from HPB Base Address: <tt> 0x0004</tt> */ 97 #define MXC_R_HPB_INTFL ((uint32_t)0x00000008UL) /**< Offset from HPB Base Address: <tt> 0x0008</tt> */ 98 #define MXC_R_HPB_MBR ((uint32_t)0x00000010UL) /**< Offset from HPB Base Address: <tt> 0x0010</tt> */ 99 #define MXC_R_HPB_MCR ((uint32_t)0x00000020UL) /**< Offset from HPB Base Address: <tt> 0x0020</tt> */ 100 #define MXC_R_HPB_MTR ((uint32_t)0x00000030UL) /**< Offset from HPB Base Address: <tt> 0x0030</tt> */ 101 /**@} end of group hpb_registers */ 102 103 /** 104 * @ingroup hpb_registers 105 * @defgroup HPB_STATUS HPB_STATUS 106 * @brief HPB Status Register. 107 * @{ 108 */ 109 #define MXC_F_HPB_STATUS_RACT_POS 0 /**< STATUS_RACT Position */ 110 #define MXC_F_HPB_STATUS_RACT ((uint32_t)(0x1UL << MXC_F_HPB_STATUS_RACT_POS)) /**< STATUS_RACT Mask */ 111 #define MXC_V_HPB_STATUS_RACT_NOREAD ((uint32_t)0x0UL) /**< STATUS_RACT_NOREAD Value */ 112 #define MXC_S_HPB_STATUS_RACT_NOREAD (MXC_V_HPB_STATUS_RACT_NOREAD << MXC_F_HPB_STATUS_RACT_POS) /**< STATUS_RACT_NOREAD Setting */ 113 #define MXC_V_HPB_STATUS_RACT_READ ((uint32_t)0x1UL) /**< STATUS_RACT_READ Value */ 114 #define MXC_S_HPB_STATUS_RACT_READ (MXC_V_HPB_STATUS_RACT_READ << MXC_F_HPB_STATUS_RACT_POS) /**< STATUS_RACT_READ Setting */ 115 116 #define MXC_F_HPB_STATUS_RDECERR_POS 8 /**< STATUS_RDECERR Position */ 117 #define MXC_F_HPB_STATUS_RDECERR ((uint32_t)(0x1UL << MXC_F_HPB_STATUS_RDECERR_POS)) /**< STATUS_RDECERR Mask */ 118 #define MXC_V_HPB_STATUS_RDECERR_NOERR ((uint32_t)0x0UL) /**< STATUS_RDECERR_NOERR Value */ 119 #define MXC_S_HPB_STATUS_RDECERR_NOERR (MXC_V_HPB_STATUS_RDECERR_NOERR << MXC_F_HPB_STATUS_RDECERR_POS) /**< STATUS_RDECERR_NOERR Setting */ 120 #define MXC_V_HPB_STATUS_RDECERR_ERR ((uint32_t)0x1UL) /**< STATUS_RDECERR_ERR Value */ 121 #define MXC_S_HPB_STATUS_RDECERR_ERR (MXC_V_HPB_STATUS_RDECERR_ERR << MXC_F_HPB_STATUS_RDECERR_POS) /**< STATUS_RDECERR_ERR Setting */ 122 123 #define MXC_F_HPB_STATUS_RRSTOERR_POS 10 /**< STATUS_RRSTOERR Position */ 124 #define MXC_F_HPB_STATUS_RRSTOERR ((uint32_t)(0x1UL << MXC_F_HPB_STATUS_RRSTOERR_POS)) /**< STATUS_RRSTOERR Mask */ 125 #define MXC_V_HPB_STATUS_RRSTOERR_NOERR ((uint32_t)0x0UL) /**< STATUS_RRSTOERR_NOERR Value */ 126 #define MXC_S_HPB_STATUS_RRSTOERR_NOERR (MXC_V_HPB_STATUS_RRSTOERR_NOERR << MXC_F_HPB_STATUS_RRSTOERR_POS) /**< STATUS_RRSTOERR_NOERR Setting */ 127 #define MXC_V_HPB_STATUS_RRSTOERR_ERR ((uint32_t)0x1UL) /**< STATUS_RRSTOERR_ERR Value */ 128 #define MXC_S_HPB_STATUS_RRSTOERR_ERR (MXC_V_HPB_STATUS_RRSTOERR_ERR << MXC_F_HPB_STATUS_RRSTOERR_POS) /**< STATUS_RRSTOERR_ERR Setting */ 129 130 #define MXC_F_HPB_STATUS_RDSSTALL_POS 11 /**< STATUS_RDSSTALL Position */ 131 #define MXC_F_HPB_STATUS_RDSSTALL ((uint32_t)(0x1UL << MXC_F_HPB_STATUS_RDSSTALL_POS)) /**< STATUS_RDSSTALL Mask */ 132 #define MXC_V_HPB_STATUS_RDSSTALL_NORMALOP ((uint32_t)0x0UL) /**< STATUS_RDSSTALL_NORMALOP Value */ 133 #define MXC_S_HPB_STATUS_RDSSTALL_NORMALOP (MXC_V_HPB_STATUS_RDSSTALL_NORMALOP << MXC_F_HPB_STATUS_RDSSTALL_POS) /**< STATUS_RDSSTALL_NORMALOP Setting */ 134 #define MXC_V_HPB_STATUS_RDSSTALL_STALLED ((uint32_t)0x1UL) /**< STATUS_RDSSTALL_STALLED Value */ 135 #define MXC_S_HPB_STATUS_RDSSTALL_STALLED (MXC_V_HPB_STATUS_RDSSTALL_STALLED << MXC_F_HPB_STATUS_RDSSTALL_POS) /**< STATUS_RDSSTALL_STALLED Setting */ 136 137 #define MXC_F_HPB_STATUS_WACT_POS 16 /**< STATUS_WACT Position */ 138 #define MXC_F_HPB_STATUS_WACT ((uint32_t)(0x1UL << MXC_F_HPB_STATUS_WACT_POS)) /**< STATUS_WACT Mask */ 139 #define MXC_V_HPB_STATUS_WACT_NOWRITE ((uint32_t)0x0UL) /**< STATUS_WACT_NOWRITE Value */ 140 #define MXC_S_HPB_STATUS_WACT_NOWRITE (MXC_V_HPB_STATUS_WACT_NOWRITE << MXC_F_HPB_STATUS_WACT_POS) /**< STATUS_WACT_NOWRITE Setting */ 141 #define MXC_V_HPB_STATUS_WACT_WRITE ((uint32_t)0x1UL) /**< STATUS_WACT_WRITE Value */ 142 #define MXC_S_HPB_STATUS_WACT_WRITE (MXC_V_HPB_STATUS_WACT_WRITE << MXC_F_HPB_STATUS_WACT_POS) /**< STATUS_WACT_WRITE Setting */ 143 144 #define MXC_F_HPB_STATUS_WDECERR_POS 24 /**< STATUS_WDECERR Position */ 145 #define MXC_F_HPB_STATUS_WDECERR ((uint32_t)(0x1UL << MXC_F_HPB_STATUS_WDECERR_POS)) /**< STATUS_WDECERR Mask */ 146 #define MXC_V_HPB_STATUS_WDECERR_NOERR ((uint32_t)0x0UL) /**< STATUS_WDECERR_NOERR Value */ 147 #define MXC_S_HPB_STATUS_WDECERR_NOERR (MXC_V_HPB_STATUS_WDECERR_NOERR << MXC_F_HPB_STATUS_WDECERR_POS) /**< STATUS_WDECERR_NOERR Setting */ 148 #define MXC_V_HPB_STATUS_WDECERR_ERR ((uint32_t)0x1UL) /**< STATUS_WDECERR_ERR Value */ 149 #define MXC_S_HPB_STATUS_WDECERR_ERR (MXC_V_HPB_STATUS_WDECERR_ERR << MXC_F_HPB_STATUS_WDECERR_POS) /**< STATUS_WDECERR_ERR Setting */ 150 151 #define MXC_F_HPB_STATUS_WRSTOERR_POS 26 /**< STATUS_WRSTOERR Position */ 152 #define MXC_F_HPB_STATUS_WRSTOERR ((uint32_t)(0x1UL << MXC_F_HPB_STATUS_WRSTOERR_POS)) /**< STATUS_WRSTOERR Mask */ 153 #define MXC_V_HPB_STATUS_WRSTOERR_NOERR ((uint32_t)0x0UL) /**< STATUS_WRSTOERR_NOERR Value */ 154 #define MXC_S_HPB_STATUS_WRSTOERR_NOERR (MXC_V_HPB_STATUS_WRSTOERR_NOERR << MXC_F_HPB_STATUS_WRSTOERR_POS) /**< STATUS_WRSTOERR_NOERR Setting */ 155 #define MXC_V_HPB_STATUS_WRSTOERR_ERR ((uint32_t)0x1UL) /**< STATUS_WRSTOERR_ERR Value */ 156 #define MXC_S_HPB_STATUS_WRSTOERR_ERR (MXC_V_HPB_STATUS_WRSTOERR_ERR << MXC_F_HPB_STATUS_WRSTOERR_POS) /**< STATUS_WRSTOERR_ERR Setting */ 157 158 /**@} end of group HPB_STATUS_Register */ 159 160 /** 161 * @ingroup hpb_registers 162 * @defgroup HPB_INTEN HPB_INTEN 163 * @brief HPB Interrupt Enable. 164 * @{ 165 */ 166 #define MXC_F_HPB_INTEN_ERRINTE_POS 1 /**< INTEN_ERRINTE Position */ 167 #define MXC_F_HPB_INTEN_ERRINTE ((uint32_t)(0x1UL << MXC_F_HPB_INTEN_ERRINTE_POS)) /**< INTEN_ERRINTE Mask */ 168 #define MXC_V_HPB_INTEN_ERRINTE_DIS ((uint32_t)0x0UL) /**< INTEN_ERRINTE_DIS Value */ 169 #define MXC_S_HPB_INTEN_ERRINTE_DIS (MXC_V_HPB_INTEN_ERRINTE_DIS << MXC_F_HPB_INTEN_ERRINTE_POS) /**< INTEN_ERRINTE_DIS Setting */ 170 #define MXC_V_HPB_INTEN_ERRINTE_EN ((uint32_t)0x1UL) /**< INTEN_ERRINTE_EN Value */ 171 #define MXC_S_HPB_INTEN_ERRINTE_EN (MXC_V_HPB_INTEN_ERRINTE_EN << MXC_F_HPB_INTEN_ERRINTE_POS) /**< INTEN_ERRINTE_EN Setting */ 172 173 /**@} end of group HPB_INTEN_Register */ 174 175 /** 176 * @ingroup hpb_registers 177 * @defgroup HPB_INTFL HPB_INTFL 178 * @brief HPB Interrupt Status Flags. 179 * @{ 180 */ 181 #define MXC_F_HPB_INTFL_ERRINT_POS 1 /**< INTFL_ERRINT Position */ 182 #define MXC_F_HPB_INTFL_ERRINT ((uint32_t)(0x1UL << MXC_F_HPB_INTFL_ERRINT_POS)) /**< INTFL_ERRINT Mask */ 183 #define MXC_V_HPB_INTFL_ERRINT_NOINT ((uint32_t)0x0UL) /**< INTFL_ERRINT_NOINT Value */ 184 #define MXC_S_HPB_INTFL_ERRINT_NOINT (MXC_V_HPB_INTFL_ERRINT_NOINT << MXC_F_HPB_INTFL_ERRINT_POS) /**< INTFL_ERRINT_NOINT Setting */ 185 #define MXC_V_HPB_INTFL_ERRINT_PENDING ((uint32_t)0x1UL) /**< INTFL_ERRINT_PENDING Value */ 186 #define MXC_S_HPB_INTFL_ERRINT_PENDING (MXC_V_HPB_INTFL_ERRINT_PENDING << MXC_F_HPB_INTFL_ERRINT_POS) /**< INTFL_ERRINT_PENDING Setting */ 187 188 /**@} end of group HPB_INTFL_Register */ 189 190 /** 191 * @ingroup hpb_registers 192 * @defgroup HPB_MBR HPB_MBR 193 * @brief HPB Memory Base Address. 194 * @{ 195 */ 196 #define MXC_F_HPB_MBR_ADDR_POS 24 /**< MBR_ADDR Position */ 197 #define MXC_F_HPB_MBR_ADDR ((uint32_t)(0xFFUL << MXC_F_HPB_MBR_ADDR_POS)) /**< MBR_ADDR Mask */ 198 199 /**@} end of group HPB_MBR_Register */ 200 201 /** 202 * @ingroup hpb_registers 203 * @defgroup HPB_MCR HPB_MCR 204 * @brief HPB Memory Configuration Register. 205 * @{ 206 */ 207 #define MXC_F_HPB_MCR_DEV_TYPE_POS 3 /**< MCR_DEV_TYPE Position */ 208 #define MXC_F_HPB_MCR_DEV_TYPE ((uint32_t)(0x3UL << MXC_F_HPB_MCR_DEV_TYPE_POS)) /**< MCR_DEV_TYPE Mask */ 209 #define MXC_V_HPB_MCR_DEV_TYPE_HYPERFLASH ((uint32_t)0x0UL) /**< MCR_DEV_TYPE_HYPERFLASH Value */ 210 #define MXC_S_HPB_MCR_DEV_TYPE_HYPERFLASH (MXC_V_HPB_MCR_DEV_TYPE_HYPERFLASH << MXC_F_HPB_MCR_DEV_TYPE_POS) /**< MCR_DEV_TYPE_HYPERFLASH Setting */ 211 #define MXC_V_HPB_MCR_DEV_TYPE_XCCELAPSRAM ((uint32_t)0x1UL) /**< MCR_DEV_TYPE_XCCELAPSRAM Value */ 212 #define MXC_S_HPB_MCR_DEV_TYPE_XCCELAPSRAM (MXC_V_HPB_MCR_DEV_TYPE_XCCELAPSRAM << MXC_F_HPB_MCR_DEV_TYPE_POS) /**< MCR_DEV_TYPE_XCCELAPSRAM Setting */ 213 #define MXC_V_HPB_MCR_DEV_TYPE_HYPERRAM ((uint32_t)0x2UL) /**< MCR_DEV_TYPE_HYPERRAM Value */ 214 #define MXC_S_HPB_MCR_DEV_TYPE_HYPERRAM (MXC_V_HPB_MCR_DEV_TYPE_HYPERRAM << MXC_F_HPB_MCR_DEV_TYPE_POS) /**< MCR_DEV_TYPE_HYPERRAM Setting */ 215 216 #define MXC_F_HPB_MCR_CRT_POS 5 /**< MCR_CRT Position */ 217 #define MXC_F_HPB_MCR_CRT ((uint32_t)(0x1UL << MXC_F_HPB_MCR_CRT_POS)) /**< MCR_CRT Mask */ 218 #define MXC_V_HPB_MCR_CRT_MEM_SPACE ((uint32_t)0x0UL) /**< MCR_CRT_MEM_SPACE Value */ 219 #define MXC_S_HPB_MCR_CRT_MEM_SPACE (MXC_V_HPB_MCR_CRT_MEM_SPACE << MXC_F_HPB_MCR_CRT_POS) /**< MCR_CRT_MEM_SPACE Setting */ 220 #define MXC_V_HPB_MCR_CRT_CONFIG_REG_SPACE ((uint32_t)0x1UL) /**< MCR_CRT_CONFIG_REG_SPACE Value */ 221 #define MXC_S_HPB_MCR_CRT_CONFIG_REG_SPACE (MXC_V_HPB_MCR_CRT_CONFIG_REG_SPACE << MXC_F_HPB_MCR_CRT_POS) /**< MCR_CRT_CONFIG_REG_SPACE Setting */ 222 223 #define MXC_F_HPB_MCR_READ_LATENCY_POS 6 /**< MCR_READ_LATENCY Position */ 224 #define MXC_F_HPB_MCR_READ_LATENCY ((uint32_t)(0x1UL << MXC_F_HPB_MCR_READ_LATENCY_POS)) /**< MCR_READ_LATENCY Mask */ 225 #define MXC_V_HPB_MCR_READ_LATENCY_VARIABLE ((uint32_t)0x0UL) /**< MCR_READ_LATENCY_VARIABLE Value */ 226 #define MXC_S_HPB_MCR_READ_LATENCY_VARIABLE (MXC_V_HPB_MCR_READ_LATENCY_VARIABLE << MXC_F_HPB_MCR_READ_LATENCY_POS) /**< MCR_READ_LATENCY_VARIABLE Setting */ 227 #define MXC_V_HPB_MCR_READ_LATENCY_FIXED ((uint32_t)0x1UL) /**< MCR_READ_LATENCY_FIXED Value */ 228 #define MXC_S_HPB_MCR_READ_LATENCY_FIXED (MXC_V_HPB_MCR_READ_LATENCY_FIXED << MXC_F_HPB_MCR_READ_LATENCY_POS) /**< MCR_READ_LATENCY_FIXED Setting */ 229 230 #define MXC_F_HPB_MCR_HSE_POS 7 /**< MCR_HSE Position */ 231 #define MXC_F_HPB_MCR_HSE ((uint32_t)(0x1UL << MXC_F_HPB_MCR_HSE_POS)) /**< MCR_HSE Mask */ 232 #define MXC_V_HPB_MCR_HSE_DIS ((uint32_t)0x0UL) /**< MCR_HSE_DIS Value */ 233 #define MXC_S_HPB_MCR_HSE_DIS (MXC_V_HPB_MCR_HSE_DIS << MXC_F_HPB_MCR_HSE_POS) /**< MCR_HSE_DIS Setting */ 234 #define MXC_V_HPB_MCR_HSE_EN ((uint32_t)0x1UL) /**< MCR_HSE_EN Value */ 235 #define MXC_S_HPB_MCR_HSE_EN (MXC_V_HPB_MCR_HSE_EN << MXC_F_HPB_MCR_HSE_POS) /**< MCR_HSE_EN Setting */ 236 237 #define MXC_F_HPB_MCR_MAXLEN_POS 18 /**< MCR_MAXLEN Position */ 238 #define MXC_F_HPB_MCR_MAXLEN ((uint32_t)(0x1FFUL << MXC_F_HPB_MCR_MAXLEN_POS)) /**< MCR_MAXLEN Mask */ 239 240 #define MXC_F_HPB_MCR_MAXLEN_EN_POS 31 /**< MCR_MAXLEN_EN Position */ 241 #define MXC_F_HPB_MCR_MAXLEN_EN ((uint32_t)(0x1UL << MXC_F_HPB_MCR_MAXLEN_EN_POS)) /**< MCR_MAXLEN_EN Mask */ 242 #define MXC_V_HPB_MCR_MAXLEN_EN_DIS ((uint32_t)0x0UL) /**< MCR_MAXLEN_EN_DIS Value */ 243 #define MXC_S_HPB_MCR_MAXLEN_EN_DIS (MXC_V_HPB_MCR_MAXLEN_EN_DIS << MXC_F_HPB_MCR_MAXLEN_EN_POS) /**< MCR_MAXLEN_EN_DIS Setting */ 244 #define MXC_V_HPB_MCR_MAXLEN_EN_EN ((uint32_t)0x1UL) /**< MCR_MAXLEN_EN_EN Value */ 245 #define MXC_S_HPB_MCR_MAXLEN_EN_EN (MXC_V_HPB_MCR_MAXLEN_EN_EN << MXC_F_HPB_MCR_MAXLEN_EN_POS) /**< MCR_MAXLEN_EN_EN Setting */ 246 247 /**@} end of group HPB_MCR_Register */ 248 249 /** 250 * @ingroup hpb_registers 251 * @defgroup HPB_MTR HPB_MTR 252 * @brief HPB Memory Timing Register. 253 * @{ 254 */ 255 #define MXC_F_HPB_MTR_LATENCY_POS 0 /**< MTR_LATENCY Position */ 256 #define MXC_F_HPB_MTR_LATENCY ((uint32_t)(0xFUL << MXC_F_HPB_MTR_LATENCY_POS)) /**< MTR_LATENCY Mask */ 257 #define MXC_V_HPB_MTR_LATENCY_5CLK ((uint32_t)0x0UL) /**< MTR_LATENCY_5CLK Value */ 258 #define MXC_S_HPB_MTR_LATENCY_5CLK (MXC_V_HPB_MTR_LATENCY_5CLK << MXC_F_HPB_MTR_LATENCY_POS) /**< MTR_LATENCY_5CLK Setting */ 259 #define MXC_V_HPB_MTR_LATENCY_6CLK ((uint32_t)0x1UL) /**< MTR_LATENCY_6CLK Value */ 260 #define MXC_S_HPB_MTR_LATENCY_6CLK (MXC_V_HPB_MTR_LATENCY_6CLK << MXC_F_HPB_MTR_LATENCY_POS) /**< MTR_LATENCY_6CLK Setting */ 261 #define MXC_V_HPB_MTR_LATENCY_3CLK ((uint32_t)0xEUL) /**< MTR_LATENCY_3CLK Value */ 262 #define MXC_S_HPB_MTR_LATENCY_3CLK (MXC_V_HPB_MTR_LATENCY_3CLK << MXC_F_HPB_MTR_LATENCY_POS) /**< MTR_LATENCY_3CLK Setting */ 263 #define MXC_V_HPB_MTR_LATENCY_4CLK ((uint32_t)0xFUL) /**< MTR_LATENCY_4CLK Value */ 264 #define MXC_S_HPB_MTR_LATENCY_4CLK (MXC_V_HPB_MTR_LATENCY_4CLK << MXC_F_HPB_MTR_LATENCY_POS) /**< MTR_LATENCY_4CLK Setting */ 265 266 #define MXC_F_HPB_MTR_WCSH_POS 8 /**< MTR_WCSH Position */ 267 #define MXC_F_HPB_MTR_WCSH ((uint32_t)(0xFUL << MXC_F_HPB_MTR_WCSH_POS)) /**< MTR_WCSH Mask */ 268 269 #define MXC_F_HPB_MTR_RCSH_POS 12 /**< MTR_RCSH Position */ 270 #define MXC_F_HPB_MTR_RCSH ((uint32_t)(0xFUL << MXC_F_HPB_MTR_RCSH_POS)) /**< MTR_RCSH Mask */ 271 272 #define MXC_F_HPB_MTR_WCSS_POS 16 /**< MTR_WCSS Position */ 273 #define MXC_F_HPB_MTR_WCSS ((uint32_t)(0xFUL << MXC_F_HPB_MTR_WCSS_POS)) /**< MTR_WCSS Mask */ 274 275 #define MXC_F_HPB_MTR_RCSS_POS 20 /**< MTR_RCSS Position */ 276 #define MXC_F_HPB_MTR_RCSS ((uint32_t)(0xFUL << MXC_F_HPB_MTR_RCSS_POS)) /**< MTR_RCSS Mask */ 277 278 #define MXC_F_HPB_MTR_WCSHI_POS 24 /**< MTR_WCSHI Position */ 279 #define MXC_F_HPB_MTR_WCSHI ((uint32_t)(0xFUL << MXC_F_HPB_MTR_WCSHI_POS)) /**< MTR_WCSHI Mask */ 280 281 #define MXC_F_HPB_MTR_RCSHI_POS 28 /**< MTR_RCSHI Position */ 282 #define MXC_F_HPB_MTR_RCSHI ((uint32_t)(0xFUL << MXC_F_HPB_MTR_RCSHI_POS)) /**< MTR_RCSHI Mask */ 283 284 /**@} end of group HPB_MTR_Register */ 285 286 #ifdef __cplusplus 287 } 288 #endif 289 290 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_HPB_REGS_H_ 291
