1 /** 2 * @file flc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup flc_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_FLC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_FLC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup flc 67 * @defgroup flc_registers FLC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. 69 * @details Flash Memory Control. 70 */ 71 72 /** 73 * @ingroup flc_registers 74 * Structure type to access the FLC Registers. 75 */ 76 typedef struct { 77 __IO uint32_t addr; /**< <tt>\b 0x00:</tt> FLC ADDR Register */ 78 __IO uint32_t clkdiv; /**< <tt>\b 0x04:</tt> FLC CLKDIV Register */ 79 __IO uint32_t ctrl; /**< <tt>\b 0x08:</tt> FLC CTRL Register */ 80 __R uint32_t rsv_0xc_0x23[6]; 81 __IO uint32_t intr; /**< <tt>\b 0x024:</tt> FLC INTR Register */ 82 __R uint32_t rsv_0x28_0x2f[2]; 83 __IO uint32_t data[4]; /**< <tt>\b 0x30:</tt> FLC DATA Register */ 84 __O uint32_t actnl; /**< <tt>\b 0x40:</tt> FLC ACTNL Register */ 85 } mxc_flc_regs_t; 86 87 /* Register offsets for module FLC */ 88 /** 89 * @ingroup flc_registers 90 * @defgroup FLC_Register_Offsets Register Offsets 91 * @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address. 92 * @{ 93 */ 94 #define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> 0x0000</tt> */ 95 #define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0004</tt> */ 96 #define MXC_R_FLC_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> 0x0008</tt> */ 97 #define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> 0x0024</tt> */ 98 #define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> 0x0030</tt> */ 99 #define MXC_R_FLC_ACTNL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> 0x0040</tt> */ 100 /**@} end of group flc_registers */ 101 102 /** 103 * @ingroup flc_registers 104 * @defgroup FLC_ADDR FLC_ADDR 105 * @brief Flash Write Address. 106 * @{ 107 */ 108 #define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ 109 #define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ 110 111 /**@} end of group FLC_ADDR_Register */ 112 113 /** 114 * @ingroup flc_registers 115 * @defgroup FLC_CLKDIV FLC_CLKDIV 116 * @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 117 * MHz clock for Flash controller. 118 * @{ 119 */ 120 #define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ 121 #define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ 122 123 /**@} end of group FLC_CLKDIV_Register */ 124 125 /** 126 * @ingroup flc_registers 127 * @defgroup FLC_CTRL FLC_CTRL 128 * @brief Flash Control Register. 129 * @{ 130 */ 131 #define MXC_F_FLC_CTRL_WRITE_POS 0 /**< CTRL_WRITE Position */ 132 #define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WRITE_POS)) /**< CTRL_WRITE Mask */ 133 #define MXC_V_FLC_CTRL_WRITE_COMPLETE ((uint32_t)0x0UL) /**< CTRL_WRITE_COMPLETE Value */ 134 #define MXC_S_FLC_CTRL_WRITE_COMPLETE (MXC_V_FLC_CTRL_WRITE_COMPLETE << MXC_F_FLC_CTRL_WRITE_POS) /**< CTRL_WRITE_COMPLETE Setting */ 135 #define MXC_V_FLC_CTRL_WRITE_START_WR ((uint32_t)0x1UL) /**< CTRL_WRITE_START_WR Value */ 136 #define MXC_S_FLC_CTRL_WRITE_START_WR (MXC_V_FLC_CTRL_WRITE_START_WR << MXC_F_FLC_CTRL_WRITE_POS) /**< CTRL_WRITE_START_WR Setting */ 137 138 #define MXC_F_FLC_CTRL_MASS_ERASE_POS 1 /**< CTRL_MASS_ERASE Position */ 139 #define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_MASS_ERASE_POS)) /**< CTRL_MASS_ERASE Mask */ 140 #define MXC_V_FLC_CTRL_MASS_ERASE_COMPLETE ((uint32_t)0x0UL) /**< CTRL_MASS_ERASE_COMPLETE Value */ 141 #define MXC_S_FLC_CTRL_MASS_ERASE_COMPLETE (MXC_V_FLC_CTRL_MASS_ERASE_COMPLETE << MXC_F_FLC_CTRL_MASS_ERASE_POS) /**< CTRL_MASS_ERASE_COMPLETE Setting */ 142 #define MXC_V_FLC_CTRL_MASS_ERASE_START_ME ((uint32_t)0x1UL) /**< CTRL_MASS_ERASE_START_ME Value */ 143 #define MXC_S_FLC_CTRL_MASS_ERASE_START_ME (MXC_V_FLC_CTRL_MASS_ERASE_START_ME << MXC_F_FLC_CTRL_MASS_ERASE_POS) /**< CTRL_MASS_ERASE_START_ME Setting */ 144 145 #define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2 /**< CTRL_PAGE_ERASE Position */ 146 #define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS)) /**< CTRL_PAGE_ERASE Mask */ 147 #define MXC_V_FLC_CTRL_PAGE_ERASE_COMPLETE ((uint32_t)0x0UL) /**< CTRL_PAGE_ERASE_COMPLETE Value */ 148 #define MXC_S_FLC_CTRL_PAGE_ERASE_COMPLETE (MXC_V_FLC_CTRL_PAGE_ERASE_COMPLETE << MXC_F_FLC_CTRL_PAGE_ERASE_POS) /**< CTRL_PAGE_ERASE_COMPLETE Setting */ 149 #define MXC_V_FLC_CTRL_PAGE_ERASE_START_PGE ((uint32_t)0x1UL) /**< CTRL_PAGE_ERASE_START_PGE Value */ 150 #define MXC_S_FLC_CTRL_PAGE_ERASE_START_PGE (MXC_V_FLC_CTRL_PAGE_ERASE_START_PGE << MXC_F_FLC_CTRL_PAGE_ERASE_POS) /**< CTRL_PAGE_ERASE_START_PGE Setting */ 151 152 #define MXC_F_FLC_CTRL_WIDTH_POS 4 /**< CTRL_WIDTH Position */ 153 #define MXC_F_FLC_CTRL_WIDTH ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WIDTH_POS)) /**< CTRL_WIDTH Mask */ 154 #define MXC_V_FLC_CTRL_WIDTH_128_BIT ((uint32_t)0x0UL) /**< CTRL_WIDTH_128_BIT Value */ 155 #define MXC_S_FLC_CTRL_WIDTH_128_BIT (MXC_V_FLC_CTRL_WIDTH_128_BIT << MXC_F_FLC_CTRL_WIDTH_POS) /**< CTRL_WIDTH_128_BIT Setting */ 156 #define MXC_V_FLC_CTRL_WIDTH_32_BIT ((uint32_t)0x1UL) /**< CTRL_WIDTH_32_BIT Value */ 157 #define MXC_S_FLC_CTRL_WIDTH_32_BIT (MXC_V_FLC_CTRL_WIDTH_32_BIT << MXC_F_FLC_CTRL_WIDTH_POS) /**< CTRL_WIDTH_32_BIT Setting */ 158 159 #define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */ 160 #define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */ 161 #define MXC_V_FLC_CTRL_ERASE_CODE_DIS ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_DIS Value */ 162 #define MXC_S_FLC_CTRL_ERASE_CODE_DIS (MXC_V_FLC_CTRL_ERASE_CODE_DIS << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_DIS Setting */ 163 #define MXC_V_FLC_CTRL_ERASE_CODE_PGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_PGE Value */ 164 #define MXC_S_FLC_CTRL_ERASE_CODE_PGE (MXC_V_FLC_CTRL_ERASE_CODE_PGE << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_PGE Setting */ 165 #define MXC_V_FLC_CTRL_ERASE_CODE_ME ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ME Value */ 166 #define MXC_S_FLC_CTRL_ERASE_CODE_ME (MXC_V_FLC_CTRL_ERASE_CODE_ME << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ME Setting */ 167 168 #define MXC_F_FLC_CTRL_BUSY_POS 24 /**< CTRL_BUSY Position */ 169 #define MXC_F_FLC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ 170 #define MXC_V_FLC_CTRL_BUSY_IDLE ((uint32_t)0x0UL) /**< CTRL_BUSY_IDLE Value */ 171 #define MXC_S_FLC_CTRL_BUSY_IDLE (MXC_V_FLC_CTRL_BUSY_IDLE << MXC_F_FLC_CTRL_BUSY_POS) /**< CTRL_BUSY_IDLE Setting */ 172 #define MXC_V_FLC_CTRL_BUSY_BUSY ((uint32_t)0x1UL) /**< CTRL_BUSY_BUSY Value */ 173 #define MXC_S_FLC_CTRL_BUSY_BUSY (MXC_V_FLC_CTRL_BUSY_BUSY << MXC_F_FLC_CTRL_BUSY_POS) /**< CTRL_BUSY_BUSY Setting */ 174 175 #define MXC_F_FLC_CTRL_UNLOCK_CODE_POS 28 /**< CTRL_UNLOCK_CODE Position */ 176 #define MXC_F_FLC_CTRL_UNLOCK_CODE ((uint32_t)(0xFUL << MXC_F_FLC_CTRL_UNLOCK_CODE_POS)) /**< CTRL_UNLOCK_CODE Mask */ 177 #define MXC_V_FLC_CTRL_UNLOCK_CODE_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_CODE_UNLOCKED Value */ 178 #define MXC_S_FLC_CTRL_UNLOCK_CODE_UNLOCKED (MXC_V_FLC_CTRL_UNLOCK_CODE_UNLOCKED << MXC_F_FLC_CTRL_UNLOCK_CODE_POS) /**< CTRL_UNLOCK_CODE_UNLOCKED Setting */ 179 #define MXC_V_FLC_CTRL_UNLOCK_CODE_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_CODE_LOCKED Value */ 180 #define MXC_S_FLC_CTRL_UNLOCK_CODE_LOCKED (MXC_V_FLC_CTRL_UNLOCK_CODE_LOCKED << MXC_F_FLC_CTRL_UNLOCK_CODE_POS) /**< CTRL_UNLOCK_CODE_LOCKED Setting */ 181 182 /**@} end of group FLC_CTRL_Register */ 183 184 /** 185 * @ingroup flc_registers 186 * @defgroup FLC_INTR FLC_INTR 187 * @brief Flash Interrupt Register. 188 * @{ 189 */ 190 #define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */ 191 #define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */ 192 #define MXC_V_FLC_INTR_DONE_INACTIVE ((uint32_t)0x0UL) /**< INTR_DONE_INACTIVE Value */ 193 #define MXC_S_FLC_INTR_DONE_INACTIVE (MXC_V_FLC_INTR_DONE_INACTIVE << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_INACTIVE Setting */ 194 #define MXC_V_FLC_INTR_DONE_PENDING ((uint32_t)0x1UL) /**< INTR_DONE_PENDING Value */ 195 #define MXC_S_FLC_INTR_DONE_PENDING (MXC_V_FLC_INTR_DONE_PENDING << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_PENDING Setting */ 196 197 #define MXC_F_FLC_INTR_ACCESS_FAIL_POS 1 /**< INTR_ACCESS_FAIL Position */ 198 #define MXC_F_FLC_INTR_ACCESS_FAIL ((uint32_t)(0x1UL << MXC_F_FLC_INTR_ACCESS_FAIL_POS)) /**< INTR_ACCESS_FAIL Mask */ 199 #define MXC_V_FLC_INTR_ACCESS_FAIL_NOERR ((uint32_t)0x0UL) /**< INTR_ACCESS_FAIL_NOERR Value */ 200 #define MXC_S_FLC_INTR_ACCESS_FAIL_NOERR (MXC_V_FLC_INTR_ACCESS_FAIL_NOERR << MXC_F_FLC_INTR_ACCESS_FAIL_POS) /**< INTR_ACCESS_FAIL_NOERR Setting */ 201 #define MXC_V_FLC_INTR_ACCESS_FAIL_ERROR ((uint32_t)0x1UL) /**< INTR_ACCESS_FAIL_ERROR Value */ 202 #define MXC_S_FLC_INTR_ACCESS_FAIL_ERROR (MXC_V_FLC_INTR_ACCESS_FAIL_ERROR << MXC_F_FLC_INTR_ACCESS_FAIL_POS) /**< INTR_ACCESS_FAIL_ERROR Setting */ 203 204 #define MXC_F_FLC_INTR_DONE_IE_POS 8 /**< INTR_DONE_IE Position */ 205 #define MXC_F_FLC_INTR_DONE_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_IE_POS)) /**< INTR_DONE_IE Mask */ 206 #define MXC_V_FLC_INTR_DONE_IE_DIS ((uint32_t)0x0UL) /**< INTR_DONE_IE_DIS Value */ 207 #define MXC_S_FLC_INTR_DONE_IE_DIS (MXC_V_FLC_INTR_DONE_IE_DIS << MXC_F_FLC_INTR_DONE_IE_POS) /**< INTR_DONE_IE_DIS Setting */ 208 #define MXC_V_FLC_INTR_DONE_IE_EN ((uint32_t)0x1UL) /**< INTR_DONE_IE_EN Value */ 209 #define MXC_S_FLC_INTR_DONE_IE_EN (MXC_V_FLC_INTR_DONE_IE_EN << MXC_F_FLC_INTR_DONE_IE_POS) /**< INTR_DONE_IE_EN Setting */ 210 211 #define MXC_F_FLC_INTR_ACCESS_FAIL_IE_POS 9 /**< INTR_ACCESS_FAIL_IE Position */ 212 #define MXC_F_FLC_INTR_ACCESS_FAIL_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_ACCESS_FAIL_IE_POS)) /**< INTR_ACCESS_FAIL_IE Mask */ 213 #define MXC_V_FLC_INTR_ACCESS_FAIL_IE_DIS ((uint32_t)0x0UL) /**< INTR_ACCESS_FAIL_IE_DIS Value */ 214 #define MXC_S_FLC_INTR_ACCESS_FAIL_IE_DIS (MXC_V_FLC_INTR_ACCESS_FAIL_IE_DIS << MXC_F_FLC_INTR_ACCESS_FAIL_IE_POS) /**< INTR_ACCESS_FAIL_IE_DIS Setting */ 215 #define MXC_V_FLC_INTR_ACCESS_FAIL_IE_EN ((uint32_t)0x1UL) /**< INTR_ACCESS_FAIL_IE_EN Value */ 216 #define MXC_S_FLC_INTR_ACCESS_FAIL_IE_EN (MXC_V_FLC_INTR_ACCESS_FAIL_IE_EN << MXC_F_FLC_INTR_ACCESS_FAIL_IE_POS) /**< INTR_ACCESS_FAIL_IE_EN Setting */ 217 218 /**@} end of group FLC_INTR_Register */ 219 220 /** 221 * @ingroup flc_registers 222 * @defgroup FLC_DATA FLC_DATA 223 * @brief Flash Write Data. 224 * @{ 225 */ 226 #define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */ 227 #define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */ 228 229 /**@} end of group FLC_DATA_Register */ 230 231 /** 232 * @ingroup flc_registers 233 * @defgroup FLC_ACTNL FLC_ACTNL 234 * @brief Access Control Register. Writing the ACNTL register with the following values in 235 * the order shown, allows read and write access to the system and user Information 236 * block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = 237 * 0x9608b2c1. When unlocked, a write of any word will disable access to system and 238 * user information block. Readback of this register is always zero. 239 * @{ 240 */ 241 #define MXC_F_FLC_ACTNL_ACNTL_POS 0 /**< ACTNL_ACNTL Position */ 242 #define MXC_F_FLC_ACTNL_ACNTL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACTNL_ACNTL_POS)) /**< ACTNL_ACNTL Mask */ 243 244 /**@} end of group FLC_ACTNL_Register */ 245 246 #ifdef __cplusplus 247 } 248 #endif 249 250 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_FLC_REGS_H_ 251
