1 /** 2 * @file emcc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the EMCC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup emcc_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_EMCC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_EMCC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup emcc 67 * @defgroup emcc_registers EMCC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the EMCC Peripheral Module. 69 * @details External Memory Cache Controller Registers. 70 */ 71 72 /** 73 * @ingroup emcc_registers 74 * Structure type to access the EMCC Registers. 75 */ 76 typedef struct { 77 __I uint32_t cache_id; /**< <tt>\b 0x0000:</tt> EMCC CACHE_ID Register */ 78 __I uint32_t mem_size; /**< <tt>\b 0x0004:</tt> EMCC MEM_SIZE Register */ 79 __R uint32_t rsv_0x8_0xff[62]; 80 __IO uint32_t cache_ctrl; /**< <tt>\b 0x0100:</tt> EMCC CACHE_CTRL Register */ 81 __R uint32_t rsv_0x104_0x6ff[383]; 82 __IO uint32_t invalidate; /**< <tt>\b 0x0700:</tt> EMCC INVALIDATE Register */ 83 } mxc_emcc_regs_t; 84 85 /* Register offsets for module EMCC */ 86 /** 87 * @ingroup emcc_registers 88 * @defgroup EMCC_Register_Offsets Register Offsets 89 * @brief EMCC Peripheral Register Offsets from the EMCC Base Peripheral Address. 90 * @{ 91 */ 92 #define MXC_R_EMCC_CACHE_ID ((uint32_t)0x00000000UL) /**< Offset from EMCC Base Address: <tt> 0x0000</tt> */ 93 #define MXC_R_EMCC_MEM_SIZE ((uint32_t)0x00000004UL) /**< Offset from EMCC Base Address: <tt> 0x0004</tt> */ 94 #define MXC_R_EMCC_CACHE_CTRL ((uint32_t)0x00000100UL) /**< Offset from EMCC Base Address: <tt> 0x0100</tt> */ 95 #define MXC_R_EMCC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from EMCC Base Address: <tt> 0x0700</tt> */ 96 /**@} end of group emcc_registers */ 97 98 /** 99 * @ingroup emcc_registers 100 * @defgroup EMCC_CACHE_ID EMCC_CACHE_ID 101 * @brief Cache ID Register. 102 * @{ 103 */ 104 #define MXC_F_EMCC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */ 105 #define MXC_F_EMCC_CACHE_ID_RELNUM ((uint32_t)(0x3FUL << MXC_F_EMCC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM Mask */ 106 107 #define MXC_F_EMCC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */ 108 #define MXC_F_EMCC_CACHE_ID_PARTNUM ((uint32_t)(0xFUL << MXC_F_EMCC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM Mask */ 109 110 #define MXC_F_EMCC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */ 111 #define MXC_F_EMCC_CACHE_ID_CCHID ((uint32_t)(0x3FUL << MXC_F_EMCC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */ 112 113 /**@} end of group EMCC_CACHE_ID_Register */ 114 115 /** 116 * @ingroup emcc_registers 117 * @defgroup EMCC_MEM_SIZE EMCC_MEM_SIZE 118 * @brief Memory Configuration Register. 119 * @{ 120 */ 121 #define MXC_F_EMCC_MEM_SIZE_CCHSZ_POS 0 /**< MEM_SIZE_CCHSZ Position */ 122 #define MXC_F_EMCC_MEM_SIZE_CCHSZ ((uint32_t)(0xFFFFUL << MXC_F_EMCC_MEM_SIZE_CCHSZ_POS)) /**< MEM_SIZE_CCHSZ Mask */ 123 124 #define MXC_F_EMCC_MEM_SIZE_MEMSZ_POS 16 /**< MEM_SIZE_MEMSZ Position */ 125 #define MXC_F_EMCC_MEM_SIZE_MEMSZ ((uint32_t)(0xFFFFUL << MXC_F_EMCC_MEM_SIZE_MEMSZ_POS)) /**< MEM_SIZE_MEMSZ Mask */ 126 127 /**@} end of group EMCC_MEM_SIZE_Register */ 128 129 /** 130 * @ingroup emcc_registers 131 * @defgroup EMCC_CACHE_CTRL EMCC_CACHE_CTRL 132 * @brief Cache Control and Status Register. 133 * @{ 134 */ 135 #define MXC_F_EMCC_CACHE_CTRL_ENABLE_POS 0 /**< CACHE_CTRL_ENABLE Position */ 136 #define MXC_F_EMCC_CACHE_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_ENABLE_POS)) /**< CACHE_CTRL_ENABLE Mask */ 137 #define MXC_V_EMCC_CACHE_CTRL_ENABLE_DIS ((uint32_t)0x0UL) /**< CACHE_CTRL_ENABLE_DIS Value */ 138 #define MXC_S_EMCC_CACHE_CTRL_ENABLE_DIS (MXC_V_EMCC_CACHE_CTRL_ENABLE_DIS << MXC_F_EMCC_CACHE_CTRL_ENABLE_POS) /**< CACHE_CTRL_ENABLE_DIS Setting */ 139 #define MXC_V_EMCC_CACHE_CTRL_ENABLE_EN ((uint32_t)0x1UL) /**< CACHE_CTRL_ENABLE_EN Value */ 140 #define MXC_S_EMCC_CACHE_CTRL_ENABLE_EN (MXC_V_EMCC_CACHE_CTRL_ENABLE_EN << MXC_F_EMCC_CACHE_CTRL_ENABLE_POS) /**< CACHE_CTRL_ENABLE_EN Setting */ 141 142 #define MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_POS 1 /**< CACHE_CTRL_WRITE_ALLOC Position */ 143 #define MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_POS)) /**< CACHE_CTRL_WRITE_ALLOC Mask */ 144 #define MXC_V_EMCC_CACHE_CTRL_WRITE_ALLOC_DIS ((uint32_t)0x0UL) /**< CACHE_CTRL_WRITE_ALLOC_DIS Value */ 145 #define MXC_S_EMCC_CACHE_CTRL_WRITE_ALLOC_DIS (MXC_V_EMCC_CACHE_CTRL_WRITE_ALLOC_DIS << MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_POS) /**< CACHE_CTRL_WRITE_ALLOC_DIS Setting */ 146 #define MXC_V_EMCC_CACHE_CTRL_WRITE_ALLOC_EN ((uint32_t)0x1UL) /**< CACHE_CTRL_WRITE_ALLOC_EN Value */ 147 #define MXC_S_EMCC_CACHE_CTRL_WRITE_ALLOC_EN (MXC_V_EMCC_CACHE_CTRL_WRITE_ALLOC_EN << MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_POS) /**< CACHE_CTRL_WRITE_ALLOC_EN Setting */ 148 149 #define MXC_F_EMCC_CACHE_CTRL_CWFST_DIS_POS 2 /**< CACHE_CTRL_CWFST_DIS Position */ 150 #define MXC_F_EMCC_CACHE_CTRL_CWFST_DIS ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_CWFST_DIS_POS)) /**< CACHE_CTRL_CWFST_DIS Mask */ 151 #define MXC_V_EMCC_CACHE_CTRL_CWFST_DIS_DIS ((uint32_t)0x1UL) /**< CACHE_CTRL_CWFST_DIS_DIS Value */ 152 #define MXC_S_EMCC_CACHE_CTRL_CWFST_DIS_DIS (MXC_V_EMCC_CACHE_CTRL_CWFST_DIS_DIS << MXC_F_EMCC_CACHE_CTRL_CWFST_DIS_POS) /**< CACHE_CTRL_CWFST_DIS_DIS Setting */ 153 #define MXC_V_EMCC_CACHE_CTRL_CWFST_DIS_EN ((uint32_t)0x0UL) /**< CACHE_CTRL_CWFST_DIS_EN Value */ 154 #define MXC_S_EMCC_CACHE_CTRL_CWFST_DIS_EN (MXC_V_EMCC_CACHE_CTRL_CWFST_DIS_EN << MXC_F_EMCC_CACHE_CTRL_CWFST_DIS_POS) /**< CACHE_CTRL_CWFST_DIS_EN Setting */ 155 156 #define MXC_F_EMCC_CACHE_CTRL_READY_POS 16 /**< CACHE_CTRL_READY Position */ 157 #define MXC_F_EMCC_CACHE_CTRL_READY ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_READY_POS)) /**< CACHE_CTRL_READY Mask */ 158 #define MXC_V_EMCC_CACHE_CTRL_READY_NOTREADY ((uint32_t)0x0UL) /**< CACHE_CTRL_READY_NOTREADY Value */ 159 #define MXC_S_EMCC_CACHE_CTRL_READY_NOTREADY (MXC_V_EMCC_CACHE_CTRL_READY_NOTREADY << MXC_F_EMCC_CACHE_CTRL_READY_POS) /**< CACHE_CTRL_READY_NOTREADY Setting */ 160 #define MXC_V_EMCC_CACHE_CTRL_READY_READY ((uint32_t)0x1UL) /**< CACHE_CTRL_READY_READY Value */ 161 #define MXC_S_EMCC_CACHE_CTRL_READY_READY (MXC_V_EMCC_CACHE_CTRL_READY_READY << MXC_F_EMCC_CACHE_CTRL_READY_POS) /**< CACHE_CTRL_READY_READY Setting */ 162 163 /**@} end of group EMCC_CACHE_CTRL_Register */ 164 165 /** 166 * @ingroup emcc_registers 167 * @defgroup EMCC_INVALIDATE EMCC_INVALIDATE 168 * @brief Invalidate All Cache Contents. Any time this register location is written 169 * (regardless of the data value), the cache controller immediately begins 170 * invalidating the entire contents of the cache memory. The cache will be in 171 * bypass mode until the invalidate operation is complete. System software can 172 * examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the 173 * invalidate operation is complete. Note that it is not necessary to disable the 174 * cache controller prior to beginning this operation. Reads from this register 175 * always return 0. 176 * @{ 177 */ 178 #define MXC_F_EMCC_INVALIDATE_IA_POS 0 /**< INVALIDATE_IA Position */ 179 #define MXC_F_EMCC_INVALIDATE_IA ((uint32_t)(0xFFFFFFFFUL << MXC_F_EMCC_INVALIDATE_IA_POS)) /**< INVALIDATE_IA Mask */ 180 181 /**@} end of group EMCC_INVALIDATE_Register */ 182 183 #ifdef __cplusplus 184 } 185 #endif 186 187 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_EMCC_REGS_H_ 188
