1 /** 2 * @file dma_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup dma_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_DMA_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_DMA_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup dma 67 * @defgroup dma_registers DMA_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. 69 * @details DMA Controller Fully programmable, chaining capable DMA channels. 70 */ 71 72 /** 73 * @ingroup dma_registers 74 * Structure type to access the DMA Registers. 75 */ 76 typedef struct { 77 __IO uint32_t cfg; /**< <tt>\b 0x000:</tt> DMA CFG Register */ 78 __IO uint32_t st; /**< <tt>\b 0x004:</tt> DMA ST Register */ 79 __IO uint32_t src; /**< <tt>\b 0x008:</tt> DMA SRC Register */ 80 __IO uint32_t dst; /**< <tt>\b 0x00C:</tt> DMA DST Register */ 81 __IO uint32_t cnt; /**< <tt>\b 0x010:</tt> DMA CNT Register */ 82 __IO uint32_t src_rld; /**< <tt>\b 0x014:</tt> DMA SRC_RLD Register */ 83 __IO uint32_t dst_rld; /**< <tt>\b 0x018:</tt> DMA DST_RLD Register */ 84 __IO uint32_t cnt_rld; /**< <tt>\b 0x01C:</tt> DMA CNT_RLD Register */ 85 } mxc_dma_ch_regs_t; 86 87 typedef struct { 88 __IO uint32_t cn; /**< <tt>\b 0x000:</tt> DMA CN Register */ 89 __I uint32_t intr; /**< <tt>\b 0x004:</tt> DMA INTR Register */ 90 __R uint32_t rsv_0x8_0xff[62]; 91 __IO mxc_dma_ch_regs_t ch[16]; /**< <tt>\b 0x100:</tt> DMA CH Register */ 92 } mxc_dma_regs_t; 93 94 /* Register offsets for module DMA */ 95 /** 96 * @ingroup dma_registers 97 * @defgroup DMA_Register_Offsets Register Offsets 98 * @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address. 99 * @{ 100 */ 101 #define MXC_R_DMA_CFG ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */ 102 #define MXC_R_DMA_ST ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */ 103 #define MXC_R_DMA_SRC ((uint32_t)0x00000008UL) /**< Offset from DMA Base Address: <tt> 0x0008</tt> */ 104 #define MXC_R_DMA_DST ((uint32_t)0x0000000CUL) /**< Offset from DMA Base Address: <tt> 0x000C</tt> */ 105 #define MXC_R_DMA_CNT ((uint32_t)0x00000010UL) /**< Offset from DMA Base Address: <tt> 0x0010</tt> */ 106 #define MXC_R_DMA_SRC_RLD ((uint32_t)0x00000014UL) /**< Offset from DMA Base Address: <tt> 0x0014</tt> */ 107 #define MXC_R_DMA_DST_RLD ((uint32_t)0x00000018UL) /**< Offset from DMA Base Address: <tt> 0x0018</tt> */ 108 #define MXC_R_DMA_CNT_RLD ((uint32_t)0x0000001CUL) /**< Offset from DMA Base Address: <tt> 0x001C</tt> */ 109 #define MXC_R_DMA_CN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */ 110 #define MXC_R_DMA_INTR ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */ 111 #define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */ 112 /**@} end of group dma_registers */ 113 114 /** 115 * @ingroup dma_registers 116 * @defgroup DMA_CN DMA_CN 117 * @brief DMA Control Register. 118 * @{ 119 */ 120 #define MXC_F_DMA_CN_CH0_IEN_POS 0 /**< CN_CH0_IEN Position */ 121 #define MXC_F_DMA_CN_CH0_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH0_IEN_POS)) /**< CN_CH0_IEN Mask */ 122 #define MXC_V_DMA_CN_CH0_IEN_DIS ((uint32_t)0x0UL) /**< CN_CH0_IEN_DIS Value */ 123 #define MXC_S_DMA_CN_CH0_IEN_DIS (MXC_V_DMA_CN_CH0_IEN_DIS << MXC_F_DMA_CN_CH0_IEN_POS) /**< CN_CH0_IEN_DIS Setting */ 124 #define MXC_V_DMA_CN_CH0_IEN_EN ((uint32_t)0x1UL) /**< CN_CH0_IEN_EN Value */ 125 #define MXC_S_DMA_CN_CH0_IEN_EN (MXC_V_DMA_CN_CH0_IEN_EN << MXC_F_DMA_CN_CH0_IEN_POS) /**< CN_CH0_IEN_EN Setting */ 126 127 #define MXC_F_DMA_CN_CH1_IEN_POS 1 /**< CN_CH1_IEN Position */ 128 #define MXC_F_DMA_CN_CH1_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH1_IEN_POS)) /**< CN_CH1_IEN Mask */ 129 #define MXC_V_DMA_CN_CH1_IEN_DIS ((uint32_t)0x0UL) /**< CN_CH1_IEN_DIS Value */ 130 #define MXC_S_DMA_CN_CH1_IEN_DIS (MXC_V_DMA_CN_CH1_IEN_DIS << MXC_F_DMA_CN_CH1_IEN_POS) /**< CN_CH1_IEN_DIS Setting */ 131 #define MXC_V_DMA_CN_CH1_IEN_EN ((uint32_t)0x1UL) /**< CN_CH1_IEN_EN Value */ 132 #define MXC_S_DMA_CN_CH1_IEN_EN (MXC_V_DMA_CN_CH1_IEN_EN << MXC_F_DMA_CN_CH1_IEN_POS) /**< CN_CH1_IEN_EN Setting */ 133 134 #define MXC_F_DMA_CN_CH2_IEN_POS 2 /**< CN_CH2_IEN Position */ 135 #define MXC_F_DMA_CN_CH2_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH2_IEN_POS)) /**< CN_CH2_IEN Mask */ 136 #define MXC_V_DMA_CN_CH2_IEN_DIS ((uint32_t)0x0UL) /**< CN_CH2_IEN_DIS Value */ 137 #define MXC_S_DMA_CN_CH2_IEN_DIS (MXC_V_DMA_CN_CH2_IEN_DIS << MXC_F_DMA_CN_CH2_IEN_POS) /**< CN_CH2_IEN_DIS Setting */ 138 #define MXC_V_DMA_CN_CH2_IEN_EN ((uint32_t)0x1UL) /**< CN_CH2_IEN_EN Value */ 139 #define MXC_S_DMA_CN_CH2_IEN_EN (MXC_V_DMA_CN_CH2_IEN_EN << MXC_F_DMA_CN_CH2_IEN_POS) /**< CN_CH2_IEN_EN Setting */ 140 141 #define MXC_F_DMA_CN_CH3_IEN_POS 3 /**< CN_CH3_IEN Position */ 142 #define MXC_F_DMA_CN_CH3_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH3_IEN_POS)) /**< CN_CH3_IEN Mask */ 143 #define MXC_V_DMA_CN_CH3_IEN_DIS ((uint32_t)0x0UL) /**< CN_CH3_IEN_DIS Value */ 144 #define MXC_S_DMA_CN_CH3_IEN_DIS (MXC_V_DMA_CN_CH3_IEN_DIS << MXC_F_DMA_CN_CH3_IEN_POS) /**< CN_CH3_IEN_DIS Setting */ 145 #define MXC_V_DMA_CN_CH3_IEN_EN ((uint32_t)0x1UL) /**< CN_CH3_IEN_EN Value */ 146 #define MXC_S_DMA_CN_CH3_IEN_EN (MXC_V_DMA_CN_CH3_IEN_EN << MXC_F_DMA_CN_CH3_IEN_POS) /**< CN_CH3_IEN_EN Setting */ 147 148 #define MXC_F_DMA_CN_CH4_IEN_POS 4 /**< CN_CH4_IEN Position */ 149 #define MXC_F_DMA_CN_CH4_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH4_IEN_POS)) /**< CN_CH4_IEN Mask */ 150 #define MXC_V_DMA_CN_CH4_IEN_DIS ((uint32_t)0x0UL) /**< CN_CH4_IEN_DIS Value */ 151 #define MXC_S_DMA_CN_CH4_IEN_DIS (MXC_V_DMA_CN_CH4_IEN_DIS << MXC_F_DMA_CN_CH4_IEN_POS) /**< CN_CH4_IEN_DIS Setting */ 152 #define MXC_V_DMA_CN_CH4_IEN_EN ((uint32_t)0x1UL) /**< CN_CH4_IEN_EN Value */ 153 #define MXC_S_DMA_CN_CH4_IEN_EN (MXC_V_DMA_CN_CH4_IEN_EN << MXC_F_DMA_CN_CH4_IEN_POS) /**< CN_CH4_IEN_EN Setting */ 154 155 #define MXC_F_DMA_CN_CH5_IEN_POS 5 /**< CN_CH5_IEN Position */ 156 #define MXC_F_DMA_CN_CH5_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH5_IEN_POS)) /**< CN_CH5_IEN Mask */ 157 #define MXC_V_DMA_CN_CH5_IEN_DIS ((uint32_t)0x0UL) /**< CN_CH5_IEN_DIS Value */ 158 #define MXC_S_DMA_CN_CH5_IEN_DIS (MXC_V_DMA_CN_CH5_IEN_DIS << MXC_F_DMA_CN_CH5_IEN_POS) /**< CN_CH5_IEN_DIS Setting */ 159 #define MXC_V_DMA_CN_CH5_IEN_EN ((uint32_t)0x1UL) /**< CN_CH5_IEN_EN Value */ 160 #define MXC_S_DMA_CN_CH5_IEN_EN (MXC_V_DMA_CN_CH5_IEN_EN << MXC_F_DMA_CN_CH5_IEN_POS) /**< CN_CH5_IEN_EN Setting */ 161 162 #define MXC_F_DMA_CN_CH6_IEN_POS 6 /**< CN_CH6_IEN Position */ 163 #define MXC_F_DMA_CN_CH6_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH6_IEN_POS)) /**< CN_CH6_IEN Mask */ 164 #define MXC_V_DMA_CN_CH6_IEN_DIS ((uint32_t)0x0UL) /**< CN_CH6_IEN_DIS Value */ 165 #define MXC_S_DMA_CN_CH6_IEN_DIS (MXC_V_DMA_CN_CH6_IEN_DIS << MXC_F_DMA_CN_CH6_IEN_POS) /**< CN_CH6_IEN_DIS Setting */ 166 #define MXC_V_DMA_CN_CH6_IEN_EN ((uint32_t)0x1UL) /**< CN_CH6_IEN_EN Value */ 167 #define MXC_S_DMA_CN_CH6_IEN_EN (MXC_V_DMA_CN_CH6_IEN_EN << MXC_F_DMA_CN_CH6_IEN_POS) /**< CN_CH6_IEN_EN Setting */ 168 169 #define MXC_F_DMA_CN_CH7_IEN_POS 7 /**< CN_CH7_IEN Position */ 170 #define MXC_F_DMA_CN_CH7_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH7_IEN_POS)) /**< CN_CH7_IEN Mask */ 171 #define MXC_V_DMA_CN_CH7_IEN_DIS ((uint32_t)0x0UL) /**< CN_CH7_IEN_DIS Value */ 172 #define MXC_S_DMA_CN_CH7_IEN_DIS (MXC_V_DMA_CN_CH7_IEN_DIS << MXC_F_DMA_CN_CH7_IEN_POS) /**< CN_CH7_IEN_DIS Setting */ 173 #define MXC_V_DMA_CN_CH7_IEN_EN ((uint32_t)0x1UL) /**< CN_CH7_IEN_EN Value */ 174 #define MXC_S_DMA_CN_CH7_IEN_EN (MXC_V_DMA_CN_CH7_IEN_EN << MXC_F_DMA_CN_CH7_IEN_POS) /**< CN_CH7_IEN_EN Setting */ 175 176 #define MXC_F_DMA_CN_CH8_IEN_POS 8 /**< CN_CH8_IEN Position */ 177 #define MXC_F_DMA_CN_CH8_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH8_IEN_POS)) /**< CN_CH8_IEN Mask */ 178 #define MXC_V_DMA_CN_CH8_IEN_DIS ((uint32_t)0x0UL) /**< CN_CH8_IEN_DIS Value */ 179 #define MXC_S_DMA_CN_CH8_IEN_DIS (MXC_V_DMA_CN_CH8_IEN_DIS << MXC_F_DMA_CN_CH8_IEN_POS) /**< CN_CH8_IEN_DIS Setting */ 180 #define MXC_V_DMA_CN_CH8_IEN_EN ((uint32_t)0x1UL) /**< CN_CH8_IEN_EN Value */ 181 #define MXC_S_DMA_CN_CH8_IEN_EN (MXC_V_DMA_CN_CH8_IEN_EN << MXC_F_DMA_CN_CH8_IEN_POS) /**< CN_CH8_IEN_EN Setting */ 182 183 #define MXC_F_DMA_CN_CH9_IEN_POS 9 /**< CN_CH9_IEN Position */ 184 #define MXC_F_DMA_CN_CH9_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH9_IEN_POS)) /**< CN_CH9_IEN Mask */ 185 #define MXC_V_DMA_CN_CH9_IEN_DIS ((uint32_t)0x0UL) /**< CN_CH9_IEN_DIS Value */ 186 #define MXC_S_DMA_CN_CH9_IEN_DIS (MXC_V_DMA_CN_CH9_IEN_DIS << MXC_F_DMA_CN_CH9_IEN_POS) /**< CN_CH9_IEN_DIS Setting */ 187 #define MXC_V_DMA_CN_CH9_IEN_EN ((uint32_t)0x1UL) /**< CN_CH9_IEN_EN Value */ 188 #define MXC_S_DMA_CN_CH9_IEN_EN (MXC_V_DMA_CN_CH9_IEN_EN << MXC_F_DMA_CN_CH9_IEN_POS) /**< CN_CH9_IEN_EN Setting */ 189 190 #define MXC_F_DMA_CN_CH10_IEN_POS 10 /**< CN_CH10_IEN Position */ 191 #define MXC_F_DMA_CN_CH10_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH10_IEN_POS)) /**< CN_CH10_IEN Mask */ 192 #define MXC_V_DMA_CN_CH10_IEN_DIS ((uint32_t)0x0UL) /**< CN_CH10_IEN_DIS Value */ 193 #define MXC_S_DMA_CN_CH10_IEN_DIS (MXC_V_DMA_CN_CH10_IEN_DIS << MXC_F_DMA_CN_CH10_IEN_POS) /**< CN_CH10_IEN_DIS Setting */ 194 #define MXC_V_DMA_CN_CH10_IEN_EN ((uint32_t)0x1UL) /**< CN_CH10_IEN_EN Value */ 195 #define MXC_S_DMA_CN_CH10_IEN_EN (MXC_V_DMA_CN_CH10_IEN_EN << MXC_F_DMA_CN_CH10_IEN_POS) /**< CN_CH10_IEN_EN Setting */ 196 197 #define MXC_F_DMA_CN_CH11_IEN_POS 11 /**< CN_CH11_IEN Position */ 198 #define MXC_F_DMA_CN_CH11_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH11_IEN_POS)) /**< CN_CH11_IEN Mask */ 199 #define MXC_V_DMA_CN_CH11_IEN_DIS ((uint32_t)0x0UL) /**< CN_CH11_IEN_DIS Value */ 200 #define MXC_S_DMA_CN_CH11_IEN_DIS (MXC_V_DMA_CN_CH11_IEN_DIS << MXC_F_DMA_CN_CH11_IEN_POS) /**< CN_CH11_IEN_DIS Setting */ 201 #define MXC_V_DMA_CN_CH11_IEN_EN ((uint32_t)0x1UL) /**< CN_CH11_IEN_EN Value */ 202 #define MXC_S_DMA_CN_CH11_IEN_EN (MXC_V_DMA_CN_CH11_IEN_EN << MXC_F_DMA_CN_CH11_IEN_POS) /**< CN_CH11_IEN_EN Setting */ 203 204 #define MXC_F_DMA_CN_CH12_IEN_POS 12 /**< CN_CH12_IEN Position */ 205 #define MXC_F_DMA_CN_CH12_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH12_IEN_POS)) /**< CN_CH12_IEN Mask */ 206 #define MXC_V_DMA_CN_CH12_IEN_DIS ((uint32_t)0x0UL) /**< CN_CH12_IEN_DIS Value */ 207 #define MXC_S_DMA_CN_CH12_IEN_DIS (MXC_V_DMA_CN_CH12_IEN_DIS << MXC_F_DMA_CN_CH12_IEN_POS) /**< CN_CH12_IEN_DIS Setting */ 208 #define MXC_V_DMA_CN_CH12_IEN_EN ((uint32_t)0x1UL) /**< CN_CH12_IEN_EN Value */ 209 #define MXC_S_DMA_CN_CH12_IEN_EN (MXC_V_DMA_CN_CH12_IEN_EN << MXC_F_DMA_CN_CH12_IEN_POS) /**< CN_CH12_IEN_EN Setting */ 210 211 #define MXC_F_DMA_CN_CH13_IEN_POS 13 /**< CN_CH13_IEN Position */ 212 #define MXC_F_DMA_CN_CH13_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH13_IEN_POS)) /**< CN_CH13_IEN Mask */ 213 #define MXC_V_DMA_CN_CH13_IEN_DIS ((uint32_t)0x0UL) /**< CN_CH13_IEN_DIS Value */ 214 #define MXC_S_DMA_CN_CH13_IEN_DIS (MXC_V_DMA_CN_CH13_IEN_DIS << MXC_F_DMA_CN_CH13_IEN_POS) /**< CN_CH13_IEN_DIS Setting */ 215 #define MXC_V_DMA_CN_CH13_IEN_EN ((uint32_t)0x1UL) /**< CN_CH13_IEN_EN Value */ 216 #define MXC_S_DMA_CN_CH13_IEN_EN (MXC_V_DMA_CN_CH13_IEN_EN << MXC_F_DMA_CN_CH13_IEN_POS) /**< CN_CH13_IEN_EN Setting */ 217 218 #define MXC_F_DMA_CN_CH14_IEN_POS 14 /**< CN_CH14_IEN Position */ 219 #define MXC_F_DMA_CN_CH14_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH14_IEN_POS)) /**< CN_CH14_IEN Mask */ 220 #define MXC_V_DMA_CN_CH14_IEN_DIS ((uint32_t)0x0UL) /**< CN_CH14_IEN_DIS Value */ 221 #define MXC_S_DMA_CN_CH14_IEN_DIS (MXC_V_DMA_CN_CH14_IEN_DIS << MXC_F_DMA_CN_CH14_IEN_POS) /**< CN_CH14_IEN_DIS Setting */ 222 #define MXC_V_DMA_CN_CH14_IEN_EN ((uint32_t)0x1UL) /**< CN_CH14_IEN_EN Value */ 223 #define MXC_S_DMA_CN_CH14_IEN_EN (MXC_V_DMA_CN_CH14_IEN_EN << MXC_F_DMA_CN_CH14_IEN_POS) /**< CN_CH14_IEN_EN Setting */ 224 225 #define MXC_F_DMA_CN_CH15_IEN_POS 15 /**< CN_CH15_IEN Position */ 226 #define MXC_F_DMA_CN_CH15_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH15_IEN_POS)) /**< CN_CH15_IEN Mask */ 227 #define MXC_V_DMA_CN_CH15_IEN_DIS ((uint32_t)0x0UL) /**< CN_CH15_IEN_DIS Value */ 228 #define MXC_S_DMA_CN_CH15_IEN_DIS (MXC_V_DMA_CN_CH15_IEN_DIS << MXC_F_DMA_CN_CH15_IEN_POS) /**< CN_CH15_IEN_DIS Setting */ 229 #define MXC_V_DMA_CN_CH15_IEN_EN ((uint32_t)0x1UL) /**< CN_CH15_IEN_EN Value */ 230 #define MXC_S_DMA_CN_CH15_IEN_EN (MXC_V_DMA_CN_CH15_IEN_EN << MXC_F_DMA_CN_CH15_IEN_POS) /**< CN_CH15_IEN_EN Setting */ 231 232 /**@} end of group DMA_CN_Register */ 233 234 /** 235 * @ingroup dma_registers 236 * @defgroup DMA_INTR DMA_INTR 237 * @brief DMA Interrupt Register. 238 * @{ 239 */ 240 #define MXC_F_DMA_INTR_CH0_IPEND_POS 0 /**< INTR_CH0_IPEND Position */ 241 #define MXC_F_DMA_INTR_CH0_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH0_IPEND_POS)) /**< INTR_CH0_IPEND Mask */ 242 #define MXC_V_DMA_INTR_CH0_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INTR_CH0_IPEND_INACTIVE Value */ 243 #define MXC_S_DMA_INTR_CH0_IPEND_INACTIVE (MXC_V_DMA_INTR_CH0_IPEND_INACTIVE << MXC_F_DMA_INTR_CH0_IPEND_POS) /**< INTR_CH0_IPEND_INACTIVE Setting */ 244 #define MXC_V_DMA_INTR_CH0_IPEND_PENDING ((uint32_t)0x1UL) /**< INTR_CH0_IPEND_PENDING Value */ 245 #define MXC_S_DMA_INTR_CH0_IPEND_PENDING (MXC_V_DMA_INTR_CH0_IPEND_PENDING << MXC_F_DMA_INTR_CH0_IPEND_POS) /**< INTR_CH0_IPEND_PENDING Setting */ 246 247 #define MXC_F_DMA_INTR_CH1_IPEND_POS 1 /**< INTR_CH1_IPEND Position */ 248 #define MXC_F_DMA_INTR_CH1_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH1_IPEND_POS)) /**< INTR_CH1_IPEND Mask */ 249 #define MXC_V_DMA_INTR_CH1_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INTR_CH1_IPEND_INACTIVE Value */ 250 #define MXC_S_DMA_INTR_CH1_IPEND_INACTIVE (MXC_V_DMA_INTR_CH1_IPEND_INACTIVE << MXC_F_DMA_INTR_CH1_IPEND_POS) /**< INTR_CH1_IPEND_INACTIVE Setting */ 251 #define MXC_V_DMA_INTR_CH1_IPEND_PENDING ((uint32_t)0x1UL) /**< INTR_CH1_IPEND_PENDING Value */ 252 #define MXC_S_DMA_INTR_CH1_IPEND_PENDING (MXC_V_DMA_INTR_CH1_IPEND_PENDING << MXC_F_DMA_INTR_CH1_IPEND_POS) /**< INTR_CH1_IPEND_PENDING Setting */ 253 254 #define MXC_F_DMA_INTR_CH2_IPEND_POS 2 /**< INTR_CH2_IPEND Position */ 255 #define MXC_F_DMA_INTR_CH2_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH2_IPEND_POS)) /**< INTR_CH2_IPEND Mask */ 256 #define MXC_V_DMA_INTR_CH2_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INTR_CH2_IPEND_INACTIVE Value */ 257 #define MXC_S_DMA_INTR_CH2_IPEND_INACTIVE (MXC_V_DMA_INTR_CH2_IPEND_INACTIVE << MXC_F_DMA_INTR_CH2_IPEND_POS) /**< INTR_CH2_IPEND_INACTIVE Setting */ 258 #define MXC_V_DMA_INTR_CH2_IPEND_PENDING ((uint32_t)0x1UL) /**< INTR_CH2_IPEND_PENDING Value */ 259 #define MXC_S_DMA_INTR_CH2_IPEND_PENDING (MXC_V_DMA_INTR_CH2_IPEND_PENDING << MXC_F_DMA_INTR_CH2_IPEND_POS) /**< INTR_CH2_IPEND_PENDING Setting */ 260 261 #define MXC_F_DMA_INTR_CH3_IPEND_POS 3 /**< INTR_CH3_IPEND Position */ 262 #define MXC_F_DMA_INTR_CH3_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH3_IPEND_POS)) /**< INTR_CH3_IPEND Mask */ 263 #define MXC_V_DMA_INTR_CH3_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INTR_CH3_IPEND_INACTIVE Value */ 264 #define MXC_S_DMA_INTR_CH3_IPEND_INACTIVE (MXC_V_DMA_INTR_CH3_IPEND_INACTIVE << MXC_F_DMA_INTR_CH3_IPEND_POS) /**< INTR_CH3_IPEND_INACTIVE Setting */ 265 #define MXC_V_DMA_INTR_CH3_IPEND_PENDING ((uint32_t)0x1UL) /**< INTR_CH3_IPEND_PENDING Value */ 266 #define MXC_S_DMA_INTR_CH3_IPEND_PENDING (MXC_V_DMA_INTR_CH3_IPEND_PENDING << MXC_F_DMA_INTR_CH3_IPEND_POS) /**< INTR_CH3_IPEND_PENDING Setting */ 267 268 #define MXC_F_DMA_INTR_CH4_IPEND_POS 4 /**< INTR_CH4_IPEND Position */ 269 #define MXC_F_DMA_INTR_CH4_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH4_IPEND_POS)) /**< INTR_CH4_IPEND Mask */ 270 #define MXC_V_DMA_INTR_CH4_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INTR_CH4_IPEND_INACTIVE Value */ 271 #define MXC_S_DMA_INTR_CH4_IPEND_INACTIVE (MXC_V_DMA_INTR_CH4_IPEND_INACTIVE << MXC_F_DMA_INTR_CH4_IPEND_POS) /**< INTR_CH4_IPEND_INACTIVE Setting */ 272 #define MXC_V_DMA_INTR_CH4_IPEND_PENDING ((uint32_t)0x1UL) /**< INTR_CH4_IPEND_PENDING Value */ 273 #define MXC_S_DMA_INTR_CH4_IPEND_PENDING (MXC_V_DMA_INTR_CH4_IPEND_PENDING << MXC_F_DMA_INTR_CH4_IPEND_POS) /**< INTR_CH4_IPEND_PENDING Setting */ 274 275 #define MXC_F_DMA_INTR_CH5_IPEND_POS 5 /**< INTR_CH5_IPEND Position */ 276 #define MXC_F_DMA_INTR_CH5_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH5_IPEND_POS)) /**< INTR_CH5_IPEND Mask */ 277 #define MXC_V_DMA_INTR_CH5_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INTR_CH5_IPEND_INACTIVE Value */ 278 #define MXC_S_DMA_INTR_CH5_IPEND_INACTIVE (MXC_V_DMA_INTR_CH5_IPEND_INACTIVE << MXC_F_DMA_INTR_CH5_IPEND_POS) /**< INTR_CH5_IPEND_INACTIVE Setting */ 279 #define MXC_V_DMA_INTR_CH5_IPEND_PENDING ((uint32_t)0x1UL) /**< INTR_CH5_IPEND_PENDING Value */ 280 #define MXC_S_DMA_INTR_CH5_IPEND_PENDING (MXC_V_DMA_INTR_CH5_IPEND_PENDING << MXC_F_DMA_INTR_CH5_IPEND_POS) /**< INTR_CH5_IPEND_PENDING Setting */ 281 282 #define MXC_F_DMA_INTR_CH6_IPEND_POS 6 /**< INTR_CH6_IPEND Position */ 283 #define MXC_F_DMA_INTR_CH6_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH6_IPEND_POS)) /**< INTR_CH6_IPEND Mask */ 284 #define MXC_V_DMA_INTR_CH6_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INTR_CH6_IPEND_INACTIVE Value */ 285 #define MXC_S_DMA_INTR_CH6_IPEND_INACTIVE (MXC_V_DMA_INTR_CH6_IPEND_INACTIVE << MXC_F_DMA_INTR_CH6_IPEND_POS) /**< INTR_CH6_IPEND_INACTIVE Setting */ 286 #define MXC_V_DMA_INTR_CH6_IPEND_PENDING ((uint32_t)0x1UL) /**< INTR_CH6_IPEND_PENDING Value */ 287 #define MXC_S_DMA_INTR_CH6_IPEND_PENDING (MXC_V_DMA_INTR_CH6_IPEND_PENDING << MXC_F_DMA_INTR_CH6_IPEND_POS) /**< INTR_CH6_IPEND_PENDING Setting */ 288 289 #define MXC_F_DMA_INTR_CH7_IPEND_POS 7 /**< INTR_CH7_IPEND Position */ 290 #define MXC_F_DMA_INTR_CH7_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH7_IPEND_POS)) /**< INTR_CH7_IPEND Mask */ 291 #define MXC_V_DMA_INTR_CH7_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INTR_CH7_IPEND_INACTIVE Value */ 292 #define MXC_S_DMA_INTR_CH7_IPEND_INACTIVE (MXC_V_DMA_INTR_CH7_IPEND_INACTIVE << MXC_F_DMA_INTR_CH7_IPEND_POS) /**< INTR_CH7_IPEND_INACTIVE Setting */ 293 #define MXC_V_DMA_INTR_CH7_IPEND_PENDING ((uint32_t)0x1UL) /**< INTR_CH7_IPEND_PENDING Value */ 294 #define MXC_S_DMA_INTR_CH7_IPEND_PENDING (MXC_V_DMA_INTR_CH7_IPEND_PENDING << MXC_F_DMA_INTR_CH7_IPEND_POS) /**< INTR_CH7_IPEND_PENDING Setting */ 295 296 #define MXC_F_DMA_INTR_CH8_IPEND_POS 8 /**< INTR_CH8_IPEND Position */ 297 #define MXC_F_DMA_INTR_CH8_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH8_IPEND_POS)) /**< INTR_CH8_IPEND Mask */ 298 #define MXC_V_DMA_INTR_CH8_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INTR_CH8_IPEND_INACTIVE Value */ 299 #define MXC_S_DMA_INTR_CH8_IPEND_INACTIVE (MXC_V_DMA_INTR_CH8_IPEND_INACTIVE << MXC_F_DMA_INTR_CH8_IPEND_POS) /**< INTR_CH8_IPEND_INACTIVE Setting */ 300 #define MXC_V_DMA_INTR_CH8_IPEND_PENDING ((uint32_t)0x1UL) /**< INTR_CH8_IPEND_PENDING Value */ 301 #define MXC_S_DMA_INTR_CH8_IPEND_PENDING (MXC_V_DMA_INTR_CH8_IPEND_PENDING << MXC_F_DMA_INTR_CH8_IPEND_POS) /**< INTR_CH8_IPEND_PENDING Setting */ 302 303 #define MXC_F_DMA_INTR_CH9_IPEND_POS 9 /**< INTR_CH9_IPEND Position */ 304 #define MXC_F_DMA_INTR_CH9_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH9_IPEND_POS)) /**< INTR_CH9_IPEND Mask */ 305 #define MXC_V_DMA_INTR_CH9_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INTR_CH9_IPEND_INACTIVE Value */ 306 #define MXC_S_DMA_INTR_CH9_IPEND_INACTIVE (MXC_V_DMA_INTR_CH9_IPEND_INACTIVE << MXC_F_DMA_INTR_CH9_IPEND_POS) /**< INTR_CH9_IPEND_INACTIVE Setting */ 307 #define MXC_V_DMA_INTR_CH9_IPEND_PENDING ((uint32_t)0x1UL) /**< INTR_CH9_IPEND_PENDING Value */ 308 #define MXC_S_DMA_INTR_CH9_IPEND_PENDING (MXC_V_DMA_INTR_CH9_IPEND_PENDING << MXC_F_DMA_INTR_CH9_IPEND_POS) /**< INTR_CH9_IPEND_PENDING Setting */ 309 310 #define MXC_F_DMA_INTR_CH10_IPEND_POS 10 /**< INTR_CH10_IPEND Position */ 311 #define MXC_F_DMA_INTR_CH10_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH10_IPEND_POS)) /**< INTR_CH10_IPEND Mask */ 312 #define MXC_V_DMA_INTR_CH10_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INTR_CH10_IPEND_INACTIVE Value */ 313 #define MXC_S_DMA_INTR_CH10_IPEND_INACTIVE (MXC_V_DMA_INTR_CH10_IPEND_INACTIVE << MXC_F_DMA_INTR_CH10_IPEND_POS) /**< INTR_CH10_IPEND_INACTIVE Setting */ 314 #define MXC_V_DMA_INTR_CH10_IPEND_PENDING ((uint32_t)0x1UL) /**< INTR_CH10_IPEND_PENDING Value */ 315 #define MXC_S_DMA_INTR_CH10_IPEND_PENDING (MXC_V_DMA_INTR_CH10_IPEND_PENDING << MXC_F_DMA_INTR_CH10_IPEND_POS) /**< INTR_CH10_IPEND_PENDING Setting */ 316 317 #define MXC_F_DMA_INTR_CH11_IPEND_POS 11 /**< INTR_CH11_IPEND Position */ 318 #define MXC_F_DMA_INTR_CH11_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH11_IPEND_POS)) /**< INTR_CH11_IPEND Mask */ 319 #define MXC_V_DMA_INTR_CH11_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INTR_CH11_IPEND_INACTIVE Value */ 320 #define MXC_S_DMA_INTR_CH11_IPEND_INACTIVE (MXC_V_DMA_INTR_CH11_IPEND_INACTIVE << MXC_F_DMA_INTR_CH11_IPEND_POS) /**< INTR_CH11_IPEND_INACTIVE Setting */ 321 #define MXC_V_DMA_INTR_CH11_IPEND_PENDING ((uint32_t)0x1UL) /**< INTR_CH11_IPEND_PENDING Value */ 322 #define MXC_S_DMA_INTR_CH11_IPEND_PENDING (MXC_V_DMA_INTR_CH11_IPEND_PENDING << MXC_F_DMA_INTR_CH11_IPEND_POS) /**< INTR_CH11_IPEND_PENDING Setting */ 323 324 #define MXC_F_DMA_INTR_CH12_IPEND_POS 12 /**< INTR_CH12_IPEND Position */ 325 #define MXC_F_DMA_INTR_CH12_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH12_IPEND_POS)) /**< INTR_CH12_IPEND Mask */ 326 #define MXC_V_DMA_INTR_CH12_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INTR_CH12_IPEND_INACTIVE Value */ 327 #define MXC_S_DMA_INTR_CH12_IPEND_INACTIVE (MXC_V_DMA_INTR_CH12_IPEND_INACTIVE << MXC_F_DMA_INTR_CH12_IPEND_POS) /**< INTR_CH12_IPEND_INACTIVE Setting */ 328 #define MXC_V_DMA_INTR_CH12_IPEND_PENDING ((uint32_t)0x1UL) /**< INTR_CH12_IPEND_PENDING Value */ 329 #define MXC_S_DMA_INTR_CH12_IPEND_PENDING (MXC_V_DMA_INTR_CH12_IPEND_PENDING << MXC_F_DMA_INTR_CH12_IPEND_POS) /**< INTR_CH12_IPEND_PENDING Setting */ 330 331 #define MXC_F_DMA_INTR_CH13_IPEND_POS 13 /**< INTR_CH13_IPEND Position */ 332 #define MXC_F_DMA_INTR_CH13_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH13_IPEND_POS)) /**< INTR_CH13_IPEND Mask */ 333 #define MXC_V_DMA_INTR_CH13_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INTR_CH13_IPEND_INACTIVE Value */ 334 #define MXC_S_DMA_INTR_CH13_IPEND_INACTIVE (MXC_V_DMA_INTR_CH13_IPEND_INACTIVE << MXC_F_DMA_INTR_CH13_IPEND_POS) /**< INTR_CH13_IPEND_INACTIVE Setting */ 335 #define MXC_V_DMA_INTR_CH13_IPEND_PENDING ((uint32_t)0x1UL) /**< INTR_CH13_IPEND_PENDING Value */ 336 #define MXC_S_DMA_INTR_CH13_IPEND_PENDING (MXC_V_DMA_INTR_CH13_IPEND_PENDING << MXC_F_DMA_INTR_CH13_IPEND_POS) /**< INTR_CH13_IPEND_PENDING Setting */ 337 338 #define MXC_F_DMA_INTR_CH14_IPEND_POS 14 /**< INTR_CH14_IPEND Position */ 339 #define MXC_F_DMA_INTR_CH14_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH14_IPEND_POS)) /**< INTR_CH14_IPEND Mask */ 340 #define MXC_V_DMA_INTR_CH14_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INTR_CH14_IPEND_INACTIVE Value */ 341 #define MXC_S_DMA_INTR_CH14_IPEND_INACTIVE (MXC_V_DMA_INTR_CH14_IPEND_INACTIVE << MXC_F_DMA_INTR_CH14_IPEND_POS) /**< INTR_CH14_IPEND_INACTIVE Setting */ 342 #define MXC_V_DMA_INTR_CH14_IPEND_PENDING ((uint32_t)0x1UL) /**< INTR_CH14_IPEND_PENDING Value */ 343 #define MXC_S_DMA_INTR_CH14_IPEND_PENDING (MXC_V_DMA_INTR_CH14_IPEND_PENDING << MXC_F_DMA_INTR_CH14_IPEND_POS) /**< INTR_CH14_IPEND_PENDING Setting */ 344 345 #define MXC_F_DMA_INTR_CH15_IPEND_POS 15 /**< INTR_CH15_IPEND Position */ 346 #define MXC_F_DMA_INTR_CH15_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH15_IPEND_POS)) /**< INTR_CH15_IPEND Mask */ 347 #define MXC_V_DMA_INTR_CH15_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INTR_CH15_IPEND_INACTIVE Value */ 348 #define MXC_S_DMA_INTR_CH15_IPEND_INACTIVE (MXC_V_DMA_INTR_CH15_IPEND_INACTIVE << MXC_F_DMA_INTR_CH15_IPEND_POS) /**< INTR_CH15_IPEND_INACTIVE Setting */ 349 #define MXC_V_DMA_INTR_CH15_IPEND_PENDING ((uint32_t)0x1UL) /**< INTR_CH15_IPEND_PENDING Value */ 350 #define MXC_S_DMA_INTR_CH15_IPEND_PENDING (MXC_V_DMA_INTR_CH15_IPEND_PENDING << MXC_F_DMA_INTR_CH15_IPEND_POS) /**< INTR_CH15_IPEND_PENDING Setting */ 351 352 /**@} end of group DMA_INTR_Register */ 353 354 /** 355 * @ingroup dma_registers 356 * @defgroup DMA_CFG DMA_CFG 357 * @brief DMA Channel Configuration Register. 358 * @{ 359 */ 360 #define MXC_F_DMA_CFG_CHEN_POS 0 /**< CFG_CHEN Position */ 361 #define MXC_F_DMA_CFG_CHEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHEN_POS)) /**< CFG_CHEN Mask */ 362 #define MXC_V_DMA_CFG_CHEN_DIS ((uint32_t)0x0UL) /**< CFG_CHEN_DIS Value */ 363 #define MXC_S_DMA_CFG_CHEN_DIS (MXC_V_DMA_CFG_CHEN_DIS << MXC_F_DMA_CFG_CHEN_POS) /**< CFG_CHEN_DIS Setting */ 364 #define MXC_V_DMA_CFG_CHEN_EN ((uint32_t)0x1UL) /**< CFG_CHEN_EN Value */ 365 #define MXC_S_DMA_CFG_CHEN_EN (MXC_V_DMA_CFG_CHEN_EN << MXC_F_DMA_CFG_CHEN_POS) /**< CFG_CHEN_EN Setting */ 366 367 #define MXC_F_DMA_CFG_RLDEN_POS 1 /**< CFG_RLDEN Position */ 368 #define MXC_F_DMA_CFG_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_RLDEN_POS)) /**< CFG_RLDEN Mask */ 369 #define MXC_V_DMA_CFG_RLDEN_DIS ((uint32_t)0x0UL) /**< CFG_RLDEN_DIS Value */ 370 #define MXC_S_DMA_CFG_RLDEN_DIS (MXC_V_DMA_CFG_RLDEN_DIS << MXC_F_DMA_CFG_RLDEN_POS) /**< CFG_RLDEN_DIS Setting */ 371 #define MXC_V_DMA_CFG_RLDEN_EN ((uint32_t)0x1UL) /**< CFG_RLDEN_EN Value */ 372 #define MXC_S_DMA_CFG_RLDEN_EN (MXC_V_DMA_CFG_RLDEN_EN << MXC_F_DMA_CFG_RLDEN_POS) /**< CFG_RLDEN_EN Setting */ 373 374 #define MXC_F_DMA_CFG_PRI_POS 2 /**< CFG_PRI Position */ 375 #define MXC_F_DMA_CFG_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PRI_POS)) /**< CFG_PRI Mask */ 376 #define MXC_V_DMA_CFG_PRI_HIGH ((uint32_t)0x0UL) /**< CFG_PRI_HIGH Value */ 377 #define MXC_S_DMA_CFG_PRI_HIGH (MXC_V_DMA_CFG_PRI_HIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_HIGH Setting */ 378 #define MXC_V_DMA_CFG_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CFG_PRI_MEDHIGH Value */ 379 #define MXC_S_DMA_CFG_PRI_MEDHIGH (MXC_V_DMA_CFG_PRI_MEDHIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDHIGH Setting */ 380 #define MXC_V_DMA_CFG_PRI_MEDLOW ((uint32_t)0x2UL) /**< CFG_PRI_MEDLOW Value */ 381 #define MXC_S_DMA_CFG_PRI_MEDLOW (MXC_V_DMA_CFG_PRI_MEDLOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDLOW Setting */ 382 #define MXC_V_DMA_CFG_PRI_LOW ((uint32_t)0x3UL) /**< CFG_PRI_LOW Value */ 383 #define MXC_S_DMA_CFG_PRI_LOW (MXC_V_DMA_CFG_PRI_LOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_LOW Setting */ 384 385 #define MXC_F_DMA_CFG_REQSEL_POS 4 /**< CFG_REQSEL Position */ 386 #define MXC_F_DMA_CFG_REQSEL ((uint32_t)(0x3FUL << MXC_F_DMA_CFG_REQSEL_POS)) /**< CFG_REQSEL Mask */ 387 #define MXC_V_DMA_CFG_REQSEL_MEMTOMEM ((uint32_t)0x0UL) /**< CFG_REQSEL_MEMTOMEM Value */ 388 #define MXC_S_DMA_CFG_REQSEL_MEMTOMEM (MXC_V_DMA_CFG_REQSEL_MEMTOMEM << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_MEMTOMEM Setting */ 389 #define MXC_V_DMA_CFG_REQSEL_SPI0RX ((uint32_t)0x1UL) /**< CFG_REQSEL_SPI0RX Value */ 390 #define MXC_S_DMA_CFG_REQSEL_SPI0RX (MXC_V_DMA_CFG_REQSEL_SPI0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0RX Setting */ 391 #define MXC_V_DMA_CFG_REQSEL_SPI1RX ((uint32_t)0x2UL) /**< CFG_REQSEL_SPI1RX Value */ 392 #define MXC_S_DMA_CFG_REQSEL_SPI1RX (MXC_V_DMA_CFG_REQSEL_SPI1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1RX Setting */ 393 #define MXC_V_DMA_CFG_REQSEL_SPI2RX ((uint32_t)0x3UL) /**< CFG_REQSEL_SPI2RX Value */ 394 #define MXC_S_DMA_CFG_REQSEL_SPI2RX (MXC_V_DMA_CFG_REQSEL_SPI2RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI2RX Setting */ 395 #define MXC_V_DMA_CFG_REQSEL_UART0RX ((uint32_t)0x4UL) /**< CFG_REQSEL_UART0RX Value */ 396 #define MXC_S_DMA_CFG_REQSEL_UART0RX (MXC_V_DMA_CFG_REQSEL_UART0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0RX Setting */ 397 #define MXC_V_DMA_CFG_REQSEL_UART1RX ((uint32_t)0x5UL) /**< CFG_REQSEL_UART1RX Value */ 398 #define MXC_S_DMA_CFG_REQSEL_UART1RX (MXC_V_DMA_CFG_REQSEL_UART1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1RX Setting */ 399 #define MXC_V_DMA_CFG_REQSEL_I2C0RX ((uint32_t)0x7UL) /**< CFG_REQSEL_I2C0RX Value */ 400 #define MXC_S_DMA_CFG_REQSEL_I2C0RX (MXC_V_DMA_CFG_REQSEL_I2C0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0RX Setting */ 401 #define MXC_V_DMA_CFG_REQSEL_I2C1RX ((uint32_t)0x8UL) /**< CFG_REQSEL_I2C1RX Value */ 402 #define MXC_S_DMA_CFG_REQSEL_I2C1RX (MXC_V_DMA_CFG_REQSEL_I2C1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1RX Setting */ 403 #define MXC_V_DMA_CFG_REQSEL_ADC ((uint32_t)0x9UL) /**< CFG_REQSEL_ADC Value */ 404 #define MXC_S_DMA_CFG_REQSEL_ADC (MXC_V_DMA_CFG_REQSEL_ADC << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_ADC Setting */ 405 #define MXC_V_DMA_CFG_REQSEL_UART2RX ((uint32_t)0xEUL) /**< CFG_REQSEL_UART2RX Value */ 406 #define MXC_S_DMA_CFG_REQSEL_UART2RX (MXC_V_DMA_CFG_REQSEL_UART2RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART2RX Setting */ 407 #define MXC_V_DMA_CFG_REQSEL_SPI3RX ((uint32_t)0xFUL) /**< CFG_REQSEL_SPI3RX Value */ 408 #define MXC_S_DMA_CFG_REQSEL_SPI3RX (MXC_V_DMA_CFG_REQSEL_SPI3RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI3RX Setting */ 409 #define MXC_V_DMA_CFG_REQSEL_SPIMSSRX ((uint32_t)0x10UL) /**< CFG_REQSEL_SPIMSSRX Value */ 410 #define MXC_S_DMA_CFG_REQSEL_SPIMSSRX (MXC_V_DMA_CFG_REQSEL_SPIMSSRX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPIMSSRX Setting */ 411 #define MXC_V_DMA_CFG_REQSEL_USBRXEP1 ((uint32_t)0x11UL) /**< CFG_REQSEL_USBRXEP1 Value */ 412 #define MXC_S_DMA_CFG_REQSEL_USBRXEP1 (MXC_V_DMA_CFG_REQSEL_USBRXEP1 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP1 Setting */ 413 #define MXC_V_DMA_CFG_REQSEL_USBRXEP2 ((uint32_t)0x12UL) /**< CFG_REQSEL_USBRXEP2 Value */ 414 #define MXC_S_DMA_CFG_REQSEL_USBRXEP2 (MXC_V_DMA_CFG_REQSEL_USBRXEP2 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP2 Setting */ 415 #define MXC_V_DMA_CFG_REQSEL_USBRXEP3 ((uint32_t)0x13UL) /**< CFG_REQSEL_USBRXEP3 Value */ 416 #define MXC_S_DMA_CFG_REQSEL_USBRXEP3 (MXC_V_DMA_CFG_REQSEL_USBRXEP3 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP3 Setting */ 417 #define MXC_V_DMA_CFG_REQSEL_USBRXEP4 ((uint32_t)0x14UL) /**< CFG_REQSEL_USBRXEP4 Value */ 418 #define MXC_S_DMA_CFG_REQSEL_USBRXEP4 (MXC_V_DMA_CFG_REQSEL_USBRXEP4 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP4 Setting */ 419 #define MXC_V_DMA_CFG_REQSEL_USBRXEP5 ((uint32_t)0x15UL) /**< CFG_REQSEL_USBRXEP5 Value */ 420 #define MXC_S_DMA_CFG_REQSEL_USBRXEP5 (MXC_V_DMA_CFG_REQSEL_USBRXEP5 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP5 Setting */ 421 #define MXC_V_DMA_CFG_REQSEL_USBRXEP6 ((uint32_t)0x16UL) /**< CFG_REQSEL_USBRXEP6 Value */ 422 #define MXC_S_DMA_CFG_REQSEL_USBRXEP6 (MXC_V_DMA_CFG_REQSEL_USBRXEP6 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP6 Setting */ 423 #define MXC_V_DMA_CFG_REQSEL_USBRXEP7 ((uint32_t)0x17UL) /**< CFG_REQSEL_USBRXEP7 Value */ 424 #define MXC_S_DMA_CFG_REQSEL_USBRXEP7 (MXC_V_DMA_CFG_REQSEL_USBRXEP7 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP7 Setting */ 425 #define MXC_V_DMA_CFG_REQSEL_USBRXEP8 ((uint32_t)0x18UL) /**< CFG_REQSEL_USBRXEP8 Value */ 426 #define MXC_S_DMA_CFG_REQSEL_USBRXEP8 (MXC_V_DMA_CFG_REQSEL_USBRXEP8 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP8 Setting */ 427 #define MXC_V_DMA_CFG_REQSEL_USBRXEP9 ((uint32_t)0x19UL) /**< CFG_REQSEL_USBRXEP9 Value */ 428 #define MXC_S_DMA_CFG_REQSEL_USBRXEP9 (MXC_V_DMA_CFG_REQSEL_USBRXEP9 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP9 Setting */ 429 #define MXC_V_DMA_CFG_REQSEL_USBRXEP10 ((uint32_t)0x1AUL) /**< CFG_REQSEL_USBRXEP10 Value */ 430 #define MXC_S_DMA_CFG_REQSEL_USBRXEP10 (MXC_V_DMA_CFG_REQSEL_USBRXEP10 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP10 Setting */ 431 #define MXC_V_DMA_CFG_REQSEL_USBRXEP11 ((uint32_t)0x1BUL) /**< CFG_REQSEL_USBRXEP11 Value */ 432 #define MXC_S_DMA_CFG_REQSEL_USBRXEP11 (MXC_V_DMA_CFG_REQSEL_USBRXEP11 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP11 Setting */ 433 #define MXC_V_DMA_CFG_REQSEL_SPI0TX ((uint32_t)0x21UL) /**< CFG_REQSEL_SPI0TX Value */ 434 #define MXC_S_DMA_CFG_REQSEL_SPI0TX (MXC_V_DMA_CFG_REQSEL_SPI0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0TX Setting */ 435 #define MXC_V_DMA_CFG_REQSEL_SPI1TX ((uint32_t)0x22UL) /**< CFG_REQSEL_SPI1TX Value */ 436 #define MXC_S_DMA_CFG_REQSEL_SPI1TX (MXC_V_DMA_CFG_REQSEL_SPI1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1TX Setting */ 437 #define MXC_V_DMA_CFG_REQSEL_SPI2TX ((uint32_t)0x23UL) /**< CFG_REQSEL_SPI2TX Value */ 438 #define MXC_S_DMA_CFG_REQSEL_SPI2TX (MXC_V_DMA_CFG_REQSEL_SPI2TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI2TX Setting */ 439 #define MXC_V_DMA_CFG_REQSEL_UART0TX ((uint32_t)0x24UL) /**< CFG_REQSEL_UART0TX Value */ 440 #define MXC_S_DMA_CFG_REQSEL_UART0TX (MXC_V_DMA_CFG_REQSEL_UART0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0TX Setting */ 441 #define MXC_V_DMA_CFG_REQSEL_UART1TX ((uint32_t)0x25UL) /**< CFG_REQSEL_UART1TX Value */ 442 #define MXC_S_DMA_CFG_REQSEL_UART1TX (MXC_V_DMA_CFG_REQSEL_UART1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1TX Setting */ 443 #define MXC_V_DMA_CFG_REQSEL_I2C0TX ((uint32_t)0x27UL) /**< CFG_REQSEL_I2C0TX Value */ 444 #define MXC_S_DMA_CFG_REQSEL_I2C0TX (MXC_V_DMA_CFG_REQSEL_I2C0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0TX Setting */ 445 #define MXC_V_DMA_CFG_REQSEL_I2C1TX ((uint32_t)0x28UL) /**< CFG_REQSEL_I2C1TX Value */ 446 #define MXC_S_DMA_CFG_REQSEL_I2C1TX (MXC_V_DMA_CFG_REQSEL_I2C1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1TX Setting */ 447 #define MXC_V_DMA_CFG_REQSEL_UART2TX ((uint32_t)0x2EUL) /**< CFG_REQSEL_UART2TX Value */ 448 #define MXC_S_DMA_CFG_REQSEL_UART2TX (MXC_V_DMA_CFG_REQSEL_UART2TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART2TX Setting */ 449 #define MXC_V_DMA_CFG_REQSEL_SPI3TX ((uint32_t)0x2FUL) /**< CFG_REQSEL_SPI3TX Value */ 450 #define MXC_S_DMA_CFG_REQSEL_SPI3TX (MXC_V_DMA_CFG_REQSEL_SPI3TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI3TX Setting */ 451 #define MXC_V_DMA_CFG_REQSEL_SPIMSSTX ((uint32_t)0x30UL) /**< CFG_REQSEL_SPIMSSTX Value */ 452 #define MXC_S_DMA_CFG_REQSEL_SPIMSSTX (MXC_V_DMA_CFG_REQSEL_SPIMSSTX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPIMSSTX Setting */ 453 #define MXC_V_DMA_CFG_REQSEL_USBTXEP1 ((uint32_t)0x31UL) /**< CFG_REQSEL_USBTXEP1 Value */ 454 #define MXC_S_DMA_CFG_REQSEL_USBTXEP1 (MXC_V_DMA_CFG_REQSEL_USBTXEP1 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBTXEP1 Setting */ 455 #define MXC_V_DMA_CFG_REQSEL_USBTXEP2 ((uint32_t)0x32UL) /**< CFG_REQSEL_USBTXEP2 Value */ 456 #define MXC_S_DMA_CFG_REQSEL_USBTXEP2 (MXC_V_DMA_CFG_REQSEL_USBTXEP2 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBTXEP2 Setting */ 457 #define MXC_V_DMA_CFG_REQSEL_USBTXEP3 ((uint32_t)0x33UL) /**< CFG_REQSEL_USBTXEP3 Value */ 458 #define MXC_S_DMA_CFG_REQSEL_USBTXEP3 (MXC_V_DMA_CFG_REQSEL_USBTXEP3 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBTXEP3 Setting */ 459 #define MXC_V_DMA_CFG_REQSEL_USBTXEP4 ((uint32_t)0x34UL) /**< CFG_REQSEL_USBTXEP4 Value */ 460 #define MXC_S_DMA_CFG_REQSEL_USBTXEP4 (MXC_V_DMA_CFG_REQSEL_USBTXEP4 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBTXEP4 Setting */ 461 #define MXC_V_DMA_CFG_REQSEL_USBTXEP5 ((uint32_t)0x35UL) /**< CFG_REQSEL_USBTXEP5 Value */ 462 #define MXC_S_DMA_CFG_REQSEL_USBTXEP5 (MXC_V_DMA_CFG_REQSEL_USBTXEP5 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBTXEP5 Setting */ 463 #define MXC_V_DMA_CFG_REQSEL_USBTXEP6 ((uint32_t)0x36UL) /**< CFG_REQSEL_USBTXEP6 Value */ 464 #define MXC_S_DMA_CFG_REQSEL_USBTXEP6 (MXC_V_DMA_CFG_REQSEL_USBTXEP6 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBTXEP6 Setting */ 465 #define MXC_V_DMA_CFG_REQSEL_USBTXEP7 ((uint32_t)0x37UL) /**< CFG_REQSEL_USBTXEP7 Value */ 466 #define MXC_S_DMA_CFG_REQSEL_USBTXEP7 (MXC_V_DMA_CFG_REQSEL_USBTXEP7 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBTXEP7 Setting */ 467 #define MXC_V_DMA_CFG_REQSEL_USBTXEP8 ((uint32_t)0x38UL) /**< CFG_REQSEL_USBTXEP8 Value */ 468 #define MXC_S_DMA_CFG_REQSEL_USBTXEP8 (MXC_V_DMA_CFG_REQSEL_USBTXEP8 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBTXEP8 Setting */ 469 #define MXC_V_DMA_CFG_REQSEL_USBTXEP9 ((uint32_t)0x39UL) /**< CFG_REQSEL_USBTXEP9 Value */ 470 #define MXC_S_DMA_CFG_REQSEL_USBTXEP9 (MXC_V_DMA_CFG_REQSEL_USBTXEP9 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBTXEP9 Setting */ 471 #define MXC_V_DMA_CFG_REQSEL_USBTXEP10 ((uint32_t)0x3AUL) /**< CFG_REQSEL_USBTXEP10 Value */ 472 #define MXC_S_DMA_CFG_REQSEL_USBTXEP10 (MXC_V_DMA_CFG_REQSEL_USBTXEP10 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBTXEP10 Setting */ 473 #define MXC_V_DMA_CFG_REQSEL_USBTXEP11 ((uint32_t)0x3BUL) /**< CFG_REQSEL_USBTXEP11 Value */ 474 #define MXC_S_DMA_CFG_REQSEL_USBTXEP11 (MXC_V_DMA_CFG_REQSEL_USBTXEP11 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBTXEP11 Setting */ 475 476 #define MXC_F_DMA_CFG_REQWAIT_POS 10 /**< CFG_REQWAIT Position */ 477 #define MXC_F_DMA_CFG_REQWAIT ((uint32_t)(0x1UL << MXC_F_DMA_CFG_REQWAIT_POS)) /**< CFG_REQWAIT Mask */ 478 #define MXC_V_DMA_CFG_REQWAIT_NORMAL ((uint32_t)0x0UL) /**< CFG_REQWAIT_NORMAL Value */ 479 #define MXC_S_DMA_CFG_REQWAIT_NORMAL (MXC_V_DMA_CFG_REQWAIT_NORMAL << MXC_F_DMA_CFG_REQWAIT_POS) /**< CFG_REQWAIT_NORMAL Setting */ 480 #define MXC_V_DMA_CFG_REQWAIT_DELAY ((uint32_t)0x1UL) /**< CFG_REQWAIT_DELAY Value */ 481 #define MXC_S_DMA_CFG_REQWAIT_DELAY (MXC_V_DMA_CFG_REQWAIT_DELAY << MXC_F_DMA_CFG_REQWAIT_POS) /**< CFG_REQWAIT_DELAY Setting */ 482 483 #define MXC_F_DMA_CFG_TOSEL_POS 11 /**< CFG_TOSEL Position */ 484 #define MXC_F_DMA_CFG_TOSEL ((uint32_t)(0x7UL << MXC_F_DMA_CFG_TOSEL_POS)) /**< CFG_TOSEL Mask */ 485 #define MXC_V_DMA_CFG_TOSEL_TO4 ((uint32_t)0x0UL) /**< CFG_TOSEL_TO4 Value */ 486 #define MXC_S_DMA_CFG_TOSEL_TO4 (MXC_V_DMA_CFG_TOSEL_TO4 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO4 Setting */ 487 #define MXC_V_DMA_CFG_TOSEL_TO8 ((uint32_t)0x1UL) /**< CFG_TOSEL_TO8 Value */ 488 #define MXC_S_DMA_CFG_TOSEL_TO8 (MXC_V_DMA_CFG_TOSEL_TO8 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO8 Setting */ 489 #define MXC_V_DMA_CFG_TOSEL_TO16 ((uint32_t)0x2UL) /**< CFG_TOSEL_TO16 Value */ 490 #define MXC_S_DMA_CFG_TOSEL_TO16 (MXC_V_DMA_CFG_TOSEL_TO16 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO16 Setting */ 491 #define MXC_V_DMA_CFG_TOSEL_TO32 ((uint32_t)0x3UL) /**< CFG_TOSEL_TO32 Value */ 492 #define MXC_S_DMA_CFG_TOSEL_TO32 (MXC_V_DMA_CFG_TOSEL_TO32 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO32 Setting */ 493 #define MXC_V_DMA_CFG_TOSEL_TO64 ((uint32_t)0x4UL) /**< CFG_TOSEL_TO64 Value */ 494 #define MXC_S_DMA_CFG_TOSEL_TO64 (MXC_V_DMA_CFG_TOSEL_TO64 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO64 Setting */ 495 #define MXC_V_DMA_CFG_TOSEL_TO128 ((uint32_t)0x5UL) /**< CFG_TOSEL_TO128 Value */ 496 #define MXC_S_DMA_CFG_TOSEL_TO128 (MXC_V_DMA_CFG_TOSEL_TO128 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO128 Setting */ 497 #define MXC_V_DMA_CFG_TOSEL_TO256 ((uint32_t)0x6UL) /**< CFG_TOSEL_TO256 Value */ 498 #define MXC_S_DMA_CFG_TOSEL_TO256 (MXC_V_DMA_CFG_TOSEL_TO256 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO256 Setting */ 499 #define MXC_V_DMA_CFG_TOSEL_TO512 ((uint32_t)0x7UL) /**< CFG_TOSEL_TO512 Value */ 500 #define MXC_S_DMA_CFG_TOSEL_TO512 (MXC_V_DMA_CFG_TOSEL_TO512 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO512 Setting */ 501 502 #define MXC_F_DMA_CFG_PSSEL_POS 14 /**< CFG_PSSEL Position */ 503 #define MXC_F_DMA_CFG_PSSEL ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PSSEL_POS)) /**< CFG_PSSEL Mask */ 504 #define MXC_V_DMA_CFG_PSSEL_DIS ((uint32_t)0x0UL) /**< CFG_PSSEL_DIS Value */ 505 #define MXC_S_DMA_CFG_PSSEL_DIS (MXC_V_DMA_CFG_PSSEL_DIS << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIS Setting */ 506 #define MXC_V_DMA_CFG_PSSEL_DIV256 ((uint32_t)0x1UL) /**< CFG_PSSEL_DIV256 Value */ 507 #define MXC_S_DMA_CFG_PSSEL_DIV256 (MXC_V_DMA_CFG_PSSEL_DIV256 << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV256 Setting */ 508 #define MXC_V_DMA_CFG_PSSEL_DIV64K ((uint32_t)0x2UL) /**< CFG_PSSEL_DIV64K Value */ 509 #define MXC_S_DMA_CFG_PSSEL_DIV64K (MXC_V_DMA_CFG_PSSEL_DIV64K << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV64K Setting */ 510 #define MXC_V_DMA_CFG_PSSEL_DIV16M ((uint32_t)0x3UL) /**< CFG_PSSEL_DIV16M Value */ 511 #define MXC_S_DMA_CFG_PSSEL_DIV16M (MXC_V_DMA_CFG_PSSEL_DIV16M << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV16M Setting */ 512 513 #define MXC_F_DMA_CFG_SRCWD_POS 16 /**< CFG_SRCWD Position */ 514 #define MXC_F_DMA_CFG_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_SRCWD_POS)) /**< CFG_SRCWD Mask */ 515 #define MXC_V_DMA_CFG_SRCWD_BYTE ((uint32_t)0x0UL) /**< CFG_SRCWD_BYTE Value */ 516 #define MXC_S_DMA_CFG_SRCWD_BYTE (MXC_V_DMA_CFG_SRCWD_BYTE << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_BYTE Setting */ 517 #define MXC_V_DMA_CFG_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_SRCWD_HALFWORD Value */ 518 #define MXC_S_DMA_CFG_SRCWD_HALFWORD (MXC_V_DMA_CFG_SRCWD_HALFWORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_HALFWORD Setting */ 519 #define MXC_V_DMA_CFG_SRCWD_WORD ((uint32_t)0x2UL) /**< CFG_SRCWD_WORD Value */ 520 #define MXC_S_DMA_CFG_SRCWD_WORD (MXC_V_DMA_CFG_SRCWD_WORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_WORD Setting */ 521 522 #define MXC_F_DMA_CFG_SRINC_POS 18 /**< CFG_SRINC Position */ 523 #define MXC_F_DMA_CFG_SRINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_SRINC_POS)) /**< CFG_SRINC Mask */ 524 #define MXC_V_DMA_CFG_SRINC_DIS ((uint32_t)0x0UL) /**< CFG_SRINC_DIS Value */ 525 #define MXC_S_DMA_CFG_SRINC_DIS (MXC_V_DMA_CFG_SRINC_DIS << MXC_F_DMA_CFG_SRINC_POS) /**< CFG_SRINC_DIS Setting */ 526 #define MXC_V_DMA_CFG_SRINC_EN ((uint32_t)0x1UL) /**< CFG_SRINC_EN Value */ 527 #define MXC_S_DMA_CFG_SRINC_EN (MXC_V_DMA_CFG_SRINC_EN << MXC_F_DMA_CFG_SRINC_POS) /**< CFG_SRINC_EN Setting */ 528 529 #define MXC_F_DMA_CFG_DSTWD_POS 20 /**< CFG_DSTWD Position */ 530 #define MXC_F_DMA_CFG_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_DSTWD_POS)) /**< CFG_DSTWD Mask */ 531 #define MXC_V_DMA_CFG_DSTWD_BYTE ((uint32_t)0x0UL) /**< CFG_DSTWD_BYTE Value */ 532 #define MXC_S_DMA_CFG_DSTWD_BYTE (MXC_V_DMA_CFG_DSTWD_BYTE << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_BYTE Setting */ 533 #define MXC_V_DMA_CFG_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_DSTWD_HALFWORD Value */ 534 #define MXC_S_DMA_CFG_DSTWD_HALFWORD (MXC_V_DMA_CFG_DSTWD_HALFWORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_HALFWORD Setting */ 535 #define MXC_V_DMA_CFG_DSTWD_WORD ((uint32_t)0x2UL) /**< CFG_DSTWD_WORD Value */ 536 #define MXC_S_DMA_CFG_DSTWD_WORD (MXC_V_DMA_CFG_DSTWD_WORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_WORD Setting */ 537 538 #define MXC_F_DMA_CFG_DSTINC_POS 22 /**< CFG_DSTINC Position */ 539 #define MXC_F_DMA_CFG_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_DSTINC_POS)) /**< CFG_DSTINC Mask */ 540 #define MXC_V_DMA_CFG_DSTINC_DIS ((uint32_t)0x0UL) /**< CFG_DSTINC_DIS Value */ 541 #define MXC_S_DMA_CFG_DSTINC_DIS (MXC_V_DMA_CFG_DSTINC_DIS << MXC_F_DMA_CFG_DSTINC_POS) /**< CFG_DSTINC_DIS Setting */ 542 #define MXC_V_DMA_CFG_DSTINC_EN ((uint32_t)0x1UL) /**< CFG_DSTINC_EN Value */ 543 #define MXC_S_DMA_CFG_DSTINC_EN (MXC_V_DMA_CFG_DSTINC_EN << MXC_F_DMA_CFG_DSTINC_POS) /**< CFG_DSTINC_EN Setting */ 544 545 #define MXC_F_DMA_CFG_BRST_POS 24 /**< CFG_BRST Position */ 546 #define MXC_F_DMA_CFG_BRST ((uint32_t)(0x1FUL << MXC_F_DMA_CFG_BRST_POS)) /**< CFG_BRST Mask */ 547 548 #define MXC_F_DMA_CFG_CHDIEN_POS 30 /**< CFG_CHDIEN Position */ 549 #define MXC_F_DMA_CFG_CHDIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHDIEN_POS)) /**< CFG_CHDIEN Mask */ 550 #define MXC_V_DMA_CFG_CHDIEN_DIS ((uint32_t)0x0UL) /**< CFG_CHDIEN_DIS Value */ 551 #define MXC_S_DMA_CFG_CHDIEN_DIS (MXC_V_DMA_CFG_CHDIEN_DIS << MXC_F_DMA_CFG_CHDIEN_POS) /**< CFG_CHDIEN_DIS Setting */ 552 #define MXC_V_DMA_CFG_CHDIEN_EN ((uint32_t)0x1UL) /**< CFG_CHDIEN_EN Value */ 553 #define MXC_S_DMA_CFG_CHDIEN_EN (MXC_V_DMA_CFG_CHDIEN_EN << MXC_F_DMA_CFG_CHDIEN_POS) /**< CFG_CHDIEN_EN Setting */ 554 555 #define MXC_F_DMA_CFG_CTZIEN_POS 31 /**< CFG_CTZIEN Position */ 556 #define MXC_F_DMA_CFG_CTZIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CTZIEN_POS)) /**< CFG_CTZIEN Mask */ 557 #define MXC_V_DMA_CFG_CTZIEN_DIS ((uint32_t)0x0UL) /**< CFG_CTZIEN_DIS Value */ 558 #define MXC_S_DMA_CFG_CTZIEN_DIS (MXC_V_DMA_CFG_CTZIEN_DIS << MXC_F_DMA_CFG_CTZIEN_POS) /**< CFG_CTZIEN_DIS Setting */ 559 #define MXC_V_DMA_CFG_CTZIEN_EN ((uint32_t)0x1UL) /**< CFG_CTZIEN_EN Value */ 560 #define MXC_S_DMA_CFG_CTZIEN_EN (MXC_V_DMA_CFG_CTZIEN_EN << MXC_F_DMA_CFG_CTZIEN_POS) /**< CFG_CTZIEN_EN Setting */ 561 562 /**@} end of group DMA_CFG_Register */ 563 564 /** 565 * @ingroup dma_registers 566 * @defgroup DMA_ST DMA_ST 567 * @brief DMA Channel Status Register. 568 * @{ 569 */ 570 #define MXC_F_DMA_ST_CH_ST_POS 0 /**< ST_CH_ST Position */ 571 #define MXC_F_DMA_ST_CH_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_CH_ST_POS)) /**< ST_CH_ST Mask */ 572 #define MXC_V_DMA_ST_CH_ST_DISABLED ((uint32_t)0x0UL) /**< ST_CH_ST_DISABLED Value */ 573 #define MXC_S_DMA_ST_CH_ST_DISABLED (MXC_V_DMA_ST_CH_ST_DISABLED << MXC_F_DMA_ST_CH_ST_POS) /**< ST_CH_ST_DISABLED Setting */ 574 #define MXC_V_DMA_ST_CH_ST_ENABLED ((uint32_t)0x1UL) /**< ST_CH_ST_ENABLED Value */ 575 #define MXC_S_DMA_ST_CH_ST_ENABLED (MXC_V_DMA_ST_CH_ST_ENABLED << MXC_F_DMA_ST_CH_ST_POS) /**< ST_CH_ST_ENABLED Setting */ 576 577 #define MXC_F_DMA_ST_IPEND_POS 1 /**< ST_IPEND Position */ 578 #define MXC_F_DMA_ST_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_ST_IPEND_POS)) /**< ST_IPEND Mask */ 579 #define MXC_V_DMA_ST_IPEND_INACTIVE ((uint32_t)0x0UL) /**< ST_IPEND_INACTIVE Value */ 580 #define MXC_S_DMA_ST_IPEND_INACTIVE (MXC_V_DMA_ST_IPEND_INACTIVE << MXC_F_DMA_ST_IPEND_POS) /**< ST_IPEND_INACTIVE Setting */ 581 #define MXC_V_DMA_ST_IPEND_PENDING ((uint32_t)0x1UL) /**< ST_IPEND_PENDING Value */ 582 #define MXC_S_DMA_ST_IPEND_PENDING (MXC_V_DMA_ST_IPEND_PENDING << MXC_F_DMA_ST_IPEND_POS) /**< ST_IPEND_PENDING Setting */ 583 584 #define MXC_F_DMA_ST_CTZ_ST_POS 2 /**< ST_CTZ_ST Position */ 585 #define MXC_F_DMA_ST_CTZ_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_CTZ_ST_POS)) /**< ST_CTZ_ST Mask */ 586 #define MXC_V_DMA_ST_CTZ_ST_NOEVENT ((uint32_t)0x0UL) /**< ST_CTZ_ST_NOEVENT Value */ 587 #define MXC_S_DMA_ST_CTZ_ST_NOEVENT (MXC_V_DMA_ST_CTZ_ST_NOEVENT << MXC_F_DMA_ST_CTZ_ST_POS) /**< ST_CTZ_ST_NOEVENT Setting */ 588 #define MXC_V_DMA_ST_CTZ_ST_CTZ_OCCUR ((uint32_t)0x1UL) /**< ST_CTZ_ST_CTZ_OCCUR Value */ 589 #define MXC_S_DMA_ST_CTZ_ST_CTZ_OCCUR (MXC_V_DMA_ST_CTZ_ST_CTZ_OCCUR << MXC_F_DMA_ST_CTZ_ST_POS) /**< ST_CTZ_ST_CTZ_OCCUR Setting */ 590 #define MXC_V_DMA_ST_CTZ_ST_CLEAR ((uint32_t)0x1UL) /**< ST_CTZ_ST_CLEAR Value */ 591 #define MXC_S_DMA_ST_CTZ_ST_CLEAR (MXC_V_DMA_ST_CTZ_ST_CLEAR << MXC_F_DMA_ST_CTZ_ST_POS) /**< ST_CTZ_ST_CLEAR Setting */ 592 593 #define MXC_F_DMA_ST_RLD_ST_POS 3 /**< ST_RLD_ST Position */ 594 #define MXC_F_DMA_ST_RLD_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_RLD_ST_POS)) /**< ST_RLD_ST Mask */ 595 #define MXC_V_DMA_ST_RLD_ST_NOEVENT ((uint32_t)0x0UL) /**< ST_RLD_ST_NOEVENT Value */ 596 #define MXC_S_DMA_ST_RLD_ST_NOEVENT (MXC_V_DMA_ST_RLD_ST_NOEVENT << MXC_F_DMA_ST_RLD_ST_POS) /**< ST_RLD_ST_NOEVENT Setting */ 597 #define MXC_V_DMA_ST_RLD_ST_RELOADED ((uint32_t)0x1UL) /**< ST_RLD_ST_RELOADED Value */ 598 #define MXC_S_DMA_ST_RLD_ST_RELOADED (MXC_V_DMA_ST_RLD_ST_RELOADED << MXC_F_DMA_ST_RLD_ST_POS) /**< ST_RLD_ST_RELOADED Setting */ 599 #define MXC_V_DMA_ST_RLD_ST_CLEAR ((uint32_t)0x1UL) /**< ST_RLD_ST_CLEAR Value */ 600 #define MXC_S_DMA_ST_RLD_ST_CLEAR (MXC_V_DMA_ST_RLD_ST_CLEAR << MXC_F_DMA_ST_RLD_ST_POS) /**< ST_RLD_ST_CLEAR Setting */ 601 602 #define MXC_F_DMA_ST_BUS_ERR_POS 4 /**< ST_BUS_ERR Position */ 603 #define MXC_F_DMA_ST_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_ST_BUS_ERR_POS)) /**< ST_BUS_ERR Mask */ 604 #define MXC_V_DMA_ST_BUS_ERR_NOEVENT ((uint32_t)0x0UL) /**< ST_BUS_ERR_NOEVENT Value */ 605 #define MXC_S_DMA_ST_BUS_ERR_NOEVENT (MXC_V_DMA_ST_BUS_ERR_NOEVENT << MXC_F_DMA_ST_BUS_ERR_POS) /**< ST_BUS_ERR_NOEVENT Setting */ 606 #define MXC_V_DMA_ST_BUS_ERR_BUS_ERR ((uint32_t)0x1UL) /**< ST_BUS_ERR_BUS_ERR Value */ 607 #define MXC_S_DMA_ST_BUS_ERR_BUS_ERR (MXC_V_DMA_ST_BUS_ERR_BUS_ERR << MXC_F_DMA_ST_BUS_ERR_POS) /**< ST_BUS_ERR_BUS_ERR Setting */ 608 #define MXC_V_DMA_ST_BUS_ERR_CLEAR ((uint32_t)0x1UL) /**< ST_BUS_ERR_CLEAR Value */ 609 #define MXC_S_DMA_ST_BUS_ERR_CLEAR (MXC_V_DMA_ST_BUS_ERR_CLEAR << MXC_F_DMA_ST_BUS_ERR_POS) /**< ST_BUS_ERR_CLEAR Setting */ 610 611 #define MXC_F_DMA_ST_TO_ST_POS 6 /**< ST_TO_ST Position */ 612 #define MXC_F_DMA_ST_TO_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_TO_ST_POS)) /**< ST_TO_ST Mask */ 613 #define MXC_V_DMA_ST_TO_ST_NOEVENT ((uint32_t)0x0UL) /**< ST_TO_ST_NOEVENT Value */ 614 #define MXC_S_DMA_ST_TO_ST_NOEVENT (MXC_V_DMA_ST_TO_ST_NOEVENT << MXC_F_DMA_ST_TO_ST_POS) /**< ST_TO_ST_NOEVENT Setting */ 615 #define MXC_V_DMA_ST_TO_ST_EXPIRED ((uint32_t)0x1UL) /**< ST_TO_ST_EXPIRED Value */ 616 #define MXC_S_DMA_ST_TO_ST_EXPIRED (MXC_V_DMA_ST_TO_ST_EXPIRED << MXC_F_DMA_ST_TO_ST_POS) /**< ST_TO_ST_EXPIRED Setting */ 617 #define MXC_V_DMA_ST_TO_ST_CLEAR ((uint32_t)0x1UL) /**< ST_TO_ST_CLEAR Value */ 618 #define MXC_S_DMA_ST_TO_ST_CLEAR (MXC_V_DMA_ST_TO_ST_CLEAR << MXC_F_DMA_ST_TO_ST_POS) /**< ST_TO_ST_CLEAR Setting */ 619 620 /**@} end of group DMA_ST_Register */ 621 622 /** 623 * @ingroup dma_registers 624 * @defgroup DMA_SRC DMA_SRC 625 * @brief Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 626 * 4, depending on the data width of each AHB cycle. For peripheral transfers, some 627 * or all of the actual address bits are fixed. If SRCINC=0, this register remains 628 * constant. In the case where a count-to-zero condition occurs while RLDEN=1, the 629 * register is reloaded with the contents of DMA_SRC_RLD. 630 * @{ 631 */ 632 #define MXC_F_DMA_SRC_ADDR_POS 0 /**< SRC_ADDR Position */ 633 #define MXC_F_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS)) /**< SRC_ADDR Mask */ 634 635 /**@} end of group DMA_SRC_Register */ 636 637 /** 638 * @ingroup dma_registers 639 * @defgroup DMA_DST DMA_DST 640 * @brief Destination Device Address. For peripheral transfers, some or all of the actual 641 * address bits are fixed. If DSTINC=1, this register is incremented on every AHB 642 * write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the 643 * data width of each AHB cycle. In the case where a count-to-zero condition occurs 644 * while RLDEN=1, the register is reloaded with DMA_DST_RLD. 645 * @{ 646 */ 647 #define MXC_F_DMA_DST_ADDR_POS 0 /**< DST_ADDR Position */ 648 #define MXC_F_DMA_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_ADDR_POS)) /**< DST_ADDR Mask */ 649 650 /**@} end of group DMA_DST_Register */ 651 652 /** 653 * @ingroup dma_registers 654 * @defgroup DMA_CNT DMA_CNT 655 * @brief DMA Counter. The user loads this register with the number of bytes to transfer. 656 * This counter decreases on every AHB cycle into the DMA FIFO. The decrement will 657 * be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter 658 * reaches 0, a count-to-zero condition is triggered. 659 * @{ 660 */ 661 #define MXC_F_DMA_CNT_CNT_POS 0 /**< CNT_CNT Position */ 662 #define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */ 663 664 /**@} end of group DMA_CNT_Register */ 665 666 /** 667 * @ingroup dma_registers 668 * @defgroup DMA_SRC_RLD DMA_SRC_RLD 669 * @brief Source Address Reload Value. The value of this register is loaded into DMA0_SRC 670 * upon a count-to-zero condition. 671 * @{ 672 */ 673 #define MXC_F_DMA_SRC_RLD_SRC_RLD_POS 0 /**< SRC_RLD_SRC_RLD Position */ 674 #define MXC_F_DMA_SRC_RLD_SRC_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRC_RLD_SRC_RLD_POS)) /**< SRC_RLD_SRC_RLD Mask */ 675 676 /**@} end of group DMA_SRC_RLD_Register */ 677 678 /** 679 * @ingroup dma_registers 680 * @defgroup DMA_DST_RLD DMA_DST_RLD 681 * @brief Destination Address Reload Value. The value of this register is loaded into 682 * DMA0_DST upon a count-to-zero condition. 683 * @{ 684 */ 685 #define MXC_F_DMA_DST_RLD_DST_RLD_POS 0 /**< DST_RLD_DST_RLD Position */ 686 #define MXC_F_DMA_DST_RLD_DST_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DST_RLD_DST_RLD_POS)) /**< DST_RLD_DST_RLD Mask */ 687 688 /**@} end of group DMA_DST_RLD_Register */ 689 690 /** 691 * @ingroup dma_registers 692 * @defgroup DMA_CNT_RLD DMA_CNT_RLD 693 * @brief DMA Channel Count Reload Register. 694 * @{ 695 */ 696 #define MXC_F_DMA_CNT_RLD_CNT_RLD_POS 0 /**< CNT_RLD_CNT_RLD Position */ 697 #define MXC_F_DMA_CNT_RLD_CNT_RLD ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_RLD_CNT_RLD_POS)) /**< CNT_RLD_CNT_RLD Mask */ 698 699 #define MXC_F_DMA_CNT_RLD_RLDEN_POS 31 /**< CNT_RLD_RLDEN Position */ 700 #define MXC_F_DMA_CNT_RLD_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CNT_RLD_RLDEN_POS)) /**< CNT_RLD_RLDEN Mask */ 701 #define MXC_V_DMA_CNT_RLD_RLDEN_DIS ((uint32_t)0x0UL) /**< CNT_RLD_RLDEN_DIS Value */ 702 #define MXC_S_DMA_CNT_RLD_RLDEN_DIS (MXC_V_DMA_CNT_RLD_RLDEN_DIS << MXC_F_DMA_CNT_RLD_RLDEN_POS) /**< CNT_RLD_RLDEN_DIS Setting */ 703 #define MXC_V_DMA_CNT_RLD_RLDEN_EN ((uint32_t)0x1UL) /**< CNT_RLD_RLDEN_EN Value */ 704 #define MXC_S_DMA_CNT_RLD_RLDEN_EN (MXC_V_DMA_CNT_RLD_RLDEN_EN << MXC_F_DMA_CNT_RLD_RLDEN_POS) /**< CNT_RLD_RLDEN_EN Setting */ 705 706 /**@} end of group DMA_CNT_RLD_Register */ 707 708 #ifdef __cplusplus 709 } 710 #endif 711 712 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_DMA_REGS_H_ 713
