1 /** 2 * @file clcd_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the CLCD Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup clcd_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_CLCD_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_CLCD_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup clcd 67 * @defgroup clcd_registers CLCD_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the CLCD Peripheral Module. 69 * @details Color LCD Controller 70 */ 71 72 /** 73 * @ingroup clcd_registers 74 * Structure type to access the CLCD Registers. 75 */ 76 typedef struct { 77 __IO uint32_t clk_ctrl; /**< <tt>\b 0x000:</tt> CLCD CLK_CTRL Register */ 78 __IO uint32_t vtim_0; /**< <tt>\b 0x004:</tt> CLCD VTIM_0 Register */ 79 __IO uint32_t vtim_1; /**< <tt>\b 0x008:</tt> CLCD VTIM_1 Register */ 80 __IO uint32_t htim; /**< <tt>\b 0x00C:</tt> CLCD HTIM Register */ 81 __IO uint32_t ctrl; /**< <tt>\b 0x010:</tt> CLCD CTRL Register */ 82 __R uint32_t rsv_0x14; 83 __IO uint32_t frbuf; /**< <tt>\b 0x18:</tt> CLCD FRBUF Register */ 84 __R uint32_t rsv_0x1c; 85 __IO uint32_t int_en; /**< <tt>\b 0x020:</tt> CLCD INT_EN Register */ 86 __IO uint32_t int_stat; /**< <tt>\b 0x024:</tt> CLCD INT_STAT Register */ 87 __R uint32_t rsv_0x28_0x3ff[246]; 88 __IO uint32_t palette_ram[256]; /**< <tt>\b 0x400:</tt> CLCD PALETTE_RAM Register */ 89 } mxc_clcd_regs_t; 90 91 /* Register offsets for module CLCD */ 92 /** 93 * @ingroup clcd_registers 94 * @defgroup CLCD_Register_Offsets Register Offsets 95 * @brief CLCD Peripheral Register Offsets from the CLCD Base Peripheral Address. 96 * @{ 97 */ 98 #define MXC_R_CLCD_CLK_CTRL ((uint32_t)0x00000000UL) /**< Offset from CLCD Base Address: <tt> 0x0000</tt> */ 99 #define MXC_R_CLCD_VTIM_0 ((uint32_t)0x00000004UL) /**< Offset from CLCD Base Address: <tt> 0x0004</tt> */ 100 #define MXC_R_CLCD_VTIM_1 ((uint32_t)0x00000008UL) /**< Offset from CLCD Base Address: <tt> 0x0008</tt> */ 101 #define MXC_R_CLCD_HTIM ((uint32_t)0x0000000CUL) /**< Offset from CLCD Base Address: <tt> 0x000C</tt> */ 102 #define MXC_R_CLCD_CTRL ((uint32_t)0x00000010UL) /**< Offset from CLCD Base Address: <tt> 0x0010</tt> */ 103 #define MXC_R_CLCD_FRBUF ((uint32_t)0x00000018UL) /**< Offset from CLCD Base Address: <tt> 0x0018</tt> */ 104 #define MXC_R_CLCD_INT_EN ((uint32_t)0x00000020UL) /**< Offset from CLCD Base Address: <tt> 0x0020</tt> */ 105 #define MXC_R_CLCD_INT_STAT ((uint32_t)0x00000024UL) /**< Offset from CLCD Base Address: <tt> 0x0024</tt> */ 106 #define MXC_R_CLCD_PALETTE_RAM ((uint32_t)0x00000400UL) /**< Offset from CLCD Base Address: <tt> 0x0400</tt> */ 107 /**@} end of group clcd_registers */ 108 109 /** 110 * @ingroup clcd_registers 111 * @defgroup CLCD_CLK_CTRL CLCD_CLK_CTRL 112 * @brief LCD Clock Control Register 113 * @{ 114 */ 115 #define MXC_F_CLCD_CLK_CTRL_LCD_CLKDIV_POS 0 /**< CLK_CTRL_LCD_CLKDIV Position */ 116 #define MXC_F_CLCD_CLK_CTRL_LCD_CLKDIV ((uint32_t)(0xFFUL << MXC_F_CLCD_CLK_CTRL_LCD_CLKDIV_POS)) /**< CLK_CTRL_LCD_CLKDIV Mask */ 117 118 #define MXC_F_CLCD_CLK_CTRL_STN_AC_BIAS_POS 8 /**< CLK_CTRL_STN_AC_BIAS Position */ 119 #define MXC_F_CLCD_CLK_CTRL_STN_AC_BIAS ((uint32_t)(0xFFUL << MXC_F_CLCD_CLK_CTRL_STN_AC_BIAS_POS)) /**< CLK_CTRL_STN_AC_BIAS Mask */ 120 121 #define MXC_F_CLCD_CLK_CTRL_VDEN_POL_POS 16 /**< CLK_CTRL_VDEN_POL Position */ 122 #define MXC_F_CLCD_CLK_CTRL_VDEN_POL ((uint32_t)(0x1UL << MXC_F_CLCD_CLK_CTRL_VDEN_POL_POS)) /**< CLK_CTRL_VDEN_POL Mask */ 123 #define MXC_V_CLCD_CLK_CTRL_VDEN_POL_ACTIVELO ((uint32_t)0x0UL) /**< CLK_CTRL_VDEN_POL_ACTIVELO Value */ 124 #define MXC_S_CLCD_CLK_CTRL_VDEN_POL_ACTIVELO (MXC_V_CLCD_CLK_CTRL_VDEN_POL_ACTIVELO << MXC_F_CLCD_CLK_CTRL_VDEN_POL_POS) /**< CLK_CTRL_VDEN_POL_ACTIVELO Setting */ 125 #define MXC_V_CLCD_CLK_CTRL_VDEN_POL_ACTIVEHI ((uint32_t)0x1UL) /**< CLK_CTRL_VDEN_POL_ACTIVEHI Value */ 126 #define MXC_S_CLCD_CLK_CTRL_VDEN_POL_ACTIVEHI (MXC_V_CLCD_CLK_CTRL_VDEN_POL_ACTIVEHI << MXC_F_CLCD_CLK_CTRL_VDEN_POL_POS) /**< CLK_CTRL_VDEN_POL_ACTIVEHI Setting */ 127 128 #define MXC_F_CLCD_CLK_CTRL_VSYNC_POL_POS 17 /**< CLK_CTRL_VSYNC_POL Position */ 129 #define MXC_F_CLCD_CLK_CTRL_VSYNC_POL ((uint32_t)(0x1UL << MXC_F_CLCD_CLK_CTRL_VSYNC_POL_POS)) /**< CLK_CTRL_VSYNC_POL Mask */ 130 #define MXC_V_CLCD_CLK_CTRL_VSYNC_POL_ACTIVELO ((uint32_t)0x0UL) /**< CLK_CTRL_VSYNC_POL_ACTIVELO Value */ 131 #define MXC_S_CLCD_CLK_CTRL_VSYNC_POL_ACTIVELO (MXC_V_CLCD_CLK_CTRL_VSYNC_POL_ACTIVELO << MXC_F_CLCD_CLK_CTRL_VSYNC_POL_POS) /**< CLK_CTRL_VSYNC_POL_ACTIVELO Setting */ 132 #define MXC_V_CLCD_CLK_CTRL_VSYNC_POL_ACTIVEHI ((uint32_t)0x1UL) /**< CLK_CTRL_VSYNC_POL_ACTIVEHI Value */ 133 #define MXC_S_CLCD_CLK_CTRL_VSYNC_POL_ACTIVEHI (MXC_V_CLCD_CLK_CTRL_VSYNC_POL_ACTIVEHI << MXC_F_CLCD_CLK_CTRL_VSYNC_POL_POS) /**< CLK_CTRL_VSYNC_POL_ACTIVEHI Setting */ 134 135 #define MXC_F_CLCD_CLK_CTRL_HSYNC_POL_POS 18 /**< CLK_CTRL_HSYNC_POL Position */ 136 #define MXC_F_CLCD_CLK_CTRL_HSYNC_POL ((uint32_t)(0x1UL << MXC_F_CLCD_CLK_CTRL_HSYNC_POL_POS)) /**< CLK_CTRL_HSYNC_POL Mask */ 137 #define MXC_V_CLCD_CLK_CTRL_HSYNC_POL_ACTIVELO ((uint32_t)0x0UL) /**< CLK_CTRL_HSYNC_POL_ACTIVELO Value */ 138 #define MXC_S_CLCD_CLK_CTRL_HSYNC_POL_ACTIVELO (MXC_V_CLCD_CLK_CTRL_HSYNC_POL_ACTIVELO << MXC_F_CLCD_CLK_CTRL_HSYNC_POL_POS) /**< CLK_CTRL_HSYNC_POL_ACTIVELO Setting */ 139 #define MXC_V_CLCD_CLK_CTRL_HSYNC_POL_ACTIVEHI ((uint32_t)0x1UL) /**< CLK_CTRL_HSYNC_POL_ACTIVEHI Value */ 140 #define MXC_S_CLCD_CLK_CTRL_HSYNC_POL_ACTIVEHI (MXC_V_CLCD_CLK_CTRL_HSYNC_POL_ACTIVEHI << MXC_F_CLCD_CLK_CTRL_HSYNC_POL_POS) /**< CLK_CTRL_HSYNC_POL_ACTIVEHI Setting */ 141 142 #define MXC_F_CLCD_CLK_CTRL_CLK_EDGE_SEL_POS 19 /**< CLK_CTRL_CLK_EDGE_SEL Position */ 143 #define MXC_F_CLCD_CLK_CTRL_CLK_EDGE_SEL ((uint32_t)(0x1UL << MXC_F_CLCD_CLK_CTRL_CLK_EDGE_SEL_POS)) /**< CLK_CTRL_CLK_EDGE_SEL Mask */ 144 #define MXC_V_CLCD_CLK_CTRL_CLK_EDGE_SEL_RISING ((uint32_t)0x0UL) /**< CLK_CTRL_CLK_EDGE_SEL_RISING Value */ 145 #define MXC_S_CLCD_CLK_CTRL_CLK_EDGE_SEL_RISING (MXC_V_CLCD_CLK_CTRL_CLK_EDGE_SEL_RISING << MXC_F_CLCD_CLK_CTRL_CLK_EDGE_SEL_POS) /**< CLK_CTRL_CLK_EDGE_SEL_RISING Setting */ 146 #define MXC_V_CLCD_CLK_CTRL_CLK_EDGE_SEL_FALLING ((uint32_t)0x1UL) /**< CLK_CTRL_CLK_EDGE_SEL_FALLING Value */ 147 #define MXC_S_CLCD_CLK_CTRL_CLK_EDGE_SEL_FALLING (MXC_V_CLCD_CLK_CTRL_CLK_EDGE_SEL_FALLING << MXC_F_CLCD_CLK_CTRL_CLK_EDGE_SEL_POS) /**< CLK_CTRL_CLK_EDGE_SEL_FALLING Setting */ 148 149 #define MXC_F_CLCD_CLK_CTRL_CLK_ACTIVE_POS 20 /**< CLK_CTRL_CLK_ACTIVE Position */ 150 #define MXC_F_CLCD_CLK_CTRL_CLK_ACTIVE ((uint32_t)(0x1UL << MXC_F_CLCD_CLK_CTRL_CLK_ACTIVE_POS)) /**< CLK_CTRL_CLK_ACTIVE Mask */ 151 #define MXC_V_CLCD_CLK_CTRL_CLK_ACTIVE_ALWAYS ((uint32_t)0x0UL) /**< CLK_CTRL_CLK_ACTIVE_ALWAYS Value */ 152 #define MXC_S_CLCD_CLK_CTRL_CLK_ACTIVE_ALWAYS (MXC_V_CLCD_CLK_CTRL_CLK_ACTIVE_ALWAYS << MXC_F_CLCD_CLK_CTRL_CLK_ACTIVE_POS) /**< CLK_CTRL_CLK_ACTIVE_ALWAYS Setting */ 153 #define MXC_V_CLCD_CLK_CTRL_CLK_ACTIVE_ONDATA ((uint32_t)0x1UL) /**< CLK_CTRL_CLK_ACTIVE_ONDATA Value */ 154 #define MXC_S_CLCD_CLK_CTRL_CLK_ACTIVE_ONDATA (MXC_V_CLCD_CLK_CTRL_CLK_ACTIVE_ONDATA << MXC_F_CLCD_CLK_CTRL_CLK_ACTIVE_POS) /**< CLK_CTRL_CLK_ACTIVE_ONDATA Setting */ 155 156 /**@} end of group CLCD_CLK_CTRL_Register */ 157 158 /** 159 * @ingroup clcd_registers 160 * @defgroup CLCD_VTIM_0 CLCD_VTIM_0 161 * @brief LCD Vertical Timing 0 Register 162 * @{ 163 */ 164 #define MXC_F_CLCD_VTIM_0_VLINES_POS 0 /**< VTIM_0_VLINES Position */ 165 #define MXC_F_CLCD_VTIM_0_VLINES ((uint32_t)(0xFFUL << MXC_F_CLCD_VTIM_0_VLINES_POS)) /**< VTIM_0_VLINES Mask */ 166 167 #define MXC_F_CLCD_VTIM_0_VBP_WIDTH_POS 16 /**< VTIM_0_VBP_WIDTH Position */ 168 #define MXC_F_CLCD_VTIM_0_VBP_WIDTH ((uint32_t)(0xFFUL << MXC_F_CLCD_VTIM_0_VBP_WIDTH_POS)) /**< VTIM_0_VBP_WIDTH Mask */ 169 170 /**@} end of group CLCD_VTIM_0_Register */ 171 172 /** 173 * @ingroup clcd_registers 174 * @defgroup CLCD_VTIM_1 CLCD_VTIM_1 175 * @brief LCD Vertical Timing 1 Register 176 * @{ 177 */ 178 #define MXC_F_CLCD_VTIM_1_VSYNC_WIDTH_POS 0 /**< VTIM_1_VSYNC_WIDTH Position */ 179 #define MXC_F_CLCD_VTIM_1_VSYNC_WIDTH ((uint32_t)(0xFFUL << MXC_F_CLCD_VTIM_1_VSYNC_WIDTH_POS)) /**< VTIM_1_VSYNC_WIDTH Mask */ 180 181 #define MXC_F_CLCD_VTIM_1_VFP_WIDTH_POS 16 /**< VTIM_1_VFP_WIDTH Position */ 182 #define MXC_F_CLCD_VTIM_1_VFP_WIDTH ((uint32_t)(0xFFUL << MXC_F_CLCD_VTIM_1_VFP_WIDTH_POS)) /**< VTIM_1_VFP_WIDTH Mask */ 183 184 /**@} end of group CLCD_VTIM_1_Register */ 185 186 /** 187 * @ingroup clcd_registers 188 * @defgroup CLCD_HTIM CLCD_HTIM 189 * @brief LCD Horizontal Timing Register. 190 * @{ 191 */ 192 #define MXC_F_CLCD_HTIM_HSYNC_WIDTH_POS 0 /**< HTIM_HSYNC_WIDTH Position */ 193 #define MXC_F_CLCD_HTIM_HSYNC_WIDTH ((uint32_t)(0xFFUL << MXC_F_CLCD_HTIM_HSYNC_WIDTH_POS)) /**< HTIM_HSYNC_WIDTH Mask */ 194 195 #define MXC_F_CLCD_HTIM_HFP_WIDTH_POS 8 /**< HTIM_HFP_WIDTH Position */ 196 #define MXC_F_CLCD_HTIM_HFP_WIDTH ((uint32_t)(0xFFUL << MXC_F_CLCD_HTIM_HFP_WIDTH_POS)) /**< HTIM_HFP_WIDTH Mask */ 197 198 #define MXC_F_CLCD_HTIM_HSIZE_INDEX_POS 16 /**< HTIM_HSIZE_INDEX Position */ 199 #define MXC_F_CLCD_HTIM_HSIZE_INDEX ((uint32_t)(0xFFUL << MXC_F_CLCD_HTIM_HSIZE_INDEX_POS)) /**< HTIM_HSIZE_INDEX Mask */ 200 201 #define MXC_F_CLCD_HTIM_HBP_WIDTH_POS 24 /**< HTIM_HBP_WIDTH Position */ 202 #define MXC_F_CLCD_HTIM_HBP_WIDTH ((uint32_t)(0xFFUL << MXC_F_CLCD_HTIM_HBP_WIDTH_POS)) /**< HTIM_HBP_WIDTH Mask */ 203 204 /**@} end of group CLCD_HTIM_Register */ 205 206 /** 207 * @ingroup clcd_registers 208 * @defgroup CLCD_CTRL CLCD_CTRL 209 * @brief LCD Control Register 210 * @{ 211 */ 212 #define MXC_F_CLCD_CTRL_CLCD_ENABLE_POS 0 /**< CTRL_CLCD_ENABLE Position */ 213 #define MXC_F_CLCD_CTRL_CLCD_ENABLE ((uint32_t)(0x1UL << MXC_F_CLCD_CTRL_CLCD_ENABLE_POS)) /**< CTRL_CLCD_ENABLE Mask */ 214 #define MXC_V_CLCD_CTRL_CLCD_ENABLE_DIS ((uint32_t)0x0UL) /**< CTRL_CLCD_ENABLE_DIS Value */ 215 #define MXC_S_CLCD_CTRL_CLCD_ENABLE_DIS (MXC_V_CLCD_CTRL_CLCD_ENABLE_DIS << MXC_F_CLCD_CTRL_CLCD_ENABLE_POS) /**< CTRL_CLCD_ENABLE_DIS Setting */ 216 #define MXC_V_CLCD_CTRL_CLCD_ENABLE_EN ((uint32_t)0x1UL) /**< CTRL_CLCD_ENABLE_EN Value */ 217 #define MXC_S_CLCD_CTRL_CLCD_ENABLE_EN (MXC_V_CLCD_CTRL_CLCD_ENABLE_EN << MXC_F_CLCD_CTRL_CLCD_ENABLE_POS) /**< CTRL_CLCD_ENABLE_EN Setting */ 218 219 #define MXC_F_CLCD_CTRL_VCI_SEL_POS 1 /**< CTRL_VCI_SEL Position */ 220 #define MXC_F_CLCD_CTRL_VCI_SEL ((uint32_t)(0x3UL << MXC_F_CLCD_CTRL_VCI_SEL_POS)) /**< CTRL_VCI_SEL Mask */ 221 #define MXC_V_CLCD_CTRL_VCI_SEL_ON_VSYNC ((uint32_t)0x0UL) /**< CTRL_VCI_SEL_ON_VSYNC Value */ 222 #define MXC_S_CLCD_CTRL_VCI_SEL_ON_VSYNC (MXC_V_CLCD_CTRL_VCI_SEL_ON_VSYNC << MXC_F_CLCD_CTRL_VCI_SEL_POS) /**< CTRL_VCI_SEL_ON_VSYNC Setting */ 223 #define MXC_V_CLCD_CTRL_VCI_SEL_ON_VBP ((uint32_t)0x1UL) /**< CTRL_VCI_SEL_ON_VBP Value */ 224 #define MXC_S_CLCD_CTRL_VCI_SEL_ON_VBP (MXC_V_CLCD_CTRL_VCI_SEL_ON_VBP << MXC_F_CLCD_CTRL_VCI_SEL_POS) /**< CTRL_VCI_SEL_ON_VBP Setting */ 225 #define MXC_V_CLCD_CTRL_VCI_SEL_ON_VDEN ((uint32_t)0x2UL) /**< CTRL_VCI_SEL_ON_VDEN Value */ 226 #define MXC_S_CLCD_CTRL_VCI_SEL_ON_VDEN (MXC_V_CLCD_CTRL_VCI_SEL_ON_VDEN << MXC_F_CLCD_CTRL_VCI_SEL_POS) /**< CTRL_VCI_SEL_ON_VDEN Setting */ 227 #define MXC_V_CLCD_CTRL_VCI_SEL_ON_VFP ((uint32_t)0x3UL) /**< CTRL_VCI_SEL_ON_VFP Value */ 228 #define MXC_S_CLCD_CTRL_VCI_SEL_ON_VFP (MXC_V_CLCD_CTRL_VCI_SEL_ON_VFP << MXC_F_CLCD_CTRL_VCI_SEL_POS) /**< CTRL_VCI_SEL_ON_VFP Setting */ 229 230 #define MXC_F_CLCD_CTRL_DISPTYPE_POS 4 /**< CTRL_DISPTYPE Position */ 231 #define MXC_F_CLCD_CTRL_DISPTYPE ((uint32_t)(0xFUL << MXC_F_CLCD_CTRL_DISPTYPE_POS)) /**< CTRL_DISPTYPE Mask */ 232 #define MXC_V_CLCD_CTRL_DISPTYPE_8BITCOLORSTN ((uint32_t)0x4UL) /**< CTRL_DISPTYPE_8BITCOLORSTN Value */ 233 #define MXC_S_CLCD_CTRL_DISPTYPE_8BITCOLORSTN (MXC_V_CLCD_CTRL_DISPTYPE_8BITCOLORSTN << MXC_F_CLCD_CTRL_DISPTYPE_POS) /**< CTRL_DISPTYPE_8BITCOLORSTN Setting */ 234 #define MXC_V_CLCD_CTRL_DISPTYPE_TFT ((uint32_t)0x8UL) /**< CTRL_DISPTYPE_TFT Value */ 235 #define MXC_S_CLCD_CTRL_DISPTYPE_TFT (MXC_V_CLCD_CTRL_DISPTYPE_TFT << MXC_F_CLCD_CTRL_DISPTYPE_POS) /**< CTRL_DISPTYPE_TFT Setting */ 236 237 #define MXC_F_CLCD_CTRL_BPP_POS 8 /**< CTRL_BPP Position */ 238 #define MXC_F_CLCD_CTRL_BPP ((uint32_t)(0x7UL << MXC_F_CLCD_CTRL_BPP_POS)) /**< CTRL_BPP Mask */ 239 #define MXC_V_CLCD_CTRL_BPP_BPP1 ((uint32_t)0x0UL) /**< CTRL_BPP_BPP1 Value */ 240 #define MXC_S_CLCD_CTRL_BPP_BPP1 (MXC_V_CLCD_CTRL_BPP_BPP1 << MXC_F_CLCD_CTRL_BPP_POS) /**< CTRL_BPP_BPP1 Setting */ 241 #define MXC_V_CLCD_CTRL_BPP_BPP2 ((uint32_t)0x1UL) /**< CTRL_BPP_BPP2 Value */ 242 #define MXC_S_CLCD_CTRL_BPP_BPP2 (MXC_V_CLCD_CTRL_BPP_BPP2 << MXC_F_CLCD_CTRL_BPP_POS) /**< CTRL_BPP_BPP2 Setting */ 243 #define MXC_V_CLCD_CTRL_BPP_BPP4 ((uint32_t)0x2UL) /**< CTRL_BPP_BPP4 Value */ 244 #define MXC_S_CLCD_CTRL_BPP_BPP4 (MXC_V_CLCD_CTRL_BPP_BPP4 << MXC_F_CLCD_CTRL_BPP_POS) /**< CTRL_BPP_BPP4 Setting */ 245 #define MXC_V_CLCD_CTRL_BPP_BPP8 ((uint32_t)0x3UL) /**< CTRL_BPP_BPP8 Value */ 246 #define MXC_S_CLCD_CTRL_BPP_BPP8 (MXC_V_CLCD_CTRL_BPP_BPP8 << MXC_F_CLCD_CTRL_BPP_POS) /**< CTRL_BPP_BPP8 Setting */ 247 #define MXC_V_CLCD_CTRL_BPP_BPP16 ((uint32_t)0x4UL) /**< CTRL_BPP_BPP16 Value */ 248 #define MXC_S_CLCD_CTRL_BPP_BPP16 (MXC_V_CLCD_CTRL_BPP_BPP16 << MXC_F_CLCD_CTRL_BPP_POS) /**< CTRL_BPP_BPP16 Setting */ 249 #define MXC_V_CLCD_CTRL_BPP_BPP24 ((uint32_t)0x5UL) /**< CTRL_BPP_BPP24 Value */ 250 #define MXC_S_CLCD_CTRL_BPP_BPP24 (MXC_V_CLCD_CTRL_BPP_BPP24 << MXC_F_CLCD_CTRL_BPP_POS) /**< CTRL_BPP_BPP24 Setting */ 251 252 #define MXC_F_CLCD_CTRL_MODE565_POS 11 /**< CTRL_MODE565 Position */ 253 #define MXC_F_CLCD_CTRL_MODE565 ((uint32_t)(0x1UL << MXC_F_CLCD_CTRL_MODE565_POS)) /**< CTRL_MODE565 Mask */ 254 #define MXC_V_CLCD_CTRL_MODE565_BGR556 ((uint32_t)0x0UL) /**< CTRL_MODE565_BGR556 Value */ 255 #define MXC_S_CLCD_CTRL_MODE565_BGR556 (MXC_V_CLCD_CTRL_MODE565_BGR556 << MXC_F_CLCD_CTRL_MODE565_POS) /**< CTRL_MODE565_BGR556 Setting */ 256 #define MXC_V_CLCD_CTRL_MODE565_RGB565 ((uint32_t)0x1UL) /**< CTRL_MODE565_RGB565 Value */ 257 #define MXC_S_CLCD_CTRL_MODE565_RGB565 (MXC_V_CLCD_CTRL_MODE565_RGB565 << MXC_F_CLCD_CTRL_MODE565_POS) /**< CTRL_MODE565_RGB565 Setting */ 258 259 #define MXC_F_CLCD_CTRL_ENDIAN_POS 12 /**< CTRL_ENDIAN Position */ 260 #define MXC_F_CLCD_CTRL_ENDIAN ((uint32_t)(0x3UL << MXC_F_CLCD_CTRL_ENDIAN_POS)) /**< CTRL_ENDIAN Mask */ 261 #define MXC_V_CLCD_CTRL_ENDIAN_LBLP ((uint32_t)0x0UL) /**< CTRL_ENDIAN_LBLP Value */ 262 #define MXC_S_CLCD_CTRL_ENDIAN_LBLP (MXC_V_CLCD_CTRL_ENDIAN_LBLP << MXC_F_CLCD_CTRL_ENDIAN_POS) /**< CTRL_ENDIAN_LBLP Setting */ 263 #define MXC_V_CLCD_CTRL_ENDIAN_BBBP ((uint32_t)0x1UL) /**< CTRL_ENDIAN_BBBP Value */ 264 #define MXC_S_CLCD_CTRL_ENDIAN_BBBP (MXC_V_CLCD_CTRL_ENDIAN_BBBP << MXC_F_CLCD_CTRL_ENDIAN_POS) /**< CTRL_ENDIAN_BBBP Setting */ 265 #define MXC_V_CLCD_CTRL_ENDIAN_LBBP ((uint32_t)0x2UL) /**< CTRL_ENDIAN_LBBP Value */ 266 #define MXC_S_CLCD_CTRL_ENDIAN_LBBP (MXC_V_CLCD_CTRL_ENDIAN_LBBP << MXC_F_CLCD_CTRL_ENDIAN_POS) /**< CTRL_ENDIAN_LBBP Setting */ 267 #define MXC_V_CLCD_CTRL_ENDIAN_RFU ((uint32_t)0x3UL) /**< CTRL_ENDIAN_RFU Value */ 268 #define MXC_S_CLCD_CTRL_ENDIAN_RFU (MXC_V_CLCD_CTRL_ENDIAN_RFU << MXC_F_CLCD_CTRL_ENDIAN_POS) /**< CTRL_ENDIAN_RFU Setting */ 269 270 #define MXC_F_CLCD_CTRL_COMPACT_24B_POS 15 /**< CTRL_COMPACT_24B Position */ 271 #define MXC_F_CLCD_CTRL_COMPACT_24B ((uint32_t)(0x1UL << MXC_F_CLCD_CTRL_COMPACT_24B_POS)) /**< CTRL_COMPACT_24B Mask */ 272 #define MXC_V_CLCD_CTRL_COMPACT_24B_1_PFR ((uint32_t)0x0UL) /**< CTRL_COMPACT_24B_1_PFR Value */ 273 #define MXC_S_CLCD_CTRL_COMPACT_24B_1_PFR (MXC_V_CLCD_CTRL_COMPACT_24B_1_PFR << MXC_F_CLCD_CTRL_COMPACT_24B_POS) /**< CTRL_COMPACT_24B_1_PFR Setting */ 274 #define MXC_V_CLCD_CTRL_COMPACT_24B_1ANDA3RD_PFR ((uint32_t)0x1UL) /**< CTRL_COMPACT_24B_1ANDA3RD_PFR Value */ 275 #define MXC_S_CLCD_CTRL_COMPACT_24B_1ANDA3RD_PFR (MXC_V_CLCD_CTRL_COMPACT_24B_1ANDA3RD_PFR << MXC_F_CLCD_CTRL_COMPACT_24B_POS) /**< CTRL_COMPACT_24B_1ANDA3RD_PFR Setting */ 276 277 #define MXC_F_CLCD_CTRL_BURST_SIZE_POS 19 /**< CTRL_BURST_SIZE Position */ 278 #define MXC_F_CLCD_CTRL_BURST_SIZE ((uint32_t)(0x3UL << MXC_F_CLCD_CTRL_BURST_SIZE_POS)) /**< CTRL_BURST_SIZE Mask */ 279 #define MXC_V_CLCD_CTRL_BURST_SIZE_4WORDS ((uint32_t)0x0UL) /**< CTRL_BURST_SIZE_4WORDS Value */ 280 #define MXC_S_CLCD_CTRL_BURST_SIZE_4WORDS (MXC_V_CLCD_CTRL_BURST_SIZE_4WORDS << MXC_F_CLCD_CTRL_BURST_SIZE_POS) /**< CTRL_BURST_SIZE_4WORDS Setting */ 281 #define MXC_V_CLCD_CTRL_BURST_SIZE_8WORDS ((uint32_t)0x1UL) /**< CTRL_BURST_SIZE_8WORDS Value */ 282 #define MXC_S_CLCD_CTRL_BURST_SIZE_8WORDS (MXC_V_CLCD_CTRL_BURST_SIZE_8WORDS << MXC_F_CLCD_CTRL_BURST_SIZE_POS) /**< CTRL_BURST_SIZE_8WORDS Setting */ 283 #define MXC_V_CLCD_CTRL_BURST_SIZE_16WORDS ((uint32_t)0x2UL) /**< CTRL_BURST_SIZE_16WORDS Value */ 284 #define MXC_S_CLCD_CTRL_BURST_SIZE_16WORDS (MXC_V_CLCD_CTRL_BURST_SIZE_16WORDS << MXC_F_CLCD_CTRL_BURST_SIZE_POS) /**< CTRL_BURST_SIZE_16WORDS Setting */ 285 286 #define MXC_F_CLCD_CTRL_LEND_POL_POS 21 /**< CTRL_LEND_POL Position */ 287 #define MXC_F_CLCD_CTRL_LEND_POL ((uint32_t)(0x1UL << MXC_F_CLCD_CTRL_LEND_POL_POS)) /**< CTRL_LEND_POL Mask */ 288 #define MXC_V_CLCD_CTRL_LEND_POL_ACTIVELO ((uint32_t)0x0UL) /**< CTRL_LEND_POL_ACTIVELO Value */ 289 #define MXC_S_CLCD_CTRL_LEND_POL_ACTIVELO (MXC_V_CLCD_CTRL_LEND_POL_ACTIVELO << MXC_F_CLCD_CTRL_LEND_POL_POS) /**< CTRL_LEND_POL_ACTIVELO Setting */ 290 #define MXC_V_CLCD_CTRL_LEND_POL_ACTIVEHI ((uint32_t)0x1UL) /**< CTRL_LEND_POL_ACTIVEHI Value */ 291 #define MXC_S_CLCD_CTRL_LEND_POL_ACTIVEHI (MXC_V_CLCD_CTRL_LEND_POL_ACTIVEHI << MXC_F_CLCD_CTRL_LEND_POL_POS) /**< CTRL_LEND_POL_ACTIVEHI Setting */ 292 293 #define MXC_F_CLCD_CTRL_PWR_ENABLE_POS 22 /**< CTRL_PWR_ENABLE Position */ 294 #define MXC_F_CLCD_CTRL_PWR_ENABLE ((uint32_t)(0x1UL << MXC_F_CLCD_CTRL_PWR_ENABLE_POS)) /**< CTRL_PWR_ENABLE Mask */ 295 #define MXC_V_CLCD_CTRL_PWR_ENABLE_LO ((uint32_t)0x0UL) /**< CTRL_PWR_ENABLE_LO Value */ 296 #define MXC_S_CLCD_CTRL_PWR_ENABLE_LO (MXC_V_CLCD_CTRL_PWR_ENABLE_LO << MXC_F_CLCD_CTRL_PWR_ENABLE_POS) /**< CTRL_PWR_ENABLE_LO Setting */ 297 #define MXC_V_CLCD_CTRL_PWR_ENABLE_HI ((uint32_t)0x1UL) /**< CTRL_PWR_ENABLE_HI Value */ 298 #define MXC_S_CLCD_CTRL_PWR_ENABLE_HI (MXC_V_CLCD_CTRL_PWR_ENABLE_HI << MXC_F_CLCD_CTRL_PWR_ENABLE_POS) /**< CTRL_PWR_ENABLE_HI Setting */ 299 300 /**@} end of group CLCD_CTRL_Register */ 301 302 /** 303 * @ingroup clcd_registers 304 * @defgroup CLCD_FRBUF CLCD_FRBUF 305 * @brief Frame buffer. 306 * @{ 307 */ 308 #define MXC_F_CLCD_FRBUF_FRAME_ADDR_POS 0 /**< FRBUF_FRAME_ADDR Position */ 309 #define MXC_F_CLCD_FRBUF_FRAME_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLCD_FRBUF_FRAME_ADDR_POS)) /**< FRBUF_FRAME_ADDR Mask */ 310 311 /**@} end of group CLCD_FRBUF_Register */ 312 313 /** 314 * @ingroup clcd_registers 315 * @defgroup CLCD_INT_EN CLCD_INT_EN 316 * @brief LCD Interrupt Enable Register. 317 * @{ 318 */ 319 #define MXC_F_CLCD_INT_EN_UNDERFLOW_IE_POS 0 /**< INT_EN_UNDERFLOW_IE Position */ 320 #define MXC_F_CLCD_INT_EN_UNDERFLOW_IE ((uint32_t)(0x1UL << MXC_F_CLCD_INT_EN_UNDERFLOW_IE_POS)) /**< INT_EN_UNDERFLOW_IE Mask */ 321 #define MXC_V_CLCD_INT_EN_UNDERFLOW_IE_DIS ((uint32_t)0x0UL) /**< INT_EN_UNDERFLOW_IE_DIS Value */ 322 #define MXC_S_CLCD_INT_EN_UNDERFLOW_IE_DIS (MXC_V_CLCD_INT_EN_UNDERFLOW_IE_DIS << MXC_F_CLCD_INT_EN_UNDERFLOW_IE_POS) /**< INT_EN_UNDERFLOW_IE_DIS Setting */ 323 #define MXC_V_CLCD_INT_EN_UNDERFLOW_IE_EN ((uint32_t)0x1UL) /**< INT_EN_UNDERFLOW_IE_EN Value */ 324 #define MXC_S_CLCD_INT_EN_UNDERFLOW_IE_EN (MXC_V_CLCD_INT_EN_UNDERFLOW_IE_EN << MXC_F_CLCD_INT_EN_UNDERFLOW_IE_POS) /**< INT_EN_UNDERFLOW_IE_EN Setting */ 325 326 #define MXC_F_CLCD_INT_EN_ADDR_RDY_IE_POS 1 /**< INT_EN_ADDR_RDY_IE Position */ 327 #define MXC_F_CLCD_INT_EN_ADDR_RDY_IE ((uint32_t)(0x1UL << MXC_F_CLCD_INT_EN_ADDR_RDY_IE_POS)) /**< INT_EN_ADDR_RDY_IE Mask */ 328 #define MXC_V_CLCD_INT_EN_ADDR_RDY_IE_DIS ((uint32_t)0x0UL) /**< INT_EN_ADDR_RDY_IE_DIS Value */ 329 #define MXC_S_CLCD_INT_EN_ADDR_RDY_IE_DIS (MXC_V_CLCD_INT_EN_ADDR_RDY_IE_DIS << MXC_F_CLCD_INT_EN_ADDR_RDY_IE_POS) /**< INT_EN_ADDR_RDY_IE_DIS Setting */ 330 #define MXC_V_CLCD_INT_EN_ADDR_RDY_IE_EN ((uint32_t)0x1UL) /**< INT_EN_ADDR_RDY_IE_EN Value */ 331 #define MXC_S_CLCD_INT_EN_ADDR_RDY_IE_EN (MXC_V_CLCD_INT_EN_ADDR_RDY_IE_EN << MXC_F_CLCD_INT_EN_ADDR_RDY_IE_POS) /**< INT_EN_ADDR_RDY_IE_EN Setting */ 332 333 #define MXC_F_CLCD_INT_EN_VCI_IE_POS 2 /**< INT_EN_VCI_IE Position */ 334 #define MXC_F_CLCD_INT_EN_VCI_IE ((uint32_t)(0x1UL << MXC_F_CLCD_INT_EN_VCI_IE_POS)) /**< INT_EN_VCI_IE Mask */ 335 #define MXC_V_CLCD_INT_EN_VCI_IE_DIS ((uint32_t)0x0UL) /**< INT_EN_VCI_IE_DIS Value */ 336 #define MXC_S_CLCD_INT_EN_VCI_IE_DIS (MXC_V_CLCD_INT_EN_VCI_IE_DIS << MXC_F_CLCD_INT_EN_VCI_IE_POS) /**< INT_EN_VCI_IE_DIS Setting */ 337 #define MXC_V_CLCD_INT_EN_VCI_IE_EN ((uint32_t)0x1UL) /**< INT_EN_VCI_IE_EN Value */ 338 #define MXC_S_CLCD_INT_EN_VCI_IE_EN (MXC_V_CLCD_INT_EN_VCI_IE_EN << MXC_F_CLCD_INT_EN_VCI_IE_POS) /**< INT_EN_VCI_IE_EN Setting */ 339 340 #define MXC_F_CLCD_INT_EN_BUS_ERROR_IE_POS 3 /**< INT_EN_BUS_ERROR_IE Position */ 341 #define MXC_F_CLCD_INT_EN_BUS_ERROR_IE ((uint32_t)(0x1UL << MXC_F_CLCD_INT_EN_BUS_ERROR_IE_POS)) /**< INT_EN_BUS_ERROR_IE Mask */ 342 #define MXC_V_CLCD_INT_EN_BUS_ERROR_IE_DIS ((uint32_t)0x0UL) /**< INT_EN_BUS_ERROR_IE_DIS Value */ 343 #define MXC_S_CLCD_INT_EN_BUS_ERROR_IE_DIS (MXC_V_CLCD_INT_EN_BUS_ERROR_IE_DIS << MXC_F_CLCD_INT_EN_BUS_ERROR_IE_POS) /**< INT_EN_BUS_ERROR_IE_DIS Setting */ 344 #define MXC_V_CLCD_INT_EN_BUS_ERROR_IE_EN ((uint32_t)0x1UL) /**< INT_EN_BUS_ERROR_IE_EN Value */ 345 #define MXC_S_CLCD_INT_EN_BUS_ERROR_IE_EN (MXC_V_CLCD_INT_EN_BUS_ERROR_IE_EN << MXC_F_CLCD_INT_EN_BUS_ERROR_IE_POS) /**< INT_EN_BUS_ERROR_IE_EN Setting */ 346 347 /**@} end of group CLCD_INT_EN_Register */ 348 349 /** 350 * @ingroup clcd_registers 351 * @defgroup CLCD_INT_STAT CLCD_INT_STAT 352 * @brief LCD Status Register. 353 * @{ 354 */ 355 #define MXC_F_CLCD_INT_STAT_UNDERFLOW_POS 0 /**< INT_STAT_UNDERFLOW Position */ 356 #define MXC_F_CLCD_INT_STAT_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_CLCD_INT_STAT_UNDERFLOW_POS)) /**< INT_STAT_UNDERFLOW Mask */ 357 #define MXC_V_CLCD_INT_STAT_UNDERFLOW_INACTIVE ((uint32_t)0x0UL) /**< INT_STAT_UNDERFLOW_INACTIVE Value */ 358 #define MXC_S_CLCD_INT_STAT_UNDERFLOW_INACTIVE (MXC_V_CLCD_INT_STAT_UNDERFLOW_INACTIVE << MXC_F_CLCD_INT_STAT_UNDERFLOW_POS) /**< INT_STAT_UNDERFLOW_INACTIVE Setting */ 359 #define MXC_V_CLCD_INT_STAT_UNDERFLOW_PEND ((uint32_t)0x1UL) /**< INT_STAT_UNDERFLOW_PEND Value */ 360 #define MXC_S_CLCD_INT_STAT_UNDERFLOW_PEND (MXC_V_CLCD_INT_STAT_UNDERFLOW_PEND << MXC_F_CLCD_INT_STAT_UNDERFLOW_POS) /**< INT_STAT_UNDERFLOW_PEND Setting */ 361 #define MXC_V_CLCD_INT_STAT_UNDERFLOW_CLEAR ((uint32_t)0x1UL) /**< INT_STAT_UNDERFLOW_CLEAR Value */ 362 #define MXC_S_CLCD_INT_STAT_UNDERFLOW_CLEAR (MXC_V_CLCD_INT_STAT_UNDERFLOW_CLEAR << MXC_F_CLCD_INT_STAT_UNDERFLOW_POS) /**< INT_STAT_UNDERFLOW_CLEAR Setting */ 363 364 #define MXC_F_CLCD_INT_STAT_ADDR_RDY_POS 1 /**< INT_STAT_ADDR_RDY Position */ 365 #define MXC_F_CLCD_INT_STAT_ADDR_RDY ((uint32_t)(0x1UL << MXC_F_CLCD_INT_STAT_ADDR_RDY_POS)) /**< INT_STAT_ADDR_RDY Mask */ 366 #define MXC_V_CLCD_INT_STAT_ADDR_RDY_INACTIVE ((uint32_t)0x0UL) /**< INT_STAT_ADDR_RDY_INACTIVE Value */ 367 #define MXC_S_CLCD_INT_STAT_ADDR_RDY_INACTIVE (MXC_V_CLCD_INT_STAT_ADDR_RDY_INACTIVE << MXC_F_CLCD_INT_STAT_ADDR_RDY_POS) /**< INT_STAT_ADDR_RDY_INACTIVE Setting */ 368 #define MXC_V_CLCD_INT_STAT_ADDR_RDY_PEND ((uint32_t)0x1UL) /**< INT_STAT_ADDR_RDY_PEND Value */ 369 #define MXC_S_CLCD_INT_STAT_ADDR_RDY_PEND (MXC_V_CLCD_INT_STAT_ADDR_RDY_PEND << MXC_F_CLCD_INT_STAT_ADDR_RDY_POS) /**< INT_STAT_ADDR_RDY_PEND Setting */ 370 #define MXC_V_CLCD_INT_STAT_ADDR_RDY_CLEAR ((uint32_t)0x1UL) /**< INT_STAT_ADDR_RDY_CLEAR Value */ 371 #define MXC_S_CLCD_INT_STAT_ADDR_RDY_CLEAR (MXC_V_CLCD_INT_STAT_ADDR_RDY_CLEAR << MXC_F_CLCD_INT_STAT_ADDR_RDY_POS) /**< INT_STAT_ADDR_RDY_CLEAR Setting */ 372 373 #define MXC_F_CLCD_INT_STAT_VCI_POS 2 /**< INT_STAT_VCI Position */ 374 #define MXC_F_CLCD_INT_STAT_VCI ((uint32_t)(0x1UL << MXC_F_CLCD_INT_STAT_VCI_POS)) /**< INT_STAT_VCI Mask */ 375 #define MXC_V_CLCD_INT_STAT_VCI_INACTIVE ((uint32_t)0x0UL) /**< INT_STAT_VCI_INACTIVE Value */ 376 #define MXC_S_CLCD_INT_STAT_VCI_INACTIVE (MXC_V_CLCD_INT_STAT_VCI_INACTIVE << MXC_F_CLCD_INT_STAT_VCI_POS) /**< INT_STAT_VCI_INACTIVE Setting */ 377 #define MXC_V_CLCD_INT_STAT_VCI_PEND ((uint32_t)0x1UL) /**< INT_STAT_VCI_PEND Value */ 378 #define MXC_S_CLCD_INT_STAT_VCI_PEND (MXC_V_CLCD_INT_STAT_VCI_PEND << MXC_F_CLCD_INT_STAT_VCI_POS) /**< INT_STAT_VCI_PEND Setting */ 379 #define MXC_V_CLCD_INT_STAT_VCI_CLEAR ((uint32_t)0x1UL) /**< INT_STAT_VCI_CLEAR Value */ 380 #define MXC_S_CLCD_INT_STAT_VCI_CLEAR (MXC_V_CLCD_INT_STAT_VCI_CLEAR << MXC_F_CLCD_INT_STAT_VCI_POS) /**< INT_STAT_VCI_CLEAR Setting */ 381 382 #define MXC_F_CLCD_INT_STAT_BUS_ERROR_POS 3 /**< INT_STAT_BUS_ERROR Position */ 383 #define MXC_F_CLCD_INT_STAT_BUS_ERROR ((uint32_t)(0x1UL << MXC_F_CLCD_INT_STAT_BUS_ERROR_POS)) /**< INT_STAT_BUS_ERROR Mask */ 384 #define MXC_V_CLCD_INT_STAT_BUS_ERROR_INACTIVE ((uint32_t)0x0UL) /**< INT_STAT_BUS_ERROR_INACTIVE Value */ 385 #define MXC_S_CLCD_INT_STAT_BUS_ERROR_INACTIVE (MXC_V_CLCD_INT_STAT_BUS_ERROR_INACTIVE << MXC_F_CLCD_INT_STAT_BUS_ERROR_POS) /**< INT_STAT_BUS_ERROR_INACTIVE Setting */ 386 #define MXC_V_CLCD_INT_STAT_BUS_ERROR_PEND ((uint32_t)0x1UL) /**< INT_STAT_BUS_ERROR_PEND Value */ 387 #define MXC_S_CLCD_INT_STAT_BUS_ERROR_PEND (MXC_V_CLCD_INT_STAT_BUS_ERROR_PEND << MXC_F_CLCD_INT_STAT_BUS_ERROR_POS) /**< INT_STAT_BUS_ERROR_PEND Setting */ 388 #define MXC_V_CLCD_INT_STAT_BUS_ERROR_CLEAR ((uint32_t)0x1UL) /**< INT_STAT_BUS_ERROR_CLEAR Value */ 389 #define MXC_S_CLCD_INT_STAT_BUS_ERROR_CLEAR (MXC_V_CLCD_INT_STAT_BUS_ERROR_CLEAR << MXC_F_CLCD_INT_STAT_BUS_ERROR_POS) /**< INT_STAT_BUS_ERROR_CLEAR Setting */ 390 391 #define MXC_F_CLCD_INT_STAT_CLCD_IDLE_POS 8 /**< INT_STAT_CLCD_IDLE Position */ 392 #define MXC_F_CLCD_INT_STAT_CLCD_IDLE ((uint32_t)(0x1UL << MXC_F_CLCD_INT_STAT_CLCD_IDLE_POS)) /**< INT_STAT_CLCD_IDLE Mask */ 393 #define MXC_V_CLCD_INT_STAT_CLCD_IDLE_IDLE ((uint32_t)0x0UL) /**< INT_STAT_CLCD_IDLE_IDLE Value */ 394 #define MXC_S_CLCD_INT_STAT_CLCD_IDLE_IDLE (MXC_V_CLCD_INT_STAT_CLCD_IDLE_IDLE << MXC_F_CLCD_INT_STAT_CLCD_IDLE_POS) /**< INT_STAT_CLCD_IDLE_IDLE Setting */ 395 #define MXC_V_CLCD_INT_STAT_CLCD_IDLE_BUSY ((uint32_t)0x1UL) /**< INT_STAT_CLCD_IDLE_BUSY Value */ 396 #define MXC_S_CLCD_INT_STAT_CLCD_IDLE_BUSY (MXC_V_CLCD_INT_STAT_CLCD_IDLE_BUSY << MXC_F_CLCD_INT_STAT_CLCD_IDLE_POS) /**< INT_STAT_CLCD_IDLE_BUSY Setting */ 397 398 /**@} end of group CLCD_INT_STAT_Register */ 399 400 /** 401 * @ingroup clcd_registers 402 * @defgroup CLCD_PALETTE_RAM CLCD_PALETTE_RAM 403 * @brief Palette 404 * @{ 405 */ 406 #define MXC_F_CLCD_PALETTE_RAM_RED_POS 0 /**< PALETTE_RAM_RED Position */ 407 #define MXC_F_CLCD_PALETTE_RAM_RED ((uint32_t)(0xFFUL << MXC_F_CLCD_PALETTE_RAM_RED_POS)) /**< PALETTE_RAM_RED Mask */ 408 409 #define MXC_F_CLCD_PALETTE_RAM_GREEN_POS 8 /**< PALETTE_RAM_GREEN Position */ 410 #define MXC_F_CLCD_PALETTE_RAM_GREEN ((uint32_t)(0xFFUL << MXC_F_CLCD_PALETTE_RAM_GREEN_POS)) /**< PALETTE_RAM_GREEN Mask */ 411 412 #define MXC_F_CLCD_PALETTE_RAM_BLUE_POS 16 /**< PALETTE_RAM_BLUE Position */ 413 #define MXC_F_CLCD_PALETTE_RAM_BLUE ((uint32_t)(0xFFUL << MXC_F_CLCD_PALETTE_RAM_BLUE_POS)) /**< PALETTE_RAM_BLUE Mask */ 414 415 /**@} end of group CLCD_PALETTE_RAM_Register */ 416 417 #ifdef __cplusplus 418 } 419 #endif 420 421 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_CLCD_REGS_H_ 422
