1 /** 2 * @file trng_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the TRNG Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup trng_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_TRNG_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_TRNG_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup trng 67 * @defgroup trng_registers TRNG_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the TRNG Peripheral Module. 69 * @details Random Number Generator. 70 */ 71 72 /** 73 * @ingroup trng_registers 74 * Structure type to access the TRNG Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> TRNG CTRL Register */ 78 __IO uint32_t status; /**< <tt>\b 0x04:</tt> TRNG STATUS Register */ 79 __I uint32_t data; /**< <tt>\b 0x08:</tt> TRNG DATA Register */ 80 __R uint32_t rsv_0xc_0x37[11]; 81 __IO uint32_t data_nist; /**< <tt>\b 0x38:</tt> TRNG DATA_NIST Register */ 82 } mxc_trng_regs_t; 83 84 /* Register offsets for module TRNG */ 85 /** 86 * @ingroup trng_registers 87 * @defgroup TRNG_Register_Offsets Register Offsets 88 * @brief TRNG Peripheral Register Offsets from the TRNG Base Peripheral Address. 89 * @{ 90 */ 91 #define MXC_R_TRNG_CTRL ((uint32_t)0x00000000UL) /**< Offset from TRNG Base Address: <tt> 0x0000</tt> */ 92 #define MXC_R_TRNG_STATUS ((uint32_t)0x00000004UL) /**< Offset from TRNG Base Address: <tt> 0x0004</tt> */ 93 #define MXC_R_TRNG_DATA ((uint32_t)0x00000008UL) /**< Offset from TRNG Base Address: <tt> 0x0008</tt> */ 94 #define MXC_R_TRNG_DATA_NIST ((uint32_t)0x00000038UL) /**< Offset from TRNG Base Address: <tt> 0x0038</tt> */ 95 /**@} end of group trng_registers */ 96 97 /** 98 * @ingroup trng_registers 99 * @defgroup TRNG_CTRL TRNG_CTRL 100 * @brief TRNG Control Register. 101 * @{ 102 */ 103 #define MXC_F_TRNG_CTRL_OD_HEALTH_POS 0 /**< CTRL_OD_HEALTH Position */ 104 #define MXC_F_TRNG_CTRL_OD_HEALTH ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_OD_HEALTH_POS)) /**< CTRL_OD_HEALTH Mask */ 105 106 #define MXC_F_TRNG_CTRL_RND_IE_POS 1 /**< CTRL_RND_IE Position */ 107 #define MXC_F_TRNG_CTRL_RND_IE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_RND_IE_POS)) /**< CTRL_RND_IE Mask */ 108 109 #define MXC_F_TRNG_CTRL_HEALTH_IE_POS 2 /**< CTRL_HEALTH_IE Position */ 110 #define MXC_F_TRNG_CTRL_HEALTH_IE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_HEALTH_IE_POS)) /**< CTRL_HEALTH_IE Mask */ 111 112 #define MXC_F_TRNG_CTRL_MEU_KEYGEN_POS 3 /**< CTRL_MEU_KEYGEN Position */ 113 #define MXC_F_TRNG_CTRL_MEU_KEYGEN ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_MEU_KEYGEN_POS)) /**< CTRL_MEU_KEYGEN Mask */ 114 115 #define MXC_F_TRNG_CTRL_XIP_KEYGEN_POS 4 /**< CTRL_XIP_KEYGEN Position */ 116 #define MXC_F_TRNG_CTRL_XIP_KEYGEN ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_XIP_KEYGEN_POS)) /**< CTRL_XIP_KEYGEN Mask */ 117 118 #define MXC_F_TRNG_CTRL_OD_ROMON_POS 6 /**< CTRL_OD_ROMON Position */ 119 #define MXC_F_TRNG_CTRL_OD_ROMON ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_OD_ROMON_POS)) /**< CTRL_OD_ROMON Mask */ 120 121 #define MXC_F_TRNG_CTRL_OD_EE_POS 7 /**< CTRL_OD_EE Position */ 122 #define MXC_F_TRNG_CTRL_OD_EE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_OD_EE_POS)) /**< CTRL_OD_EE Mask */ 123 124 #define MXC_F_TRNG_CTRL_ROMON_EE_FOE_POS 8 /**< CTRL_ROMON_EE_FOE Position */ 125 #define MXC_F_TRNG_CTRL_ROMON_EE_FOE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_ROMON_EE_FOE_POS)) /**< CTRL_ROMON_EE_FOE Mask */ 126 127 #define MXC_F_TRNG_CTRL_ROMON_EE_FOD_POS 9 /**< CTRL_ROMON_EE_FOD Position */ 128 #define MXC_F_TRNG_CTRL_ROMON_EE_FOD ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_ROMON_EE_FOD_POS)) /**< CTRL_ROMON_EE_FOD Mask */ 129 130 #define MXC_F_TRNG_CTRL_EBLS_POS 10 /**< CTRL_EBLS Position */ 131 #define MXC_F_TRNG_CTRL_EBLS ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_EBLS_POS)) /**< CTRL_EBLS Mask */ 132 133 #define MXC_F_TRNG_CTRL_KEYWIPE_POS 15 /**< CTRL_KEYWIPE Position */ 134 #define MXC_F_TRNG_CTRL_KEYWIPE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_KEYWIPE_POS)) /**< CTRL_KEYWIPE Mask */ 135 136 #define MXC_F_TRNG_CTRL_GET_TERO_CNT_POS 16 /**< CTRL_GET_TERO_CNT Position */ 137 #define MXC_F_TRNG_CTRL_GET_TERO_CNT ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_GET_TERO_CNT_POS)) /**< CTRL_GET_TERO_CNT Mask */ 138 139 #define MXC_F_TRNG_CTRL_EE_DONE_IE_POS 23 /**< CTRL_EE_DONE_IE Position */ 140 #define MXC_F_TRNG_CTRL_EE_DONE_IE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_EE_DONE_IE_POS)) /**< CTRL_EE_DONE_IE Mask */ 141 142 #define MXC_F_TRNG_CTRL_ROMON_DIS_POS 24 /**< CTRL_ROMON_DIS Position */ 143 #define MXC_F_TRNG_CTRL_ROMON_DIS ((uint32_t)(0x7UL << MXC_F_TRNG_CTRL_ROMON_DIS_POS)) /**< CTRL_ROMON_DIS Mask */ 144 #define MXC_V_TRNG_CTRL_ROMON_DIS_RO_0 ((uint32_t)0x1UL) /**< CTRL_ROMON_DIS_RO_0 Value */ 145 #define MXC_S_TRNG_CTRL_ROMON_DIS_RO_0 (MXC_V_TRNG_CTRL_ROMON_DIS_RO_0 << MXC_F_TRNG_CTRL_ROMON_DIS_POS) /**< CTRL_ROMON_DIS_RO_0 Setting */ 146 #define MXC_V_TRNG_CTRL_ROMON_DIS_RO_1 ((uint32_t)0x2UL) /**< CTRL_ROMON_DIS_RO_1 Value */ 147 #define MXC_S_TRNG_CTRL_ROMON_DIS_RO_1 (MXC_V_TRNG_CTRL_ROMON_DIS_RO_1 << MXC_F_TRNG_CTRL_ROMON_DIS_POS) /**< CTRL_ROMON_DIS_RO_1 Setting */ 148 #define MXC_V_TRNG_CTRL_ROMON_DIS_RO_2 ((uint32_t)0x4UL) /**< CTRL_ROMON_DIS_RO_2 Value */ 149 #define MXC_S_TRNG_CTRL_ROMON_DIS_RO_2 (MXC_V_TRNG_CTRL_ROMON_DIS_RO_2 << MXC_F_TRNG_CTRL_ROMON_DIS_POS) /**< CTRL_ROMON_DIS_RO_2 Setting */ 150 151 /**@} end of group TRNG_CTRL_Register */ 152 153 /** 154 * @ingroup trng_registers 155 * @defgroup TRNG_STATUS TRNG_STATUS 156 * @brief Data. The content of this register is valid only when RNG_IS = 1. When TRNG is 157 * disabled, read returns 0x0000 0000. 158 * @{ 159 */ 160 #define MXC_F_TRNG_STATUS_RDY_POS 0 /**< STATUS_RDY Position */ 161 #define MXC_F_TRNG_STATUS_RDY ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_RDY_POS)) /**< STATUS_RDY Mask */ 162 163 #define MXC_F_TRNG_STATUS_OD_HEALTH_POS 1 /**< STATUS_OD_HEALTH Position */ 164 #define MXC_F_TRNG_STATUS_OD_HEALTH ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_OD_HEALTH_POS)) /**< STATUS_OD_HEALTH Mask */ 165 166 #define MXC_F_TRNG_STATUS_HEALTH_POS 2 /**< STATUS_HEALTH Position */ 167 #define MXC_F_TRNG_STATUS_HEALTH ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_HEALTH_POS)) /**< STATUS_HEALTH Mask */ 168 169 #define MXC_F_TRNG_STATUS_SRCFAIL_POS 3 /**< STATUS_SRCFAIL Position */ 170 #define MXC_F_TRNG_STATUS_SRCFAIL ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_SRCFAIL_POS)) /**< STATUS_SRCFAIL Mask */ 171 172 #define MXC_F_TRNG_STATUS_AES_KEYGEN_POS 4 /**< STATUS_AES_KEYGEN Position */ 173 #define MXC_F_TRNG_STATUS_AES_KEYGEN ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_AES_KEYGEN_POS)) /**< STATUS_AES_KEYGEN Mask */ 174 175 #define MXC_F_TRNG_STATUS_OD_ROMON_POS 6 /**< STATUS_OD_ROMON Position */ 176 #define MXC_F_TRNG_STATUS_OD_ROMON ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_OD_ROMON_POS)) /**< STATUS_OD_ROMON Mask */ 177 178 #define MXC_F_TRNG_STATUS_OD_EE_POS 7 /**< STATUS_OD_EE Position */ 179 #define MXC_F_TRNG_STATUS_OD_EE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_OD_EE_POS)) /**< STATUS_OD_EE Mask */ 180 181 #define MXC_F_TRNG_STATUS_PP_ERR_POS 8 /**< STATUS_PP_ERR Position */ 182 #define MXC_F_TRNG_STATUS_PP_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_PP_ERR_POS)) /**< STATUS_PP_ERR Mask */ 183 184 #define MXC_F_TRNG_STATUS_ROMON_0_ERR_POS 9 /**< STATUS_ROMON_0_ERR Position */ 185 #define MXC_F_TRNG_STATUS_ROMON_0_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_ROMON_0_ERR_POS)) /**< STATUS_ROMON_0_ERR Mask */ 186 187 #define MXC_F_TRNG_STATUS_ROMON_1_ERR_POS 10 /**< STATUS_ROMON_1_ERR Position */ 188 #define MXC_F_TRNG_STATUS_ROMON_1_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_ROMON_1_ERR_POS)) /**< STATUS_ROMON_1_ERR Mask */ 189 190 #define MXC_F_TRNG_STATUS_ROMON_2_ERR_POS 11 /**< STATUS_ROMON_2_ERR Position */ 191 #define MXC_F_TRNG_STATUS_ROMON_2_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_ROMON_2_ERR_POS)) /**< STATUS_ROMON_2_ERR Mask */ 192 193 #define MXC_F_TRNG_STATUS_EE_ERR_THR_POS 12 /**< STATUS_EE_ERR_THR Position */ 194 #define MXC_F_TRNG_STATUS_EE_ERR_THR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_EE_ERR_THR_POS)) /**< STATUS_EE_ERR_THR Mask */ 195 196 #define MXC_F_TRNG_STATUS_EE_ERR_OOB_POS 13 /**< STATUS_EE_ERR_OOB Position */ 197 #define MXC_F_TRNG_STATUS_EE_ERR_OOB ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_EE_ERR_OOB_POS)) /**< STATUS_EE_ERR_OOB Mask */ 198 199 #define MXC_F_TRNG_STATUS_EE_ERR_LOCK_POS 14 /**< STATUS_EE_ERR_LOCK Position */ 200 #define MXC_F_TRNG_STATUS_EE_ERR_LOCK ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_EE_ERR_LOCK_POS)) /**< STATUS_EE_ERR_LOCK Mask */ 201 202 #define MXC_F_TRNG_STATUS_TERO_CNT_RDY_POS 16 /**< STATUS_TERO_CNT_RDY Position */ 203 #define MXC_F_TRNG_STATUS_TERO_CNT_RDY ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_TERO_CNT_RDY_POS)) /**< STATUS_TERO_CNT_RDY Mask */ 204 205 #define MXC_F_TRNG_STATUS_RC_ERR_POS 17 /**< STATUS_RC_ERR Position */ 206 #define MXC_F_TRNG_STATUS_RC_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_RC_ERR_POS)) /**< STATUS_RC_ERR Mask */ 207 208 #define MXC_F_TRNG_STATUS_AP_ERR_POS 18 /**< STATUS_AP_ERR Position */ 209 #define MXC_F_TRNG_STATUS_AP_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_AP_ERR_POS)) /**< STATUS_AP_ERR Mask */ 210 211 #define MXC_F_TRNG_STATUS_DATA_DONE_POS 19 /**< STATUS_DATA_DONE Position */ 212 #define MXC_F_TRNG_STATUS_DATA_DONE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_DATA_DONE_POS)) /**< STATUS_DATA_DONE Mask */ 213 214 #define MXC_F_TRNG_STATUS_DATA_NIST_DONE_POS 20 /**< STATUS_DATA_NIST_DONE Position */ 215 #define MXC_F_TRNG_STATUS_DATA_NIST_DONE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_DATA_NIST_DONE_POS)) /**< STATUS_DATA_NIST_DONE Mask */ 216 217 #define MXC_F_TRNG_STATUS_HEALTH_DONE_POS 21 /**< STATUS_HEALTH_DONE Position */ 218 #define MXC_F_TRNG_STATUS_HEALTH_DONE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_HEALTH_DONE_POS)) /**< STATUS_HEALTH_DONE Mask */ 219 220 #define MXC_F_TRNG_STATUS_ROMON_DONE_POS 22 /**< STATUS_ROMON_DONE Position */ 221 #define MXC_F_TRNG_STATUS_ROMON_DONE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_ROMON_DONE_POS)) /**< STATUS_ROMON_DONE Mask */ 222 223 #define MXC_F_TRNG_STATUS_EE_DONE_POS 23 /**< STATUS_EE_DONE Position */ 224 #define MXC_F_TRNG_STATUS_EE_DONE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_EE_DONE_POS)) /**< STATUS_EE_DONE Mask */ 225 226 /**@} end of group TRNG_STATUS_Register */ 227 228 /** 229 * @ingroup trng_registers 230 * @defgroup TRNG_DATA TRNG_DATA 231 * @brief Data. The content of this register is valid only when RNG_IS = 1. When TRNG is 232 * disabled, read returns 0x0000 0000. 233 * @{ 234 */ 235 #define MXC_F_TRNG_DATA_DATA_POS 0 /**< DATA_DATA Position */ 236 #define MXC_F_TRNG_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TRNG_DATA_DATA_POS)) /**< DATA_DATA Mask */ 237 238 /**@} end of group TRNG_DATA_Register */ 239 240 /** 241 * @ingroup trng_registers 242 * @defgroup TRNG_DATA_NIST TRNG_DATA_NIST 243 * @brief Data NIST Register. 244 * @{ 245 */ 246 #define MXC_F_TRNG_DATA_NIST_DATA_POS 0 /**< DATA_NIST_DATA Position */ 247 #define MXC_F_TRNG_DATA_NIST_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TRNG_DATA_NIST_DATA_POS)) /**< DATA_NIST_DATA Mask */ 248 249 /**@} end of group TRNG_DATA_NIST_Register */ 250 251 #ifdef __cplusplus 252 } 253 #endif 254 255 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_TRNG_REGS_H_ 256
