1 /** 2 * @file tmr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup tmr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_TMR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_TMR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup tmr 67 * @defgroup tmr_registers TMR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. 69 * @details 32-bit reloadable timer that can be used for timing and event counting. 70 */ 71 72 /** 73 * @ingroup tmr_registers 74 * Structure type to access the TMR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t cnt; /**< <tt>\b 0x00:</tt> TMR CNT Register */ 78 __IO uint32_t cmp; /**< <tt>\b 0x04:</tt> TMR CMP Register */ 79 __IO uint32_t pwm; /**< <tt>\b 0x08:</tt> TMR PWM Register */ 80 __IO uint32_t intfl; /**< <tt>\b 0x0C:</tt> TMR INTFL Register */ 81 __IO uint32_t ctrl; /**< <tt>\b 0x10:</tt> TMR CTRL Register */ 82 __IO uint32_t nolcmp; /**< <tt>\b 0x14:</tt> TMR NOLCMP Register */ 83 } mxc_tmr_regs_t; 84 85 /* Register offsets for module TMR */ 86 /** 87 * @ingroup tmr_registers 88 * @defgroup TMR_Register_Offsets Register Offsets 89 * @brief TMR Peripheral Register Offsets from the TMR Base Peripheral Address. 90 * @{ 91 */ 92 #define MXC_R_TMR_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt> 0x0000</tt> */ 93 #define MXC_R_TMR_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt> 0x0004</tt> */ 94 #define MXC_R_TMR_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt> 0x0008</tt> */ 95 #define MXC_R_TMR_INTFL ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt> 0x000C</tt> */ 96 #define MXC_R_TMR_CTRL ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt> 0x0010</tt> */ 97 #define MXC_R_TMR_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: <tt> 0x0014</tt> */ 98 /**@} end of group tmr_registers */ 99 100 /** 101 * @ingroup tmr_registers 102 * @defgroup TMR_CNT TMR_CNT 103 * @brief Count. This register stores the current timer count. 104 * @{ 105 */ 106 #define MXC_F_TMR_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ 107 #define MXC_F_TMR_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CNT_COUNT_POS)) /**< CNT_COUNT Mask */ 108 109 /**@} end of group TMR_CNT_Register */ 110 111 /** 112 * @ingroup tmr_registers 113 * @defgroup TMR_CMP TMR_CMP 114 * @brief Compare. This register stores the compare value, which is used to set the 115 * maximum count value to initiate a reload of the timer to 0x0001. 116 * @{ 117 */ 118 #define MXC_F_TMR_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */ 119 #define MXC_F_TMR_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */ 120 121 /**@} end of group TMR_CMP_Register */ 122 123 /** 124 * @ingroup tmr_registers 125 * @defgroup TMR_PWM TMR_PWM 126 * @brief PWM. This register stores the value that is compared to the current timer 127 * count. 128 * @{ 129 */ 130 #define MXC_F_TMR_PWM_PWM_POS 0 /**< PWM_PWM Position */ 131 #define MXC_F_TMR_PWM_PWM ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_PWM_PWM_POS)) /**< PWM_PWM Mask */ 132 133 /**@} end of group TMR_PWM_Register */ 134 135 /** 136 * @ingroup tmr_registers 137 * @defgroup TMR_INTFL TMR_INTFL 138 * @brief Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the 139 * associated interrupt. 140 * @{ 141 */ 142 #define MXC_F_TMR_INTFL_IRQ_POS 0 /**< INTFL_IRQ Position */ 143 #define MXC_F_TMR_INTFL_IRQ ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_POS)) /**< INTFL_IRQ Mask */ 144 145 /**@} end of group TMR_INTFL_Register */ 146 147 /** 148 * @ingroup tmr_registers 149 * @defgroup TMR_CTRL TMR_CTRL 150 * @brief Timer Control Register. 151 * @{ 152 */ 153 #define MXC_F_TMR_CTRL_MODE_POS 0 /**< CTRL_MODE Position */ 154 #define MXC_F_TMR_CTRL_MODE ((uint32_t)(0x7UL << MXC_F_TMR_CTRL_MODE_POS)) /**< CTRL_MODE Mask */ 155 #define MXC_V_TMR_CTRL_MODE_ONESHOT ((uint32_t)0x0UL) /**< CTRL_MODE_ONESHOT Value */ 156 #define MXC_S_TMR_CTRL_MODE_ONESHOT (MXC_V_TMR_CTRL_MODE_ONESHOT << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_ONESHOT Setting */ 157 #define MXC_V_TMR_CTRL_MODE_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL_MODE_CONTINUOUS Value */ 158 #define MXC_S_TMR_CTRL_MODE_CONTINUOUS (MXC_V_TMR_CTRL_MODE_CONTINUOUS << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_CONTINUOUS Setting */ 159 #define MXC_V_TMR_CTRL_MODE_COUNTER ((uint32_t)0x2UL) /**< CTRL_MODE_COUNTER Value */ 160 #define MXC_S_TMR_CTRL_MODE_COUNTER (MXC_V_TMR_CTRL_MODE_COUNTER << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_COUNTER Setting */ 161 #define MXC_V_TMR_CTRL_MODE_PWM ((uint32_t)0x3UL) /**< CTRL_MODE_PWM Value */ 162 #define MXC_S_TMR_CTRL_MODE_PWM (MXC_V_TMR_CTRL_MODE_PWM << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_PWM Setting */ 163 #define MXC_V_TMR_CTRL_MODE_CAPTURE ((uint32_t)0x4UL) /**< CTRL_MODE_CAPTURE Value */ 164 #define MXC_S_TMR_CTRL_MODE_CAPTURE (MXC_V_TMR_CTRL_MODE_CAPTURE << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_CAPTURE Setting */ 165 #define MXC_V_TMR_CTRL_MODE_COMPARE ((uint32_t)0x5UL) /**< CTRL_MODE_COMPARE Value */ 166 #define MXC_S_TMR_CTRL_MODE_COMPARE (MXC_V_TMR_CTRL_MODE_COMPARE << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_COMPARE Setting */ 167 #define MXC_V_TMR_CTRL_MODE_GATED ((uint32_t)0x6UL) /**< CTRL_MODE_GATED Value */ 168 #define MXC_S_TMR_CTRL_MODE_GATED (MXC_V_TMR_CTRL_MODE_GATED << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_GATED Setting */ 169 #define MXC_V_TMR_CTRL_MODE_CAPTURECOMPARE ((uint32_t)0x7UL) /**< CTRL_MODE_CAPTURECOMPARE Value */ 170 #define MXC_S_TMR_CTRL_MODE_CAPTURECOMPARE (MXC_V_TMR_CTRL_MODE_CAPTURECOMPARE << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_CAPTURECOMPARE Setting */ 171 172 #define MXC_F_TMR_CTRL_CLKDIV_POS 3 /**< CTRL_CLKDIV Position */ 173 #define MXC_F_TMR_CTRL_CLKDIV ((uint32_t)(0x7UL << MXC_F_TMR_CTRL_CLKDIV_POS)) /**< CTRL_CLKDIV Mask */ 174 #define MXC_V_TMR_CTRL_CLKDIV_DIV1 ((uint32_t)0x0UL) /**< CTRL_CLKDIV_DIV1 Value */ 175 #define MXC_S_TMR_CTRL_CLKDIV_DIV1 (MXC_V_TMR_CTRL_CLKDIV_DIV1 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV1 Setting */ 176 #define MXC_V_TMR_CTRL_CLKDIV_DIV2 ((uint32_t)0x1UL) /**< CTRL_CLKDIV_DIV2 Value */ 177 #define MXC_S_TMR_CTRL_CLKDIV_DIV2 (MXC_V_TMR_CTRL_CLKDIV_DIV2 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV2 Setting */ 178 #define MXC_V_TMR_CTRL_CLKDIV_DIV4 ((uint32_t)0x2UL) /**< CTRL_CLKDIV_DIV4 Value */ 179 #define MXC_S_TMR_CTRL_CLKDIV_DIV4 (MXC_V_TMR_CTRL_CLKDIV_DIV4 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV4 Setting */ 180 #define MXC_V_TMR_CTRL_CLKDIV_DIV8 ((uint32_t)0x3UL) /**< CTRL_CLKDIV_DIV8 Value */ 181 #define MXC_S_TMR_CTRL_CLKDIV_DIV8 (MXC_V_TMR_CTRL_CLKDIV_DIV8 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV8 Setting */ 182 #define MXC_V_TMR_CTRL_CLKDIV_DIV16 ((uint32_t)0x4UL) /**< CTRL_CLKDIV_DIV16 Value */ 183 #define MXC_S_TMR_CTRL_CLKDIV_DIV16 (MXC_V_TMR_CTRL_CLKDIV_DIV16 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV16 Setting */ 184 #define MXC_V_TMR_CTRL_CLKDIV_DIV32 ((uint32_t)0x5UL) /**< CTRL_CLKDIV_DIV32 Value */ 185 #define MXC_S_TMR_CTRL_CLKDIV_DIV32 (MXC_V_TMR_CTRL_CLKDIV_DIV32 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV32 Setting */ 186 #define MXC_V_TMR_CTRL_CLKDIV_DIV64 ((uint32_t)0x6UL) /**< CTRL_CLKDIV_DIV64 Value */ 187 #define MXC_S_TMR_CTRL_CLKDIV_DIV64 (MXC_V_TMR_CTRL_CLKDIV_DIV64 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV64 Setting */ 188 #define MXC_V_TMR_CTRL_CLKDIV_DIV128 ((uint32_t)0x7UL) /**< CTRL_CLKDIV_DIV128 Value */ 189 #define MXC_S_TMR_CTRL_CLKDIV_DIV128 (MXC_V_TMR_CTRL_CLKDIV_DIV128 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV128 Setting */ 190 191 #define MXC_F_TMR_CTRL_POL_POS 6 /**< CTRL_POL Position */ 192 #define MXC_F_TMR_CTRL_POL ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_POL_POS)) /**< CTRL_POL Mask */ 193 194 #define MXC_F_TMR_CTRL_EN_POS 7 /**< CTRL_EN Position */ 195 #define MXC_F_TMR_CTRL_EN ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_EN_POS)) /**< CTRL_EN Mask */ 196 197 #define MXC_F_TMR_CTRL_CLKDIV3_POS 8 /**< CTRL_CLKDIV3 Position */ 198 #define MXC_F_TMR_CTRL_CLKDIV3 ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_CLKDIV3_POS)) /**< CTRL_CLKDIV3 Mask */ 199 200 #define MXC_F_TMR_CTRL_PWMSYNC_POS 9 /**< CTRL_PWMSYNC Position */ 201 #define MXC_F_TMR_CTRL_PWMSYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_PWMSYNC_POS)) /**< CTRL_PWMSYNC Mask */ 202 203 #define MXC_F_TMR_CTRL_NOLHPOL_POS 10 /**< CTRL_NOLHPOL Position */ 204 #define MXC_F_TMR_CTRL_NOLHPOL ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_NOLHPOL_POS)) /**< CTRL_NOLHPOL Mask */ 205 206 #define MXC_F_TMR_CTRL_NOLLPOL_POS 11 /**< CTRL_NOLLPOL Position */ 207 #define MXC_F_TMR_CTRL_NOLLPOL ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_NOLLPOL_POS)) /**< CTRL_NOLLPOL Mask */ 208 209 #define MXC_F_TMR_CTRL_PWMCKBD_POS 12 /**< CTRL_PWMCKBD Position */ 210 #define MXC_F_TMR_CTRL_PWMCKBD ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_PWMCKBD_POS)) /**< CTRL_PWMCKBD Mask */ 211 212 /**@} end of group TMR_CTRL_Register */ 213 214 /** 215 * @ingroup tmr_registers 216 * @defgroup TMR_NOLCMP TMR_NOLCMP 217 * @brief Timer Non-Overlapping Compare Register. 218 * @{ 219 */ 220 #define MXC_F_TMR_NOLCMP_LO_POS 0 /**< NOLCMP_LO Position */ 221 #define MXC_F_TMR_NOLCMP_LO ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_POS)) /**< NOLCMP_LO Mask */ 222 223 #define MXC_F_TMR_NOLCMP_HI_POS 8 /**< NOLCMP_HI Position */ 224 #define MXC_F_TMR_NOLCMP_HI ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_POS)) /**< NOLCMP_HI Mask */ 225 226 /**@} end of group TMR_NOLCMP_Register */ 227 228 #ifdef __cplusplus 229 } 230 #endif 231 232 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_TMR_REGS_H_ 233
