1 /** 2 * @file spixfm_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPIXFM Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup spixfm_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SPIXFM_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SPIXFM_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup spixfm 67 * @defgroup spixfm_registers SPIXFM_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SPIXFM Peripheral Module. 69 * @details SPIXF Master 70 */ 71 72 /** 73 * @ingroup spixfm_registers 74 * Structure type to access the SPIXFM Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> SPIXFM CTRL Register */ 78 __IO uint32_t fetchctrl; /**< <tt>\b 0x04:</tt> SPIXFM FETCHCTRL Register */ 79 __IO uint32_t modectrl; /**< <tt>\b 0x08:</tt> SPIXFM MODECTRL Register */ 80 __IO uint32_t modedata; /**< <tt>\b 0x0C:</tt> SPIXFM MODEDATA Register */ 81 __IO uint32_t fbctrl; /**< <tt>\b 0x10:</tt> SPIXFM FBCTRL Register */ 82 __R uint32_t rsv_0x14_0x1b[2]; 83 __IO uint32_t ioctrl; /**< <tt>\b 0x1C:</tt> SPIXFM IOCTRL Register */ 84 __IO uint32_t memsecctrl; /**< <tt>\b 0x20:</tt> SPIXFM MEMSECCTRL Register */ 85 __IO uint32_t busidle; /**< <tt>\b 0x24:</tt> SPIXFM BUSIDLE Register */ 86 __IO uint32_t authoffset; /**< <tt>\b 0x28:</tt> SPIXFM AUTHOFFSET Register */ 87 __IO uint32_t bypass_mode; /**< <tt>\b 0x2C:</tt> SPIXFM BYPASS_MODE Register */ 88 } mxc_spixfm_regs_t; 89 90 /* Register offsets for module SPIXFM */ 91 /** 92 * @ingroup spixfm_registers 93 * @defgroup SPIXFM_Register_Offsets Register Offsets 94 * @brief SPIXFM Peripheral Register Offsets from the SPIXFM Base Peripheral Address. 95 * @{ 96 */ 97 #define MXC_R_SPIXFM_CTRL ((uint32_t)0x00000000UL) /**< Offset from SPIXFM Base Address: <tt> 0x0000</tt> */ 98 #define MXC_R_SPIXFM_FETCHCTRL ((uint32_t)0x00000004UL) /**< Offset from SPIXFM Base Address: <tt> 0x0004</tt> */ 99 #define MXC_R_SPIXFM_MODECTRL ((uint32_t)0x00000008UL) /**< Offset from SPIXFM Base Address: <tt> 0x0008</tt> */ 100 #define MXC_R_SPIXFM_MODEDATA ((uint32_t)0x0000000CUL) /**< Offset from SPIXFM Base Address: <tt> 0x000C</tt> */ 101 #define MXC_R_SPIXFM_FBCTRL ((uint32_t)0x00000010UL) /**< Offset from SPIXFM Base Address: <tt> 0x0010</tt> */ 102 #define MXC_R_SPIXFM_IOCTRL ((uint32_t)0x0000001CUL) /**< Offset from SPIXFM Base Address: <tt> 0x001C</tt> */ 103 #define MXC_R_SPIXFM_MEMSECCTRL ((uint32_t)0x00000020UL) /**< Offset from SPIXFM Base Address: <tt> 0x0020</tt> */ 104 #define MXC_R_SPIXFM_BUSIDLE ((uint32_t)0x00000024UL) /**< Offset from SPIXFM Base Address: <tt> 0x0024</tt> */ 105 #define MXC_R_SPIXFM_AUTHOFFSET ((uint32_t)0x00000028UL) /**< Offset from SPIXFM Base Address: <tt> 0x0028</tt> */ 106 #define MXC_R_SPIXFM_BYPASS_MODE ((uint32_t)0x0000002CUL) /**< Offset from SPIXFM Base Address: <tt> 0x002C</tt> */ 107 /**@} end of group spixfm_registers */ 108 109 /** 110 * @ingroup spixfm_registers 111 * @defgroup SPIXFM_CTRL SPIXFM_CTRL 112 * @brief SPIX Control Register. 113 * @{ 114 */ 115 #define MXC_F_SPIXFM_CTRL_MODE_POS 0 /**< CTRL_MODE Position */ 116 #define MXC_F_SPIXFM_CTRL_MODE ((uint32_t)(0x3UL << MXC_F_SPIXFM_CTRL_MODE_POS)) /**< CTRL_MODE Mask */ 117 #define MXC_V_SPIXFM_CTRL_MODE_SCLK_HI_SAMPLE_RISING ((uint32_t)0x0UL) /**< CTRL_MODE_SCLK_HI_SAMPLE_RISING Value */ 118 #define MXC_S_SPIXFM_CTRL_MODE_SCLK_HI_SAMPLE_RISING (MXC_V_SPIXFM_CTRL_MODE_SCLK_HI_SAMPLE_RISING << MXC_F_SPIXFM_CTRL_MODE_POS) /**< CTRL_MODE_SCLK_HI_SAMPLE_RISING Setting */ 119 #define MXC_V_SPIXFM_CTRL_MODE_SCLK_LO_SAMPLE_FAILLING ((uint32_t)0x3UL) /**< CTRL_MODE_SCLK_LO_SAMPLE_FAILLING Value */ 120 #define MXC_S_SPIXFM_CTRL_MODE_SCLK_LO_SAMPLE_FAILLING (MXC_V_SPIXFM_CTRL_MODE_SCLK_LO_SAMPLE_FAILLING << MXC_F_SPIXFM_CTRL_MODE_POS) /**< CTRL_MODE_SCLK_LO_SAMPLE_FAILLING Setting */ 121 122 #define MXC_F_SPIXFM_CTRL_SSPOL_POS 2 /**< CTRL_SSPOL Position */ 123 #define MXC_F_SPIXFM_CTRL_SSPOL ((uint32_t)(0x1UL << MXC_F_SPIXFM_CTRL_SSPOL_POS)) /**< CTRL_SSPOL Mask */ 124 125 #define MXC_F_SPIXFM_CTRL_SSEL_POS 4 /**< CTRL_SSEL Position */ 126 #define MXC_F_SPIXFM_CTRL_SSEL ((uint32_t)(0x7UL << MXC_F_SPIXFM_CTRL_SSEL_POS)) /**< CTRL_SSEL Mask */ 127 128 #define MXC_F_SPIXFM_CTRL_LOCLK_POS 8 /**< CTRL_LOCLK Position */ 129 #define MXC_F_SPIXFM_CTRL_LOCLK ((uint32_t)(0xFUL << MXC_F_SPIXFM_CTRL_LOCLK_POS)) /**< CTRL_LOCLK Mask */ 130 131 #define MXC_F_SPIXFM_CTRL_HICLK_POS 12 /**< CTRL_HICLK Position */ 132 #define MXC_F_SPIXFM_CTRL_HICLK ((uint32_t)(0xFUL << MXC_F_SPIXFM_CTRL_HICLK_POS)) /**< CTRL_HICLK Mask */ 133 134 #define MXC_F_SPIXFM_CTRL_SSACT_POS 16 /**< CTRL_SSACT Position */ 135 #define MXC_F_SPIXFM_CTRL_SSACT ((uint32_t)(0x3UL << MXC_F_SPIXFM_CTRL_SSACT_POS)) /**< CTRL_SSACT Mask */ 136 #define MXC_V_SPIXFM_CTRL_SSACT_OFF ((uint32_t)0x0UL) /**< CTRL_SSACT_OFF Value */ 137 #define MXC_S_SPIXFM_CTRL_SSACT_OFF (MXC_V_SPIXFM_CTRL_SSACT_OFF << MXC_F_SPIXFM_CTRL_SSACT_POS) /**< CTRL_SSACT_OFF Setting */ 138 #define MXC_V_SPIXFM_CTRL_SSACT_FOR_2_MOD_CLK ((uint32_t)0x1UL) /**< CTRL_SSACT_FOR_2_MOD_CLK Value */ 139 #define MXC_S_SPIXFM_CTRL_SSACT_FOR_2_MOD_CLK (MXC_V_SPIXFM_CTRL_SSACT_FOR_2_MOD_CLK << MXC_F_SPIXFM_CTRL_SSACT_POS) /**< CTRL_SSACT_FOR_2_MOD_CLK Setting */ 140 #define MXC_V_SPIXFM_CTRL_SSACT_FOR_4_MOD_CLK ((uint32_t)0x2UL) /**< CTRL_SSACT_FOR_4_MOD_CLK Value */ 141 #define MXC_S_SPIXFM_CTRL_SSACT_FOR_4_MOD_CLK (MXC_V_SPIXFM_CTRL_SSACT_FOR_4_MOD_CLK << MXC_F_SPIXFM_CTRL_SSACT_POS) /**< CTRL_SSACT_FOR_4_MOD_CLK Setting */ 142 #define MXC_V_SPIXFM_CTRL_SSACT_FOR_8_MOD_CLK ((uint32_t)0x3UL) /**< CTRL_SSACT_FOR_8_MOD_CLK Value */ 143 #define MXC_S_SPIXFM_CTRL_SSACT_FOR_8_MOD_CLK (MXC_V_SPIXFM_CTRL_SSACT_FOR_8_MOD_CLK << MXC_F_SPIXFM_CTRL_SSACT_POS) /**< CTRL_SSACT_FOR_8_MOD_CLK Setting */ 144 145 #define MXC_F_SPIXFM_CTRL_SSINACT_POS 18 /**< CTRL_SSINACT Position */ 146 #define MXC_F_SPIXFM_CTRL_SSINACT ((uint32_t)(0x3UL << MXC_F_SPIXFM_CTRL_SSINACT_POS)) /**< CTRL_SSINACT Mask */ 147 #define MXC_V_SPIXFM_CTRL_SSINACT_FOR_1_MOD_CLK ((uint32_t)0x0UL) /**< CTRL_SSINACT_FOR_1_MOD_CLK Value */ 148 #define MXC_S_SPIXFM_CTRL_SSINACT_FOR_1_MOD_CLK (MXC_V_SPIXFM_CTRL_SSINACT_FOR_1_MOD_CLK << MXC_F_SPIXFM_CTRL_SSINACT_POS) /**< CTRL_SSINACT_FOR_1_MOD_CLK Setting */ 149 #define MXC_V_SPIXFM_CTRL_SSINACT_FOR_3_MOD_CLK ((uint32_t)0x1UL) /**< CTRL_SSINACT_FOR_3_MOD_CLK Value */ 150 #define MXC_S_SPIXFM_CTRL_SSINACT_FOR_3_MOD_CLK (MXC_V_SPIXFM_CTRL_SSINACT_FOR_3_MOD_CLK << MXC_F_SPIXFM_CTRL_SSINACT_POS) /**< CTRL_SSINACT_FOR_3_MOD_CLK Setting */ 151 #define MXC_V_SPIXFM_CTRL_SSINACT_FOR_5_MOD_CLK ((uint32_t)0x2UL) /**< CTRL_SSINACT_FOR_5_MOD_CLK Value */ 152 #define MXC_S_SPIXFM_CTRL_SSINACT_FOR_5_MOD_CLK (MXC_V_SPIXFM_CTRL_SSINACT_FOR_5_MOD_CLK << MXC_F_SPIXFM_CTRL_SSINACT_POS) /**< CTRL_SSINACT_FOR_5_MOD_CLK Setting */ 153 #define MXC_V_SPIXFM_CTRL_SSINACT_FOR_9_MOD_CLK ((uint32_t)0x3UL) /**< CTRL_SSINACT_FOR_9_MOD_CLK Value */ 154 #define MXC_S_SPIXFM_CTRL_SSINACT_FOR_9_MOD_CLK (MXC_V_SPIXFM_CTRL_SSINACT_FOR_9_MOD_CLK << MXC_F_SPIXFM_CTRL_SSINACT_POS) /**< CTRL_SSINACT_FOR_9_MOD_CLK Setting */ 155 156 /**@} end of group SPIXFM_CTRL_Register */ 157 158 /** 159 * @ingroup spixfm_registers 160 * @defgroup SPIXFM_FETCHCTRL SPIXFM_FETCHCTRL 161 * @brief SPIX Fetch Control Register. 162 * @{ 163 */ 164 #define MXC_F_SPIXFM_FETCHCTRL_CMD_VAL_POS 0 /**< FETCHCTRL_CMD_VAL Position */ 165 #define MXC_F_SPIXFM_FETCHCTRL_CMD_VAL ((uint32_t)(0xFFUL << MXC_F_SPIXFM_FETCHCTRL_CMD_VAL_POS)) /**< FETCHCTRL_CMD_VAL Mask */ 166 167 #define MXC_F_SPIXFM_FETCHCTRL_CMD_WDTH_POS 8 /**< FETCHCTRL_CMD_WDTH Position */ 168 #define MXC_F_SPIXFM_FETCHCTRL_CMD_WDTH ((uint32_t)(0x3UL << MXC_F_SPIXFM_FETCHCTRL_CMD_WDTH_POS)) /**< FETCHCTRL_CMD_WDTH Mask */ 169 #define MXC_V_SPIXFM_FETCHCTRL_CMD_WDTH_SINGLE ((uint32_t)0x0UL) /**< FETCHCTRL_CMD_WDTH_SINGLE Value */ 170 #define MXC_S_SPIXFM_FETCHCTRL_CMD_WDTH_SINGLE (MXC_V_SPIXFM_FETCHCTRL_CMD_WDTH_SINGLE << MXC_F_SPIXFM_FETCHCTRL_CMD_WDTH_POS) /**< FETCHCTRL_CMD_WDTH_SINGLE Setting */ 171 #define MXC_V_SPIXFM_FETCHCTRL_CMD_WDTH_DUAL_IO ((uint32_t)0x1UL) /**< FETCHCTRL_CMD_WDTH_DUAL_IO Value */ 172 #define MXC_S_SPIXFM_FETCHCTRL_CMD_WDTH_DUAL_IO (MXC_V_SPIXFM_FETCHCTRL_CMD_WDTH_DUAL_IO << MXC_F_SPIXFM_FETCHCTRL_CMD_WDTH_POS) /**< FETCHCTRL_CMD_WDTH_DUAL_IO Setting */ 173 #define MXC_V_SPIXFM_FETCHCTRL_CMD_WDTH_QUAD_IO ((uint32_t)0x2UL) /**< FETCHCTRL_CMD_WDTH_QUAD_IO Value */ 174 #define MXC_S_SPIXFM_FETCHCTRL_CMD_WDTH_QUAD_IO (MXC_V_SPIXFM_FETCHCTRL_CMD_WDTH_QUAD_IO << MXC_F_SPIXFM_FETCHCTRL_CMD_WDTH_POS) /**< FETCHCTRL_CMD_WDTH_QUAD_IO Setting */ 175 #define MXC_V_SPIXFM_FETCHCTRL_CMD_WDTH_INVALID ((uint32_t)0x3UL) /**< FETCHCTRL_CMD_WDTH_INVALID Value */ 176 #define MXC_S_SPIXFM_FETCHCTRL_CMD_WDTH_INVALID (MXC_V_SPIXFM_FETCHCTRL_CMD_WDTH_INVALID << MXC_F_SPIXFM_FETCHCTRL_CMD_WDTH_POS) /**< FETCHCTRL_CMD_WDTH_INVALID Setting */ 177 178 #define MXC_F_SPIXFM_FETCHCTRL_ADDR_WDTH_POS 10 /**< FETCHCTRL_ADDR_WDTH Position */ 179 #define MXC_F_SPIXFM_FETCHCTRL_ADDR_WDTH ((uint32_t)(0x3UL << MXC_F_SPIXFM_FETCHCTRL_ADDR_WDTH_POS)) /**< FETCHCTRL_ADDR_WDTH Mask */ 180 #define MXC_V_SPIXFM_FETCHCTRL_ADDR_WDTH_SINGLE ((uint32_t)0x0UL) /**< FETCHCTRL_ADDR_WDTH_SINGLE Value */ 181 #define MXC_S_SPIXFM_FETCHCTRL_ADDR_WDTH_SINGLE (MXC_V_SPIXFM_FETCHCTRL_ADDR_WDTH_SINGLE << MXC_F_SPIXFM_FETCHCTRL_ADDR_WDTH_POS) /**< FETCHCTRL_ADDR_WDTH_SINGLE Setting */ 182 #define MXC_V_SPIXFM_FETCHCTRL_ADDR_WDTH_DUAL_IO ((uint32_t)0x1UL) /**< FETCHCTRL_ADDR_WDTH_DUAL_IO Value */ 183 #define MXC_S_SPIXFM_FETCHCTRL_ADDR_WDTH_DUAL_IO (MXC_V_SPIXFM_FETCHCTRL_ADDR_WDTH_DUAL_IO << MXC_F_SPIXFM_FETCHCTRL_ADDR_WDTH_POS) /**< FETCHCTRL_ADDR_WDTH_DUAL_IO Setting */ 184 #define MXC_V_SPIXFM_FETCHCTRL_ADDR_WDTH_QUAD_IO ((uint32_t)0x2UL) /**< FETCHCTRL_ADDR_WDTH_QUAD_IO Value */ 185 #define MXC_S_SPIXFM_FETCHCTRL_ADDR_WDTH_QUAD_IO (MXC_V_SPIXFM_FETCHCTRL_ADDR_WDTH_QUAD_IO << MXC_F_SPIXFM_FETCHCTRL_ADDR_WDTH_POS) /**< FETCHCTRL_ADDR_WDTH_QUAD_IO Setting */ 186 #define MXC_V_SPIXFM_FETCHCTRL_ADDR_WDTH_INVALID ((uint32_t)0x3UL) /**< FETCHCTRL_ADDR_WDTH_INVALID Value */ 187 #define MXC_S_SPIXFM_FETCHCTRL_ADDR_WDTH_INVALID (MXC_V_SPIXFM_FETCHCTRL_ADDR_WDTH_INVALID << MXC_F_SPIXFM_FETCHCTRL_ADDR_WDTH_POS) /**< FETCHCTRL_ADDR_WDTH_INVALID Setting */ 188 189 #define MXC_F_SPIXFM_FETCHCTRL_DATA_WDTH_POS 12 /**< FETCHCTRL_DATA_WDTH Position */ 190 #define MXC_F_SPIXFM_FETCHCTRL_DATA_WDTH ((uint32_t)(0x3UL << MXC_F_SPIXFM_FETCHCTRL_DATA_WDTH_POS)) /**< FETCHCTRL_DATA_WDTH Mask */ 191 #define MXC_V_SPIXFM_FETCHCTRL_DATA_WDTH_SINGLE ((uint32_t)0x0UL) /**< FETCHCTRL_DATA_WDTH_SINGLE Value */ 192 #define MXC_S_SPIXFM_FETCHCTRL_DATA_WDTH_SINGLE (MXC_V_SPIXFM_FETCHCTRL_DATA_WDTH_SINGLE << MXC_F_SPIXFM_FETCHCTRL_DATA_WDTH_POS) /**< FETCHCTRL_DATA_WDTH_SINGLE Setting */ 193 #define MXC_V_SPIXFM_FETCHCTRL_DATA_WDTH_DUAL_IO ((uint32_t)0x1UL) /**< FETCHCTRL_DATA_WDTH_DUAL_IO Value */ 194 #define MXC_S_SPIXFM_FETCHCTRL_DATA_WDTH_DUAL_IO (MXC_V_SPIXFM_FETCHCTRL_DATA_WDTH_DUAL_IO << MXC_F_SPIXFM_FETCHCTRL_DATA_WDTH_POS) /**< FETCHCTRL_DATA_WDTH_DUAL_IO Setting */ 195 #define MXC_V_SPIXFM_FETCHCTRL_DATA_WDTH_QUAD_IO ((uint32_t)0x2UL) /**< FETCHCTRL_DATA_WDTH_QUAD_IO Value */ 196 #define MXC_S_SPIXFM_FETCHCTRL_DATA_WDTH_QUAD_IO (MXC_V_SPIXFM_FETCHCTRL_DATA_WDTH_QUAD_IO << MXC_F_SPIXFM_FETCHCTRL_DATA_WDTH_POS) /**< FETCHCTRL_DATA_WDTH_QUAD_IO Setting */ 197 #define MXC_V_SPIXFM_FETCHCTRL_DATA_WDTH_INVALID ((uint32_t)0x3UL) /**< FETCHCTRL_DATA_WDTH_INVALID Value */ 198 #define MXC_S_SPIXFM_FETCHCTRL_DATA_WDTH_INVALID (MXC_V_SPIXFM_FETCHCTRL_DATA_WDTH_INVALID << MXC_F_SPIXFM_FETCHCTRL_DATA_WDTH_POS) /**< FETCHCTRL_DATA_WDTH_INVALID Setting */ 199 200 #define MXC_F_SPIXFM_FETCHCTRL_4BADDR_POS 16 /**< FETCHCTRL_4BADDR Position */ 201 #define MXC_F_SPIXFM_FETCHCTRL_4BADDR ((uint32_t)(0x1UL << MXC_F_SPIXFM_FETCHCTRL_4BADDR_POS)) /**< FETCHCTRL_4BADDR Mask */ 202 203 /**@} end of group SPIXFM_FETCHCTRL_Register */ 204 205 /** 206 * @ingroup spixfm_registers 207 * @defgroup SPIXFM_MODECTRL SPIXFM_MODECTRL 208 * @brief SPIX Mode Control Register. 209 * @{ 210 */ 211 #define MXC_F_SPIXFM_MODECTRL_MDCLK_POS 0 /**< MODECTRL_MDCLK Position */ 212 #define MXC_F_SPIXFM_MODECTRL_MDCLK ((uint32_t)(0xFUL << MXC_F_SPIXFM_MODECTRL_MDCLK_POS)) /**< MODECTRL_MDCLK Mask */ 213 214 #define MXC_F_SPIXFM_MODECTRL_NOCMD_POS 8 /**< MODECTRL_NOCMD Position */ 215 #define MXC_F_SPIXFM_MODECTRL_NOCMD ((uint32_t)(0x1UL << MXC_F_SPIXFM_MODECTRL_NOCMD_POS)) /**< MODECTRL_NOCMD Mask */ 216 217 #define MXC_F_SPIXFM_MODECTRL_EXIT_NOCMD_POS 9 /**< MODECTRL_EXIT_NOCMD Position */ 218 #define MXC_F_SPIXFM_MODECTRL_EXIT_NOCMD ((uint32_t)(0x1UL << MXC_F_SPIXFM_MODECTRL_EXIT_NOCMD_POS)) /**< MODECTRL_EXIT_NOCMD Mask */ 219 220 /**@} end of group SPIXFM_MODECTRL_Register */ 221 222 /** 223 * @ingroup spixfm_registers 224 * @defgroup SPIXFM_MODEDATA SPIXFM_MODEDATA 225 * @brief SPIX Mode Data Register. 226 * @{ 227 */ 228 #define MXC_F_SPIXFM_MODEDATA_DATA_POS 0 /**< MODEDATA_DATA Position */ 229 #define MXC_F_SPIXFM_MODEDATA_DATA ((uint32_t)(0xFFFFUL << MXC_F_SPIXFM_MODEDATA_DATA_POS)) /**< MODEDATA_DATA Mask */ 230 231 #define MXC_F_SPIXFM_MODEDATA_OUT_EN_POS 16 /**< MODEDATA_OUT_EN Position */ 232 #define MXC_F_SPIXFM_MODEDATA_OUT_EN ((uint32_t)(0xFFFFUL << MXC_F_SPIXFM_MODEDATA_OUT_EN_POS)) /**< MODEDATA_OUT_EN Mask */ 233 234 /**@} end of group SPIXFM_MODEDATA_Register */ 235 236 /** 237 * @ingroup spixfm_registers 238 * @defgroup SPIXFM_FBCTRL SPIXFM_FBCTRL 239 * @brief SPIX Feedback Control Register. 240 * @{ 241 */ 242 #define MXC_F_SPIXFM_FBCTRL_EN_POS 0 /**< FBCTRL_EN Position */ 243 #define MXC_F_SPIXFM_FBCTRL_EN ((uint32_t)(0x1UL << MXC_F_SPIXFM_FBCTRL_EN_POS)) /**< FBCTRL_EN Mask */ 244 245 #define MXC_F_SPIXFM_FBCTRL_INVERT_POS 1 /**< FBCTRL_INVERT Position */ 246 #define MXC_F_SPIXFM_FBCTRL_INVERT ((uint32_t)(0x1UL << MXC_F_SPIXFM_FBCTRL_INVERT_POS)) /**< FBCTRL_INVERT Mask */ 247 248 /**@} end of group SPIXFM_FBCTRL_Register */ 249 250 /** 251 * @ingroup spixfm_registers 252 * @defgroup SPIXFM_IOCTRL SPIXFM_IOCTRL 253 * @brief SPIX IO Control Register. 254 * @{ 255 */ 256 #define MXC_F_SPIXFM_IOCTRL_SCLK_DS_POS 0 /**< IOCTRL_SCLK_DS Position */ 257 #define MXC_F_SPIXFM_IOCTRL_SCLK_DS ((uint32_t)(0x1UL << MXC_F_SPIXFM_IOCTRL_SCLK_DS_POS)) /**< IOCTRL_SCLK_DS Mask */ 258 259 #define MXC_F_SPIXFM_IOCTRL_SS_DS_POS 1 /**< IOCTRL_SS_DS Position */ 260 #define MXC_F_SPIXFM_IOCTRL_SS_DS ((uint32_t)(0x1UL << MXC_F_SPIXFM_IOCTRL_SS_DS_POS)) /**< IOCTRL_SS_DS Mask */ 261 262 #define MXC_F_SPIXFM_IOCTRL_SDIO_DS_POS 2 /**< IOCTRL_SDIO_DS Position */ 263 #define MXC_F_SPIXFM_IOCTRL_SDIO_DS ((uint32_t)(0x1UL << MXC_F_SPIXFM_IOCTRL_SDIO_DS_POS)) /**< IOCTRL_SDIO_DS Mask */ 264 265 #define MXC_F_SPIXFM_IOCTRL_PADCTRL_POS 3 /**< IOCTRL_PADCTRL Position */ 266 #define MXC_F_SPIXFM_IOCTRL_PADCTRL ((uint32_t)(0x3UL << MXC_F_SPIXFM_IOCTRL_PADCTRL_POS)) /**< IOCTRL_PADCTRL Mask */ 267 #define MXC_V_SPIXFM_IOCTRL_PADCTRL_TRI_STATE ((uint32_t)0x0UL) /**< IOCTRL_PADCTRL_TRI_STATE Value */ 268 #define MXC_S_SPIXFM_IOCTRL_PADCTRL_TRI_STATE (MXC_V_SPIXFM_IOCTRL_PADCTRL_TRI_STATE << MXC_F_SPIXFM_IOCTRL_PADCTRL_POS) /**< IOCTRL_PADCTRL_TRI_STATE Setting */ 269 #define MXC_V_SPIXFM_IOCTRL_PADCTRL_PULL_UP ((uint32_t)0x1UL) /**< IOCTRL_PADCTRL_PULL_UP Value */ 270 #define MXC_S_SPIXFM_IOCTRL_PADCTRL_PULL_UP (MXC_V_SPIXFM_IOCTRL_PADCTRL_PULL_UP << MXC_F_SPIXFM_IOCTRL_PADCTRL_POS) /**< IOCTRL_PADCTRL_PULL_UP Setting */ 271 #define MXC_V_SPIXFM_IOCTRL_PADCTRL_PULL_DOWN ((uint32_t)0x2UL) /**< IOCTRL_PADCTRL_PULL_DOWN Value */ 272 #define MXC_S_SPIXFM_IOCTRL_PADCTRL_PULL_DOWN (MXC_V_SPIXFM_IOCTRL_PADCTRL_PULL_DOWN << MXC_F_SPIXFM_IOCTRL_PADCTRL_POS) /**< IOCTRL_PADCTRL_PULL_DOWN Setting */ 273 274 /**@} end of group SPIXFM_IOCTRL_Register */ 275 276 /** 277 * @ingroup spixfm_registers 278 * @defgroup SPIXFM_MEMSECCTRL SPIXFM_MEMSECCTRL 279 * @brief SPIX Memory Security Control Register. 280 * @{ 281 */ 282 #define MXC_F_SPIXFM_MEMSECCTRL_DEC_EN_POS 0 /**< MEMSECCTRL_DEC_EN Position */ 283 #define MXC_F_SPIXFM_MEMSECCTRL_DEC_EN ((uint32_t)(0x1UL << MXC_F_SPIXFM_MEMSECCTRL_DEC_EN_POS)) /**< MEMSECCTRL_DEC_EN Mask */ 284 285 #define MXC_F_SPIXFM_MEMSECCTRL_AUTH_DIS_POS 1 /**< MEMSECCTRL_AUTH_DIS Position */ 286 #define MXC_F_SPIXFM_MEMSECCTRL_AUTH_DIS ((uint32_t)(0x1UL << MXC_F_SPIXFM_MEMSECCTRL_AUTH_DIS_POS)) /**< MEMSECCTRL_AUTH_DIS Mask */ 287 288 #define MXC_F_SPIXFM_MEMSECCTRL_CNTOPT_EN_POS 2 /**< MEMSECCTRL_CNTOPT_EN Position */ 289 #define MXC_F_SPIXFM_MEMSECCTRL_CNTOPT_EN ((uint32_t)(0x1UL << MXC_F_SPIXFM_MEMSECCTRL_CNTOPT_EN_POS)) /**< MEMSECCTRL_CNTOPT_EN Mask */ 290 291 #define MXC_F_SPIXFM_MEMSECCTRL_INTERL_DIS_POS 3 /**< MEMSECCTRL_INTERL_DIS Position */ 292 #define MXC_F_SPIXFM_MEMSECCTRL_INTERL_DIS ((uint32_t)(0x1UL << MXC_F_SPIXFM_MEMSECCTRL_INTERL_DIS_POS)) /**< MEMSECCTRL_INTERL_DIS Mask */ 293 294 #define MXC_F_SPIXFM_MEMSECCTRL_AUTHERR_FL_POS 4 /**< MEMSECCTRL_AUTHERR_FL Position */ 295 #define MXC_F_SPIXFM_MEMSECCTRL_AUTHERR_FL ((uint32_t)(0x1UL << MXC_F_SPIXFM_MEMSECCTRL_AUTHERR_FL_POS)) /**< MEMSECCTRL_AUTHERR_FL Mask */ 296 297 /**@} end of group SPIXFM_MEMSECCTRL_Register */ 298 299 /** 300 * @ingroup spixfm_registers 301 * @defgroup SPIXFM_BUSIDLE SPIXFM_BUSIDLE 302 * @brief Bus Idle 303 * @{ 304 */ 305 #define MXC_F_SPIXFM_BUSIDLE_BUSIDLE_POS 0 /**< BUSIDLE_BUSIDLE Position */ 306 #define MXC_F_SPIXFM_BUSIDLE_BUSIDLE ((uint32_t)(0xFFFFUL << MXC_F_SPIXFM_BUSIDLE_BUSIDLE_POS)) /**< BUSIDLE_BUSIDLE Mask */ 307 308 /**@} end of group SPIXFM_BUSIDLE_Register */ 309 310 /** 311 * @ingroup spixfm_registers 312 * @defgroup SPIXFM_BYPASS_MODE SPIXFM_BYPASS_MODE 313 * @brief Bypass Mode Register. 314 * @{ 315 */ 316 #define MXC_F_SPIXFM_BYPASS_MODE_EN_POS 0 /**< BYPASS_MODE_EN Position */ 317 #define MXC_F_SPIXFM_BYPASS_MODE_EN ((uint32_t)(0x1UL << MXC_F_SPIXFM_BYPASS_MODE_EN_POS)) /**< BYPASS_MODE_EN Mask */ 318 319 #define MXC_F_SPIXFM_BYPASS_MODE_FCLK_DELAY_POS 1 /**< BYPASS_MODE_FCLK_DELAY Position */ 320 #define MXC_F_SPIXFM_BYPASS_MODE_FCLK_DELAY ((uint32_t)(0x7UL << MXC_F_SPIXFM_BYPASS_MODE_FCLK_DELAY_POS)) /**< BYPASS_MODE_FCLK_DELAY Mask */ 321 #define MXC_V_SPIXFM_BYPASS_MODE_FCLK_DELAY_0_NS ((uint32_t)0x0UL) /**< BYPASS_MODE_FCLK_DELAY_0_NS Value */ 322 #define MXC_S_SPIXFM_BYPASS_MODE_FCLK_DELAY_0_NS (MXC_V_SPIXFM_BYPASS_MODE_FCLK_DELAY_0_NS << MXC_F_SPIXFM_BYPASS_MODE_FCLK_DELAY_POS) /**< BYPASS_MODE_FCLK_DELAY_0_NS Setting */ 323 #define MXC_V_SPIXFM_BYPASS_MODE_FCLK_DELAY_0P5_NS ((uint32_t)0x1UL) /**< BYPASS_MODE_FCLK_DELAY_0P5_NS Value */ 324 #define MXC_S_SPIXFM_BYPASS_MODE_FCLK_DELAY_0P5_NS (MXC_V_SPIXFM_BYPASS_MODE_FCLK_DELAY_0P5_NS << MXC_F_SPIXFM_BYPASS_MODE_FCLK_DELAY_POS) /**< BYPASS_MODE_FCLK_DELAY_0P5_NS Setting */ 325 #define MXC_V_SPIXFM_BYPASS_MODE_FCLK_DELAY_1P0_NS ((uint32_t)0x2UL) /**< BYPASS_MODE_FCLK_DELAY_1P0_NS Value */ 326 #define MXC_S_SPIXFM_BYPASS_MODE_FCLK_DELAY_1P0_NS (MXC_V_SPIXFM_BYPASS_MODE_FCLK_DELAY_1P0_NS << MXC_F_SPIXFM_BYPASS_MODE_FCLK_DELAY_POS) /**< BYPASS_MODE_FCLK_DELAY_1P0_NS Setting */ 327 #define MXC_V_SPIXFM_BYPASS_MODE_FCLK_DELAY_1P5_NS ((uint32_t)0x3UL) /**< BYPASS_MODE_FCLK_DELAY_1P5_NS Value */ 328 #define MXC_S_SPIXFM_BYPASS_MODE_FCLK_DELAY_1P5_NS (MXC_V_SPIXFM_BYPASS_MODE_FCLK_DELAY_1P5_NS << MXC_F_SPIXFM_BYPASS_MODE_FCLK_DELAY_POS) /**< BYPASS_MODE_FCLK_DELAY_1P5_NS Setting */ 329 #define MXC_V_SPIXFM_BYPASS_MODE_FCLK_DELAY_2P0_NS ((uint32_t)0x4UL) /**< BYPASS_MODE_FCLK_DELAY_2P0_NS Value */ 330 #define MXC_S_SPIXFM_BYPASS_MODE_FCLK_DELAY_2P0_NS (MXC_V_SPIXFM_BYPASS_MODE_FCLK_DELAY_2P0_NS << MXC_F_SPIXFM_BYPASS_MODE_FCLK_DELAY_POS) /**< BYPASS_MODE_FCLK_DELAY_2P0_NS Setting */ 331 #define MXC_V_SPIXFM_BYPASS_MODE_FCLK_DELAY_2P5_NS ((uint32_t)0x5UL) /**< BYPASS_MODE_FCLK_DELAY_2P5_NS Value */ 332 #define MXC_S_SPIXFM_BYPASS_MODE_FCLK_DELAY_2P5_NS (MXC_V_SPIXFM_BYPASS_MODE_FCLK_DELAY_2P5_NS << MXC_F_SPIXFM_BYPASS_MODE_FCLK_DELAY_POS) /**< BYPASS_MODE_FCLK_DELAY_2P5_NS Setting */ 333 #define MXC_V_SPIXFM_BYPASS_MODE_FCLK_DELAY_3P0_NS ((uint32_t)0x6UL) /**< BYPASS_MODE_FCLK_DELAY_3P0_NS Value */ 334 #define MXC_S_SPIXFM_BYPASS_MODE_FCLK_DELAY_3P0_NS (MXC_V_SPIXFM_BYPASS_MODE_FCLK_DELAY_3P0_NS << MXC_F_SPIXFM_BYPASS_MODE_FCLK_DELAY_POS) /**< BYPASS_MODE_FCLK_DELAY_3P0_NS Setting */ 335 #define MXC_V_SPIXFM_BYPASS_MODE_FCLK_DELAY_3P5_NS ((uint32_t)0x7UL) /**< BYPASS_MODE_FCLK_DELAY_3P5_NS Value */ 336 #define MXC_S_SPIXFM_BYPASS_MODE_FCLK_DELAY_3P5_NS (MXC_V_SPIXFM_BYPASS_MODE_FCLK_DELAY_3P5_NS << MXC_F_SPIXFM_BYPASS_MODE_FCLK_DELAY_POS) /**< BYPASS_MODE_FCLK_DELAY_3P5_NS Setting */ 337 338 #define MXC_F_SPIXFM_BYPASS_MODE_SCLK_DELAY_POS 4 /**< BYPASS_MODE_SCLK_DELAY Position */ 339 #define MXC_F_SPIXFM_BYPASS_MODE_SCLK_DELAY ((uint32_t)(0x7UL << MXC_F_SPIXFM_BYPASS_MODE_SCLK_DELAY_POS)) /**< BYPASS_MODE_SCLK_DELAY Mask */ 340 #define MXC_V_SPIXFM_BYPASS_MODE_SCLK_DELAY_0_NS ((uint32_t)0x0UL) /**< BYPASS_MODE_SCLK_DELAY_0_NS Value */ 341 #define MXC_S_SPIXFM_BYPASS_MODE_SCLK_DELAY_0_NS (MXC_V_SPIXFM_BYPASS_MODE_SCLK_DELAY_0_NS << MXC_F_SPIXFM_BYPASS_MODE_SCLK_DELAY_POS) /**< BYPASS_MODE_SCLK_DELAY_0_NS Setting */ 342 #define MXC_V_SPIXFM_BYPASS_MODE_SCLK_DELAY_0P5_NS ((uint32_t)0x1UL) /**< BYPASS_MODE_SCLK_DELAY_0P5_NS Value */ 343 #define MXC_S_SPIXFM_BYPASS_MODE_SCLK_DELAY_0P5_NS (MXC_V_SPIXFM_BYPASS_MODE_SCLK_DELAY_0P5_NS << MXC_F_SPIXFM_BYPASS_MODE_SCLK_DELAY_POS) /**< BYPASS_MODE_SCLK_DELAY_0P5_NS Setting */ 344 #define MXC_V_SPIXFM_BYPASS_MODE_SCLK_DELAY_1P0_NS ((uint32_t)0x2UL) /**< BYPASS_MODE_SCLK_DELAY_1P0_NS Value */ 345 #define MXC_S_SPIXFM_BYPASS_MODE_SCLK_DELAY_1P0_NS (MXC_V_SPIXFM_BYPASS_MODE_SCLK_DELAY_1P0_NS << MXC_F_SPIXFM_BYPASS_MODE_SCLK_DELAY_POS) /**< BYPASS_MODE_SCLK_DELAY_1P0_NS Setting */ 346 #define MXC_V_SPIXFM_BYPASS_MODE_SCLK_DELAY_1P5_NS ((uint32_t)0x3UL) /**< BYPASS_MODE_SCLK_DELAY_1P5_NS Value */ 347 #define MXC_S_SPIXFM_BYPASS_MODE_SCLK_DELAY_1P5_NS (MXC_V_SPIXFM_BYPASS_MODE_SCLK_DELAY_1P5_NS << MXC_F_SPIXFM_BYPASS_MODE_SCLK_DELAY_POS) /**< BYPASS_MODE_SCLK_DELAY_1P5_NS Setting */ 348 #define MXC_V_SPIXFM_BYPASS_MODE_SCLK_DELAY_2P0_NS ((uint32_t)0x4UL) /**< BYPASS_MODE_SCLK_DELAY_2P0_NS Value */ 349 #define MXC_S_SPIXFM_BYPASS_MODE_SCLK_DELAY_2P0_NS (MXC_V_SPIXFM_BYPASS_MODE_SCLK_DELAY_2P0_NS << MXC_F_SPIXFM_BYPASS_MODE_SCLK_DELAY_POS) /**< BYPASS_MODE_SCLK_DELAY_2P0_NS Setting */ 350 #define MXC_V_SPIXFM_BYPASS_MODE_SCLK_DELAY_2P5_NS ((uint32_t)0x5UL) /**< BYPASS_MODE_SCLK_DELAY_2P5_NS Value */ 351 #define MXC_S_SPIXFM_BYPASS_MODE_SCLK_DELAY_2P5_NS (MXC_V_SPIXFM_BYPASS_MODE_SCLK_DELAY_2P5_NS << MXC_F_SPIXFM_BYPASS_MODE_SCLK_DELAY_POS) /**< BYPASS_MODE_SCLK_DELAY_2P5_NS Setting */ 352 #define MXC_V_SPIXFM_BYPASS_MODE_SCLK_DELAY_3P0_NS ((uint32_t)0x6UL) /**< BYPASS_MODE_SCLK_DELAY_3P0_NS Value */ 353 #define MXC_S_SPIXFM_BYPASS_MODE_SCLK_DELAY_3P0_NS (MXC_V_SPIXFM_BYPASS_MODE_SCLK_DELAY_3P0_NS << MXC_F_SPIXFM_BYPASS_MODE_SCLK_DELAY_POS) /**< BYPASS_MODE_SCLK_DELAY_3P0_NS Setting */ 354 #define MXC_V_SPIXFM_BYPASS_MODE_SCLK_DELAY_3P5_NS ((uint32_t)0x7UL) /**< BYPASS_MODE_SCLK_DELAY_3P5_NS Value */ 355 #define MXC_S_SPIXFM_BYPASS_MODE_SCLK_DELAY_3P5_NS (MXC_V_SPIXFM_BYPASS_MODE_SCLK_DELAY_3P5_NS << MXC_F_SPIXFM_BYPASS_MODE_SCLK_DELAY_POS) /**< BYPASS_MODE_SCLK_DELAY_3P5_NS Setting */ 356 357 /**@} end of group SPIXFM_BYPASS_MODE_Register */ 358 359 #ifdef __cplusplus 360 } 361 #endif 362 363 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SPIXFM_REGS_H_ 364
