1 /** 2 * @file spixfc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPIXFC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup spixfc_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SPIXFC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SPIXFC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup spixfc 67 * @defgroup spixfc_registers SPIXFC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SPIXFC Peripheral Module. 69 * @details SPI XiP Flash Configuration Controller 70 */ 71 72 /** 73 * @ingroup spixfc_registers 74 * Structure type to access the SPIXFC Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl0; /**< <tt>\b 0x00:</tt> SPIXFC CTRL0 Register */ 78 __IO uint32_t sspol; /**< <tt>\b 0x04:</tt> SPIXFC SSPOL Register */ 79 __IO uint32_t ctrl1; /**< <tt>\b 0x08:</tt> SPIXFC CTRL1 Register */ 80 __IO uint32_t ctrl2; /**< <tt>\b 0x0C:</tt> SPIXFC CTRL2 Register */ 81 __IO uint32_t ctrl3; /**< <tt>\b 0x10:</tt> SPIXFC CTRL3 Register */ 82 __IO uint32_t intfl; /**< <tt>\b 0x14:</tt> SPIXFC INTFL Register */ 83 __IO uint32_t inten; /**< <tt>\b 0x18:</tt> SPIXFC INTEN Register */ 84 __IO uint32_t header; /**< <tt>\b 0x1C:</tt> SPIXFC HEADER Register */ 85 __IO uint32_t autoctrl; /**< <tt>\b 0x20:</tt> SPIXFC AUTOCTRL Register */ 86 __IO uint32_t autocmd; /**< <tt>\b 0x24:</tt> SPIXFC AUTOCMD Register */ 87 } mxc_spixfc_regs_t; 88 89 /* Register offsets for module SPIXFC */ 90 /** 91 * @ingroup spixfc_registers 92 * @defgroup SPIXFC_Register_Offsets Register Offsets 93 * @brief SPIXFC Peripheral Register Offsets from the SPIXFC Base Peripheral Address. 94 * @{ 95 */ 96 #define MXC_R_SPIXFC_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from SPIXFC Base Address: <tt> 0x0000</tt> */ 97 #define MXC_R_SPIXFC_SSPOL ((uint32_t)0x00000004UL) /**< Offset from SPIXFC Base Address: <tt> 0x0004</tt> */ 98 #define MXC_R_SPIXFC_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPIXFC Base Address: <tt> 0x0008</tt> */ 99 #define MXC_R_SPIXFC_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPIXFC Base Address: <tt> 0x000C</tt> */ 100 #define MXC_R_SPIXFC_CTRL3 ((uint32_t)0x00000010UL) /**< Offset from SPIXFC Base Address: <tt> 0x0010</tt> */ 101 #define MXC_R_SPIXFC_INTFL ((uint32_t)0x00000014UL) /**< Offset from SPIXFC Base Address: <tt> 0x0014</tt> */ 102 #define MXC_R_SPIXFC_INTEN ((uint32_t)0x00000018UL) /**< Offset from SPIXFC Base Address: <tt> 0x0018</tt> */ 103 #define MXC_R_SPIXFC_HEADER ((uint32_t)0x0000001CUL) /**< Offset from SPIXFC Base Address: <tt> 0x001C</tt> */ 104 #define MXC_R_SPIXFC_AUTOCTRL ((uint32_t)0x00000020UL) /**< Offset from SPIXFC Base Address: <tt> 0x0020</tt> */ 105 #define MXC_R_SPIXFC_AUTOCMD ((uint32_t)0x00000024UL) /**< Offset from SPIXFC Base Address: <tt> 0x0024</tt> */ 106 /**@} end of group spixfc_registers */ 107 108 /** 109 * @ingroup spixfc_registers 110 * @defgroup SPIXFC_CTRL0 SPIXFC_CTRL0 111 * @brief Control Register. 112 * @{ 113 */ 114 #define MXC_F_SPIXFC_CTRL0_SSEL_POS 0 /**< CTRL0_SSEL Position */ 115 #define MXC_F_SPIXFC_CTRL0_SSEL ((uint32_t)(0x7UL << MXC_F_SPIXFC_CTRL0_SSEL_POS)) /**< CTRL0_SSEL Mask */ 116 #define MXC_V_SPIXFC_CTRL0_SSEL_SLAVE_0 ((uint32_t)0x0UL) /**< CTRL0_SSEL_SLAVE_0 Value */ 117 #define MXC_S_SPIXFC_CTRL0_SSEL_SLAVE_0 (MXC_V_SPIXFC_CTRL0_SSEL_SLAVE_0 << MXC_F_SPIXFC_CTRL0_SSEL_POS) /**< CTRL0_SSEL_SLAVE_0 Setting */ 118 #define MXC_V_SPIXFC_CTRL0_SSEL_SLAVE_1 ((uint32_t)0x1UL) /**< CTRL0_SSEL_SLAVE_1 Value */ 119 #define MXC_S_SPIXFC_CTRL0_SSEL_SLAVE_1 (MXC_V_SPIXFC_CTRL0_SSEL_SLAVE_1 << MXC_F_SPIXFC_CTRL0_SSEL_POS) /**< CTRL0_SSEL_SLAVE_1 Setting */ 120 121 #define MXC_F_SPIXFC_CTRL0_THREE_WIRE_POS 3 /**< CTRL0_THREE_WIRE Position */ 122 #define MXC_F_SPIXFC_CTRL0_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL0_THREE_WIRE_POS)) /**< CTRL0_THREE_WIRE Mask */ 123 124 #define MXC_F_SPIXFC_CTRL0_MODE_POS 4 /**< CTRL0_MODE Position */ 125 #define MXC_F_SPIXFC_CTRL0_MODE ((uint32_t)(0x3UL << MXC_F_SPIXFC_CTRL0_MODE_POS)) /**< CTRL0_MODE Mask */ 126 #define MXC_V_SPIXFC_CTRL0_MODE_SPI_MODE_0 ((uint32_t)0x0UL) /**< CTRL0_MODE_SPI_MODE_0 Value */ 127 #define MXC_S_SPIXFC_CTRL0_MODE_SPI_MODE_0 (MXC_V_SPIXFC_CTRL0_MODE_SPI_MODE_0 << MXC_F_SPIXFC_CTRL0_MODE_POS) /**< CTRL0_MODE_SPI_MODE_0 Setting */ 128 #define MXC_V_SPIXFC_CTRL0_MODE_SPI_MODE_3 ((uint32_t)0x3UL) /**< CTRL0_MODE_SPI_MODE_3 Value */ 129 #define MXC_S_SPIXFC_CTRL0_MODE_SPI_MODE_3 (MXC_V_SPIXFC_CTRL0_MODE_SPI_MODE_3 << MXC_F_SPIXFC_CTRL0_MODE_POS) /**< CTRL0_MODE_SPI_MODE_3 Setting */ 130 131 #define MXC_F_SPIXFC_CTRL0_PGSZ_POS 6 /**< CTRL0_PGSZ Position */ 132 #define MXC_F_SPIXFC_CTRL0_PGSZ ((uint32_t)(0x3UL << MXC_F_SPIXFC_CTRL0_PGSZ_POS)) /**< CTRL0_PGSZ Mask */ 133 #define MXC_V_SPIXFC_CTRL0_PGSZ_4_BYTES ((uint32_t)0x0UL) /**< CTRL0_PGSZ_4_BYTES Value */ 134 #define MXC_S_SPIXFC_CTRL0_PGSZ_4_BYTES (MXC_V_SPIXFC_CTRL0_PGSZ_4_BYTES << MXC_F_SPIXFC_CTRL0_PGSZ_POS) /**< CTRL0_PGSZ_4_BYTES Setting */ 135 #define MXC_V_SPIXFC_CTRL0_PGSZ_8_BYTES ((uint32_t)0x1UL) /**< CTRL0_PGSZ_8_BYTES Value */ 136 #define MXC_S_SPIXFC_CTRL0_PGSZ_8_BYTES (MXC_V_SPIXFC_CTRL0_PGSZ_8_BYTES << MXC_F_SPIXFC_CTRL0_PGSZ_POS) /**< CTRL0_PGSZ_8_BYTES Setting */ 137 #define MXC_V_SPIXFC_CTRL0_PGSZ_16_BYTES ((uint32_t)0x2UL) /**< CTRL0_PGSZ_16_BYTES Value */ 138 #define MXC_S_SPIXFC_CTRL0_PGSZ_16_BYTES (MXC_V_SPIXFC_CTRL0_PGSZ_16_BYTES << MXC_F_SPIXFC_CTRL0_PGSZ_POS) /**< CTRL0_PGSZ_16_BYTES Setting */ 139 #define MXC_V_SPIXFC_CTRL0_PGSZ_32_BYTES ((uint32_t)0x3UL) /**< CTRL0_PGSZ_32_BYTES Value */ 140 #define MXC_S_SPIXFC_CTRL0_PGSZ_32_BYTES (MXC_V_SPIXFC_CTRL0_PGSZ_32_BYTES << MXC_F_SPIXFC_CTRL0_PGSZ_POS) /**< CTRL0_PGSZ_32_BYTES Setting */ 141 142 #define MXC_F_SPIXFC_CTRL0_HICLK_POS 8 /**< CTRL0_HICLK Position */ 143 #define MXC_F_SPIXFC_CTRL0_HICLK ((uint32_t)(0xFUL << MXC_F_SPIXFC_CTRL0_HICLK_POS)) /**< CTRL0_HICLK Mask */ 144 #define MXC_V_SPIXFC_CTRL0_HICLK_16_SCLK ((uint32_t)0x0UL) /**< CTRL0_HICLK_16_SCLK Value */ 145 #define MXC_S_SPIXFC_CTRL0_HICLK_16_SCLK (MXC_V_SPIXFC_CTRL0_HICLK_16_SCLK << MXC_F_SPIXFC_CTRL0_HICLK_POS) /**< CTRL0_HICLK_16_SCLK Setting */ 146 147 #define MXC_F_SPIXFC_CTRL0_LOCLK_POS 12 /**< CTRL0_LOCLK Position */ 148 #define MXC_F_SPIXFC_CTRL0_LOCLK ((uint32_t)(0xFUL << MXC_F_SPIXFC_CTRL0_LOCLK_POS)) /**< CTRL0_LOCLK Mask */ 149 #define MXC_V_SPIXFC_CTRL0_LOCLK_16_SCLK ((uint32_t)0x0UL) /**< CTRL0_LOCLK_16_SCLK Value */ 150 #define MXC_S_SPIXFC_CTRL0_LOCLK_16_SCLK (MXC_V_SPIXFC_CTRL0_LOCLK_16_SCLK << MXC_F_SPIXFC_CTRL0_LOCLK_POS) /**< CTRL0_LOCLK_16_SCLK Setting */ 151 152 #define MXC_F_SPIXFC_CTRL0_SSACT_POS 16 /**< CTRL0_SSACT Position */ 153 #define MXC_F_SPIXFC_CTRL0_SSACT ((uint32_t)(0x3UL << MXC_F_SPIXFC_CTRL0_SSACT_POS)) /**< CTRL0_SSACT Mask */ 154 #define MXC_V_SPIXFC_CTRL0_SSACT_0_CLKS ((uint32_t)0x0UL) /**< CTRL0_SSACT_0_CLKS Value */ 155 #define MXC_S_SPIXFC_CTRL0_SSACT_0_CLKS (MXC_V_SPIXFC_CTRL0_SSACT_0_CLKS << MXC_F_SPIXFC_CTRL0_SSACT_POS) /**< CTRL0_SSACT_0_CLKS Setting */ 156 #define MXC_V_SPIXFC_CTRL0_SSACT_2_CLKS ((uint32_t)0x1UL) /**< CTRL0_SSACT_2_CLKS Value */ 157 #define MXC_S_SPIXFC_CTRL0_SSACT_2_CLKS (MXC_V_SPIXFC_CTRL0_SSACT_2_CLKS << MXC_F_SPIXFC_CTRL0_SSACT_POS) /**< CTRL0_SSACT_2_CLKS Setting */ 158 #define MXC_V_SPIXFC_CTRL0_SSACT_4_CLKS ((uint32_t)0x2UL) /**< CTRL0_SSACT_4_CLKS Value */ 159 #define MXC_S_SPIXFC_CTRL0_SSACT_4_CLKS (MXC_V_SPIXFC_CTRL0_SSACT_4_CLKS << MXC_F_SPIXFC_CTRL0_SSACT_POS) /**< CTRL0_SSACT_4_CLKS Setting */ 160 #define MXC_V_SPIXFC_CTRL0_SSACT_8_CLKS ((uint32_t)0x3UL) /**< CTRL0_SSACT_8_CLKS Value */ 161 #define MXC_S_SPIXFC_CTRL0_SSACT_8_CLKS (MXC_V_SPIXFC_CTRL0_SSACT_8_CLKS << MXC_F_SPIXFC_CTRL0_SSACT_POS) /**< CTRL0_SSACT_8_CLKS Setting */ 162 163 #define MXC_F_SPIXFC_CTRL0_SSINACT_POS 18 /**< CTRL0_SSINACT Position */ 164 #define MXC_F_SPIXFC_CTRL0_SSINACT ((uint32_t)(0x3UL << MXC_F_SPIXFC_CTRL0_SSINACT_POS)) /**< CTRL0_SSINACT Mask */ 165 #define MXC_V_SPIXFC_CTRL0_SSINACT_4_CLKS ((uint32_t)0x0UL) /**< CTRL0_SSINACT_4_CLKS Value */ 166 #define MXC_S_SPIXFC_CTRL0_SSINACT_4_CLKS (MXC_V_SPIXFC_CTRL0_SSINACT_4_CLKS << MXC_F_SPIXFC_CTRL0_SSINACT_POS) /**< CTRL0_SSINACT_4_CLKS Setting */ 167 #define MXC_V_SPIXFC_CTRL0_SSINACT_6_CLKS ((uint32_t)0x1UL) /**< CTRL0_SSINACT_6_CLKS Value */ 168 #define MXC_S_SPIXFC_CTRL0_SSINACT_6_CLKS (MXC_V_SPIXFC_CTRL0_SSINACT_6_CLKS << MXC_F_SPIXFC_CTRL0_SSINACT_POS) /**< CTRL0_SSINACT_6_CLKS Setting */ 169 #define MXC_V_SPIXFC_CTRL0_SSINACT_8_CLKS ((uint32_t)0x2UL) /**< CTRL0_SSINACT_8_CLKS Value */ 170 #define MXC_S_SPIXFC_CTRL0_SSINACT_8_CLKS (MXC_V_SPIXFC_CTRL0_SSINACT_8_CLKS << MXC_F_SPIXFC_CTRL0_SSINACT_POS) /**< CTRL0_SSINACT_8_CLKS Setting */ 171 #define MXC_V_SPIXFC_CTRL0_SSINACT_12_CLKS ((uint32_t)0x3UL) /**< CTRL0_SSINACT_12_CLKS Value */ 172 #define MXC_S_SPIXFC_CTRL0_SSINACT_12_CLKS (MXC_V_SPIXFC_CTRL0_SSINACT_12_CLKS << MXC_F_SPIXFC_CTRL0_SSINACT_POS) /**< CTRL0_SSINACT_12_CLKS Setting */ 173 174 #define MXC_F_SPIXFC_CTRL0_IOSMPL_POS 20 /**< CTRL0_IOSMPL Position */ 175 #define MXC_F_SPIXFC_CTRL0_IOSMPL ((uint32_t)(0xFUL << MXC_F_SPIXFC_CTRL0_IOSMPL_POS)) /**< CTRL0_IOSMPL Mask */ 176 177 /**@} end of group SPIXFC_CTRL0_Register */ 178 179 /** 180 * @ingroup spixfc_registers 181 * @defgroup SPIXFC_SSPOL SPIXFC_SSPOL 182 * @brief SPIX Controller Slave Select Polarity Register. 183 * @{ 184 */ 185 #define MXC_F_SPIXFC_SSPOL_SSPOL_POS 0 /**< SSPOL_SSPOL Position */ 186 #define MXC_F_SPIXFC_SSPOL_SSPOL ((uint32_t)(0x1UL << MXC_F_SPIXFC_SSPOL_SSPOL_POS)) /**< SSPOL_SSPOL Mask */ 187 188 #define MXC_F_SPIXFC_SSPOL_FCPOL_POS 8 /**< SSPOL_FCPOL Position */ 189 #define MXC_F_SPIXFC_SSPOL_FCPOL ((uint32_t)(0x1UL << MXC_F_SPIXFC_SSPOL_FCPOL_POS)) /**< SSPOL_FCPOL Mask */ 190 191 /**@} end of group SPIXFC_SSPOL_Register */ 192 193 /** 194 * @ingroup spixfc_registers 195 * @defgroup SPIXFC_CTRL1 SPIXFC_CTRL1 196 * @brief SPIX Controller General Controller Register. 197 * @{ 198 */ 199 #define MXC_F_SPIXFC_CTRL1_EN_POS 0 /**< CTRL1_EN Position */ 200 #define MXC_F_SPIXFC_CTRL1_EN ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_EN_POS)) /**< CTRL1_EN Mask */ 201 202 #define MXC_F_SPIXFC_CTRL1_TX_FIFO_EN_POS 1 /**< CTRL1_TX_FIFO_EN Position */ 203 #define MXC_F_SPIXFC_CTRL1_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_TX_FIFO_EN_POS)) /**< CTRL1_TX_FIFO_EN Mask */ 204 205 #define MXC_F_SPIXFC_CTRL1_RX_FIFO_EN_POS 2 /**< CTRL1_RX_FIFO_EN Position */ 206 #define MXC_F_SPIXFC_CTRL1_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_RX_FIFO_EN_POS)) /**< CTRL1_RX_FIFO_EN Mask */ 207 208 #define MXC_F_SPIXFC_CTRL1_BB_EN_POS 3 /**< CTRL1_BB_EN Position */ 209 #define MXC_F_SPIXFC_CTRL1_BB_EN ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_BB_EN_POS)) /**< CTRL1_BB_EN Mask */ 210 211 #define MXC_F_SPIXFC_CTRL1_SSDR_POS 4 /**< CTRL1_SSDR Position */ 212 #define MXC_F_SPIXFC_CTRL1_SSDR ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_SSDR_POS)) /**< CTRL1_SSDR Mask */ 213 214 #define MXC_F_SPIXFC_CTRL1_FCDR_POS 5 /**< CTRL1_FCDR Position */ 215 #define MXC_F_SPIXFC_CTRL1_FCDR ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_FCDR_POS)) /**< CTRL1_FCDR Mask */ 216 217 #define MXC_F_SPIXFC_CTRL1_SCLKDR_POS 6 /**< CTRL1_SCLKDR Position */ 218 #define MXC_F_SPIXFC_CTRL1_SCLKDR ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_SCLKDR_POS)) /**< CTRL1_SCLKDR Mask */ 219 220 #define MXC_F_SPIXFC_CTRL1_SDIO_DATA_IN_POS 8 /**< CTRL1_SDIO_DATA_IN Position */ 221 #define MXC_F_SPIXFC_CTRL1_SDIO_DATA_IN ((uint32_t)(0xFUL << MXC_F_SPIXFC_CTRL1_SDIO_DATA_IN_POS)) /**< CTRL1_SDIO_DATA_IN Mask */ 222 #define MXC_V_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO0 ((uint32_t)0x0UL) /**< CTRL1_SDIO_DATA_IN_SDIO0 Value */ 223 #define MXC_S_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO0 (MXC_V_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO0 << MXC_F_SPIXFC_CTRL1_SDIO_DATA_IN_POS) /**< CTRL1_SDIO_DATA_IN_SDIO0 Setting */ 224 #define MXC_V_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO1 ((uint32_t)0x1UL) /**< CTRL1_SDIO_DATA_IN_SDIO1 Value */ 225 #define MXC_S_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO1 (MXC_V_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO1 << MXC_F_SPIXFC_CTRL1_SDIO_DATA_IN_POS) /**< CTRL1_SDIO_DATA_IN_SDIO1 Setting */ 226 #define MXC_V_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO2 ((uint32_t)0x2UL) /**< CTRL1_SDIO_DATA_IN_SDIO2 Value */ 227 #define MXC_S_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO2 (MXC_V_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO2 << MXC_F_SPIXFC_CTRL1_SDIO_DATA_IN_POS) /**< CTRL1_SDIO_DATA_IN_SDIO2 Setting */ 228 #define MXC_V_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO3 ((uint32_t)0x3UL) /**< CTRL1_SDIO_DATA_IN_SDIO3 Value */ 229 #define MXC_S_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO3 (MXC_V_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO3 << MXC_F_SPIXFC_CTRL1_SDIO_DATA_IN_POS) /**< CTRL1_SDIO_DATA_IN_SDIO3 Setting */ 230 231 #define MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_POS 12 /**< CTRL1_BB_DATA_OUT Position */ 232 #define MXC_F_SPIXFC_CTRL1_BB_DATA_OUT ((uint32_t)(0xFUL << MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_POS)) /**< CTRL1_BB_DATA_OUT Mask */ 233 #define MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_SDIO0 ((uint32_t)0x0UL) /**< CTRL1_BB_DATA_OUT_SDIO0 Value */ 234 #define MXC_S_SPIXFC_CTRL1_BB_DATA_OUT_SDIO0 (MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_SDIO0 << MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_POS) /**< CTRL1_BB_DATA_OUT_SDIO0 Setting */ 235 #define MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_SDIO1 ((uint32_t)0x1UL) /**< CTRL1_BB_DATA_OUT_SDIO1 Value */ 236 #define MXC_S_SPIXFC_CTRL1_BB_DATA_OUT_SDIO1 (MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_SDIO1 << MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_POS) /**< CTRL1_BB_DATA_OUT_SDIO1 Setting */ 237 #define MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_SDIO2 ((uint32_t)0x2UL) /**< CTRL1_BB_DATA_OUT_SDIO2 Value */ 238 #define MXC_S_SPIXFC_CTRL1_BB_DATA_OUT_SDIO2 (MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_SDIO2 << MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_POS) /**< CTRL1_BB_DATA_OUT_SDIO2 Setting */ 239 #define MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_SDIO3 ((uint32_t)0x3UL) /**< CTRL1_BB_DATA_OUT_SDIO3 Value */ 240 #define MXC_S_SPIXFC_CTRL1_BB_DATA_OUT_SDIO3 (MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_SDIO3 << MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_POS) /**< CTRL1_BB_DATA_OUT_SDIO3 Setting */ 241 242 #define MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_EN_POS 16 /**< CTRL1_BB_DATA_OUT_EN Position */ 243 #define MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_EN ((uint32_t)(0xFUL << MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_EN_POS)) /**< CTRL1_BB_DATA_OUT_EN Mask */ 244 #define MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO0 ((uint32_t)0x0UL) /**< CTRL1_BB_DATA_OUT_EN_SDIO0 Value */ 245 #define MXC_S_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO0 (MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO0 << MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_EN_POS) /**< CTRL1_BB_DATA_OUT_EN_SDIO0 Setting */ 246 #define MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO1 ((uint32_t)0x1UL) /**< CTRL1_BB_DATA_OUT_EN_SDIO1 Value */ 247 #define MXC_S_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO1 (MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO1 << MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_EN_POS) /**< CTRL1_BB_DATA_OUT_EN_SDIO1 Setting */ 248 #define MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO2 ((uint32_t)0x2UL) /**< CTRL1_BB_DATA_OUT_EN_SDIO2 Value */ 249 #define MXC_S_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO2 (MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO2 << MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_EN_POS) /**< CTRL1_BB_DATA_OUT_EN_SDIO2 Setting */ 250 #define MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO3 ((uint32_t)0x3UL) /**< CTRL1_BB_DATA_OUT_EN_SDIO3 Value */ 251 #define MXC_S_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO3 (MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO3 << MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_EN_POS) /**< CTRL1_BB_DATA_OUT_EN_SDIO3 Setting */ 252 253 #define MXC_F_SPIXFC_CTRL1_SIMPLE_EN_POS 20 /**< CTRL1_SIMPLE_EN Position */ 254 #define MXC_F_SPIXFC_CTRL1_SIMPLE_EN ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_SIMPLE_EN_POS)) /**< CTRL1_SIMPLE_EN Mask */ 255 256 #define MXC_F_SPIXFC_CTRL1_SIMPLE_RX_POS 21 /**< CTRL1_SIMPLE_RX Position */ 257 #define MXC_F_SPIXFC_CTRL1_SIMPLE_RX ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_SIMPLE_RX_POS)) /**< CTRL1_SIMPLE_RX Mask */ 258 259 #define MXC_F_SPIXFC_CTRL1_SIMPLE_SS_POS 22 /**< CTRL1_SIMPLE_SS Position */ 260 #define MXC_F_SPIXFC_CTRL1_SIMPLE_SS ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_SIMPLE_SS_POS)) /**< CTRL1_SIMPLE_SS Mask */ 261 262 #define MXC_F_SPIXFC_CTRL1_SCLK_FB_POS 24 /**< CTRL1_SCLK_FB Position */ 263 #define MXC_F_SPIXFC_CTRL1_SCLK_FB ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_SCLK_FB_POS)) /**< CTRL1_SCLK_FB Mask */ 264 265 #define MXC_F_SPIXFC_CTRL1_SCLK_FB_INV_POS 25 /**< CTRL1_SCLK_FB_INV Position */ 266 #define MXC_F_SPIXFC_CTRL1_SCLK_FB_INV ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_SCLK_FB_INV_POS)) /**< CTRL1_SCLK_FB_INV Mask */ 267 268 /**@} end of group SPIXFC_CTRL1_Register */ 269 270 /** 271 * @ingroup spixfc_registers 272 * @defgroup SPIXFC_CTRL2 SPIXFC_CTRL2 273 * @brief SPIX Controller FIFO Control and Status Register. 274 * @{ 275 */ 276 #define MXC_F_SPIXFC_CTRL2_TX_AE_LVL_POS 0 /**< CTRL2_TX_AE_LVL Position */ 277 #define MXC_F_SPIXFC_CTRL2_TX_AE_LVL ((uint32_t)(0xFUL << MXC_F_SPIXFC_CTRL2_TX_AE_LVL_POS)) /**< CTRL2_TX_AE_LVL Mask */ 278 279 #define MXC_F_SPIXFC_CTRL2_TX_CNT_POS 8 /**< CTRL2_TX_CNT Position */ 280 #define MXC_F_SPIXFC_CTRL2_TX_CNT ((uint32_t)(0x1FUL << MXC_F_SPIXFC_CTRL2_TX_CNT_POS)) /**< CTRL2_TX_CNT Mask */ 281 282 #define MXC_F_SPIXFC_CTRL2_RX_AF_LVL_POS 16 /**< CTRL2_RX_AF_LVL Position */ 283 #define MXC_F_SPIXFC_CTRL2_RX_AF_LVL ((uint32_t)(0x1FUL << MXC_F_SPIXFC_CTRL2_RX_AF_LVL_POS)) /**< CTRL2_RX_AF_LVL Mask */ 284 285 #define MXC_F_SPIXFC_CTRL2_RX_CNT_POS 24 /**< CTRL2_RX_CNT Position */ 286 #define MXC_F_SPIXFC_CTRL2_RX_CNT ((uint32_t)(0x3FUL << MXC_F_SPIXFC_CTRL2_RX_CNT_POS)) /**< CTRL2_RX_CNT Mask */ 287 288 /**@} end of group SPIXFC_CTRL2_Register */ 289 290 /** 291 * @ingroup spixfc_registers 292 * @defgroup SPIXFC_CTRL3 SPIXFC_CTRL3 293 * @brief SPIX Controller Special Control Register. 294 * @{ 295 */ 296 #define MXC_F_SPIXFC_CTRL3_SAMPLE_POS 0 /**< CTRL3_SAMPLE Position */ 297 #define MXC_F_SPIXFC_CTRL3_SAMPLE ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL3_SAMPLE_POS)) /**< CTRL3_SAMPLE Mask */ 298 299 #define MXC_F_SPIXFC_CTRL3_MISO_FC_EN_POS 1 /**< CTRL3_MISO_FC_EN Position */ 300 #define MXC_F_SPIXFC_CTRL3_MISO_FC_EN ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL3_MISO_FC_EN_POS)) /**< CTRL3_MISO_FC_EN Mask */ 301 302 #define MXC_F_SPIXFC_CTRL3_SDIO_OUT_VAL_POS 4 /**< CTRL3_SDIO_OUT_VAL Position */ 303 #define MXC_F_SPIXFC_CTRL3_SDIO_OUT_VAL ((uint32_t)(0xFUL << MXC_F_SPIXFC_CTRL3_SDIO_OUT_VAL_POS)) /**< CTRL3_SDIO_OUT_VAL Mask */ 304 305 #define MXC_F_SPIXFC_CTRL3_SDIO_OUT_EN_POS 8 /**< CTRL3_SDIO_OUT_EN Position */ 306 #define MXC_F_SPIXFC_CTRL3_SDIO_OUT_EN ((uint32_t)(0xFUL << MXC_F_SPIXFC_CTRL3_SDIO_OUT_EN_POS)) /**< CTRL3_SDIO_OUT_EN Mask */ 307 308 #define MXC_F_SPIXFC_CTRL3_SCLKINH3_POS 16 /**< CTRL3_SCLKINH3 Position */ 309 #define MXC_F_SPIXFC_CTRL3_SCLKINH3 ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL3_SCLKINH3_POS)) /**< CTRL3_SCLKINH3 Mask */ 310 311 /**@} end of group SPIXFC_CTRL3_Register */ 312 313 /** 314 * @ingroup spixfc_registers 315 * @defgroup SPIXFC_INTFL SPIXFC_INTFL 316 * @brief SPIX Controller Interrupt Status Register. 317 * @{ 318 */ 319 #define MXC_F_SPIXFC_INTFL_TX_STALLED_POS 0 /**< INTFL_TX_STALLED Position */ 320 #define MXC_F_SPIXFC_INTFL_TX_STALLED ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTFL_TX_STALLED_POS)) /**< INTFL_TX_STALLED Mask */ 321 322 #define MXC_F_SPIXFC_INTFL_RX_STALLED_POS 1 /**< INTFL_RX_STALLED Position */ 323 #define MXC_F_SPIXFC_INTFL_RX_STALLED ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTFL_RX_STALLED_POS)) /**< INTFL_RX_STALLED Mask */ 324 325 #define MXC_F_SPIXFC_INTFL_TX_RDY_POS 2 /**< INTFL_TX_RDY Position */ 326 #define MXC_F_SPIXFC_INTFL_TX_RDY ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTFL_TX_RDY_POS)) /**< INTFL_TX_RDY Mask */ 327 328 #define MXC_F_SPIXFC_INTFL_RX_DONE_POS 3 /**< INTFL_RX_DONE Position */ 329 #define MXC_F_SPIXFC_INTFL_RX_DONE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTFL_RX_DONE_POS)) /**< INTFL_RX_DONE Mask */ 330 331 #define MXC_F_SPIXFC_INTFL_TX_AE_POS 4 /**< INTFL_TX_AE Position */ 332 #define MXC_F_SPIXFC_INTFL_TX_AE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTFL_TX_AE_POS)) /**< INTFL_TX_AE Mask */ 333 334 #define MXC_F_SPIXFC_INTFL_RX_AF_POS 5 /**< INTFL_RX_AF Position */ 335 #define MXC_F_SPIXFC_INTFL_RX_AF ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTFL_RX_AF_POS)) /**< INTFL_RX_AF Mask */ 336 337 /**@} end of group SPIXFC_INTFL_Register */ 338 339 /** 340 * @ingroup spixfc_registers 341 * @defgroup SPIXFC_INTEN SPIXFC_INTEN 342 * @brief SPIX Controller Interrupt Enable Register. 343 * @{ 344 */ 345 #define MXC_F_SPIXFC_INTEN_TX_STALLED_POS 0 /**< INTEN_TX_STALLED Position */ 346 #define MXC_F_SPIXFC_INTEN_TX_STALLED ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTEN_TX_STALLED_POS)) /**< INTEN_TX_STALLED Mask */ 347 348 #define MXC_F_SPIXFC_INTEN_RX_STALLED_POS 1 /**< INTEN_RX_STALLED Position */ 349 #define MXC_F_SPIXFC_INTEN_RX_STALLED ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTEN_RX_STALLED_POS)) /**< INTEN_RX_STALLED Mask */ 350 351 #define MXC_F_SPIXFC_INTEN_TX_RDY_POS 2 /**< INTEN_TX_RDY Position */ 352 #define MXC_F_SPIXFC_INTEN_TX_RDY ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTEN_TX_RDY_POS)) /**< INTEN_TX_RDY Mask */ 353 354 #define MXC_F_SPIXFC_INTEN_RX_DONE_POS 3 /**< INTEN_RX_DONE Position */ 355 #define MXC_F_SPIXFC_INTEN_RX_DONE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTEN_RX_DONE_POS)) /**< INTEN_RX_DONE Mask */ 356 357 #define MXC_F_SPIXFC_INTEN_TX_AE_POS 4 /**< INTEN_TX_AE Position */ 358 #define MXC_F_SPIXFC_INTEN_TX_AE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTEN_TX_AE_POS)) /**< INTEN_TX_AE Mask */ 359 360 #define MXC_F_SPIXFC_INTEN_RX_AF_POS 5 /**< INTEN_RX_AF Position */ 361 #define MXC_F_SPIXFC_INTEN_RX_AF ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTEN_RX_AF_POS)) /**< INTEN_RX_AF Mask */ 362 363 /**@} end of group SPIXFC_INTEN_Register */ 364 365 /** 366 * @ingroup spixfc_registers 367 * @defgroup SPIXFC_HEADER SPIXFC_HEADER 368 * @brief Simple Header 369 * @{ 370 */ 371 #define MXC_F_SPIXFC_HEADER_TX_BIDIR_POS 0 /**< HEADER_TX_BIDIR Position */ 372 #define MXC_F_SPIXFC_HEADER_TX_BIDIR ((uint32_t)(0x3FFFUL << MXC_F_SPIXFC_HEADER_TX_BIDIR_POS)) /**< HEADER_TX_BIDIR Mask */ 373 374 #define MXC_F_SPIXFC_HEADER_RX_ONLY_POS 16 /**< HEADER_RX_ONLY Position */ 375 #define MXC_F_SPIXFC_HEADER_RX_ONLY ((uint32_t)(0x3FFFUL << MXC_F_SPIXFC_HEADER_RX_ONLY_POS)) /**< HEADER_RX_ONLY Mask */ 376 377 /**@} end of group SPIXFC_HEADER_Register */ 378 379 #ifdef __cplusplus 380 } 381 #endif 382 383 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SPIXFC_REGS_H_ 384
