1 /** 2 * @file smon_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SMON Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup smon_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SMON_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SMON_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup smon 67 * @defgroup smon_registers SMON_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SMON Peripheral Module. 69 * @details The Security Monitor block used to monitor system threat conditions. 70 */ 71 72 /** 73 * @ingroup smon_registers 74 * Structure type to access the SMON Registers. 75 */ 76 typedef struct { 77 __IO uint32_t extsctrl; /**< <tt>\b 0x00:</tt> SMON EXTSCTRL Register */ 78 __IO uint32_t intsctrl; /**< <tt>\b 0x04:</tt> SMON INTSCTRL Register */ 79 __IO uint32_t secalm; /**< <tt>\b 0x08:</tt> SMON SECALM Register */ 80 __IO uint32_t secdiag; /**< <tt>\b 0x0C:</tt> SMON SECDIAG Register */ 81 __I uint32_t dlrtc; /**< <tt>\b 0x10:</tt> SMON DLRTC Register */ 82 __R uint32_t rsv_0x14_0x23[4]; 83 __IO uint32_t meuctrl; /**< <tt>\b 0x24:</tt> SMON MEUCTRL Register */ 84 __R uint32_t rsv_0x28_0x33[3]; 85 __I uint32_t secst; /**< <tt>\b 0x34:</tt> SMON SECST Register */ 86 __IO uint32_t sdbe; /**< <tt>\b 0x38:</tt> SMON SDBE Register */ 87 } mxc_smon_regs_t; 88 89 /* Register offsets for module SMON */ 90 /** 91 * @ingroup smon_registers 92 * @defgroup SMON_Register_Offsets Register Offsets 93 * @brief SMON Peripheral Register Offsets from the SMON Base Peripheral Address. 94 * @{ 95 */ 96 #define MXC_R_SMON_EXTSCTRL ((uint32_t)0x00000000UL) /**< Offset from SMON Base Address: <tt> 0x0000</tt> */ 97 #define MXC_R_SMON_INTSCTRL ((uint32_t)0x00000004UL) /**< Offset from SMON Base Address: <tt> 0x0004</tt> */ 98 #define MXC_R_SMON_SECALM ((uint32_t)0x00000008UL) /**< Offset from SMON Base Address: <tt> 0x0008</tt> */ 99 #define MXC_R_SMON_SECDIAG ((uint32_t)0x0000000CUL) /**< Offset from SMON Base Address: <tt> 0x000C</tt> */ 100 #define MXC_R_SMON_DLRTC ((uint32_t)0x00000010UL) /**< Offset from SMON Base Address: <tt> 0x0010</tt> */ 101 #define MXC_R_SMON_MEUCTRL ((uint32_t)0x00000024UL) /**< Offset from SMON Base Address: <tt> 0x0024</tt> */ 102 #define MXC_R_SMON_SECST ((uint32_t)0x00000034UL) /**< Offset from SMON Base Address: <tt> 0x0034</tt> */ 103 #define MXC_R_SMON_SDBE ((uint32_t)0x00000038UL) /**< Offset from SMON Base Address: <tt> 0x0038</tt> */ 104 /**@} end of group smon_registers */ 105 106 /** 107 * @ingroup smon_registers 108 * @defgroup SMON_EXTSCTRL SMON_EXTSCTRL 109 * @brief External Sensor Control Register. 110 * @{ 111 */ 112 #define MXC_F_SMON_EXTSCTRL_EXTS_EN0_POS 0 /**< EXTSCTRL_EXTS_EN0 Position */ 113 #define MXC_F_SMON_EXTSCTRL_EXTS_EN0 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCTRL_EXTS_EN0_POS)) /**< EXTSCTRL_EXTS_EN0 Mask */ 114 115 #define MXC_F_SMON_EXTSCTRL_EXTS_EN1_POS 1 /**< EXTSCTRL_EXTS_EN1 Position */ 116 #define MXC_F_SMON_EXTSCTRL_EXTS_EN1 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCTRL_EXTS_EN1_POS)) /**< EXTSCTRL_EXTS_EN1 Mask */ 117 118 #define MXC_F_SMON_EXTSCTRL_EXTS_EN2_POS 2 /**< EXTSCTRL_EXTS_EN2 Position */ 119 #define MXC_F_SMON_EXTSCTRL_EXTS_EN2 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCTRL_EXTS_EN2_POS)) /**< EXTSCTRL_EXTS_EN2 Mask */ 120 121 #define MXC_F_SMON_EXTSCTRL_EXTS_EN3_POS 3 /**< EXTSCTRL_EXTS_EN3 Position */ 122 #define MXC_F_SMON_EXTSCTRL_EXTS_EN3 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCTRL_EXTS_EN3_POS)) /**< EXTSCTRL_EXTS_EN3 Mask */ 123 124 #define MXC_F_SMON_EXTSCTRL_EXTS_EN4_POS 4 /**< EXTSCTRL_EXTS_EN4 Position */ 125 #define MXC_F_SMON_EXTSCTRL_EXTS_EN4 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCTRL_EXTS_EN4_POS)) /**< EXTSCTRL_EXTS_EN4 Mask */ 126 127 #define MXC_F_SMON_EXTSCTRL_EXTS_EN5_POS 5 /**< EXTSCTRL_EXTS_EN5 Position */ 128 #define MXC_F_SMON_EXTSCTRL_EXTS_EN5 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCTRL_EXTS_EN5_POS)) /**< EXTSCTRL_EXTS_EN5 Mask */ 129 130 #define MXC_F_SMON_EXTSCTRL_EXTCNT_POS 16 /**< EXTSCTRL_EXTCNT Position */ 131 #define MXC_F_SMON_EXTSCTRL_EXTCNT ((uint32_t)(0x1FUL << MXC_F_SMON_EXTSCTRL_EXTCNT_POS)) /**< EXTSCTRL_EXTCNT Mask */ 132 133 #define MXC_F_SMON_EXTSCTRL_EXTFRQ_POS 21 /**< EXTSCTRL_EXTFRQ Position */ 134 #define MXC_F_SMON_EXTSCTRL_EXTFRQ ((uint32_t)(0x7UL << MXC_F_SMON_EXTSCTRL_EXTFRQ_POS)) /**< EXTSCTRL_EXTFRQ Mask */ 135 #define MXC_V_SMON_EXTSCTRL_EXTFRQ_FREQ2000HZ ((uint32_t)0x0UL) /**< EXTSCTRL_EXTFRQ_FREQ2000HZ Value */ 136 #define MXC_S_SMON_EXTSCTRL_EXTFRQ_FREQ2000HZ (MXC_V_SMON_EXTSCTRL_EXTFRQ_FREQ2000HZ << MXC_F_SMON_EXTSCTRL_EXTFRQ_POS) /**< EXTSCTRL_EXTFRQ_FREQ2000HZ Setting */ 137 #define MXC_V_SMON_EXTSCTRL_EXTFRQ_FREQ1000HZ ((uint32_t)0x1UL) /**< EXTSCTRL_EXTFRQ_FREQ1000HZ Value */ 138 #define MXC_S_SMON_EXTSCTRL_EXTFRQ_FREQ1000HZ (MXC_V_SMON_EXTSCTRL_EXTFRQ_FREQ1000HZ << MXC_F_SMON_EXTSCTRL_EXTFRQ_POS) /**< EXTSCTRL_EXTFRQ_FREQ1000HZ Setting */ 139 #define MXC_V_SMON_EXTSCTRL_EXTFRQ_FREQ500HZ ((uint32_t)0x2UL) /**< EXTSCTRL_EXTFRQ_FREQ500HZ Value */ 140 #define MXC_S_SMON_EXTSCTRL_EXTFRQ_FREQ500HZ (MXC_V_SMON_EXTSCTRL_EXTFRQ_FREQ500HZ << MXC_F_SMON_EXTSCTRL_EXTFRQ_POS) /**< EXTSCTRL_EXTFRQ_FREQ500HZ Setting */ 141 #define MXC_V_SMON_EXTSCTRL_EXTFRQ_FREQ250HZ ((uint32_t)0x3UL) /**< EXTSCTRL_EXTFRQ_FREQ250HZ Value */ 142 #define MXC_S_SMON_EXTSCTRL_EXTFRQ_FREQ250HZ (MXC_V_SMON_EXTSCTRL_EXTFRQ_FREQ250HZ << MXC_F_SMON_EXTSCTRL_EXTFRQ_POS) /**< EXTSCTRL_EXTFRQ_FREQ250HZ Setting */ 143 #define MXC_V_SMON_EXTSCTRL_EXTFRQ_FREQ125HZ ((uint32_t)0x4UL) /**< EXTSCTRL_EXTFRQ_FREQ125HZ Value */ 144 #define MXC_S_SMON_EXTSCTRL_EXTFRQ_FREQ125HZ (MXC_V_SMON_EXTSCTRL_EXTFRQ_FREQ125HZ << MXC_F_SMON_EXTSCTRL_EXTFRQ_POS) /**< EXTSCTRL_EXTFRQ_FREQ125HZ Setting */ 145 #define MXC_V_SMON_EXTSCTRL_EXTFRQ_FREQ63HZ ((uint32_t)0x5UL) /**< EXTSCTRL_EXTFRQ_FREQ63HZ Value */ 146 #define MXC_S_SMON_EXTSCTRL_EXTFRQ_FREQ63HZ (MXC_V_SMON_EXTSCTRL_EXTFRQ_FREQ63HZ << MXC_F_SMON_EXTSCTRL_EXTFRQ_POS) /**< EXTSCTRL_EXTFRQ_FREQ63HZ Setting */ 147 #define MXC_V_SMON_EXTSCTRL_EXTFRQ_FREQ31HZ ((uint32_t)0x6UL) /**< EXTSCTRL_EXTFRQ_FREQ31HZ Value */ 148 #define MXC_S_SMON_EXTSCTRL_EXTFRQ_FREQ31HZ (MXC_V_SMON_EXTSCTRL_EXTFRQ_FREQ31HZ << MXC_F_SMON_EXTSCTRL_EXTFRQ_POS) /**< EXTSCTRL_EXTFRQ_FREQ31HZ Setting */ 149 #define MXC_V_SMON_EXTSCTRL_EXTFRQ_RFU ((uint32_t)0x7UL) /**< EXTSCTRL_EXTFRQ_RFU Value */ 150 #define MXC_S_SMON_EXTSCTRL_EXTFRQ_RFU (MXC_V_SMON_EXTSCTRL_EXTFRQ_RFU << MXC_F_SMON_EXTSCTRL_EXTFRQ_POS) /**< EXTSCTRL_EXTFRQ_RFU Setting */ 151 152 #define MXC_F_SMON_EXTSCTRL_CLKDIV_POS 24 /**< EXTSCTRL_CLKDIV Position */ 153 #define MXC_F_SMON_EXTSCTRL_CLKDIV ((uint32_t)(0x7UL << MXC_F_SMON_EXTSCTRL_CLKDIV_POS)) /**< EXTSCTRL_CLKDIV Mask */ 154 #define MXC_V_SMON_EXTSCTRL_CLKDIV_DIV1 ((uint32_t)0x0UL) /**< EXTSCTRL_CLKDIV_DIV1 Value */ 155 #define MXC_S_SMON_EXTSCTRL_CLKDIV_DIV1 (MXC_V_SMON_EXTSCTRL_CLKDIV_DIV1 << MXC_F_SMON_EXTSCTRL_CLKDIV_POS) /**< EXTSCTRL_CLKDIV_DIV1 Setting */ 156 #define MXC_V_SMON_EXTSCTRL_CLKDIV_DIV2 ((uint32_t)0x1UL) /**< EXTSCTRL_CLKDIV_DIV2 Value */ 157 #define MXC_S_SMON_EXTSCTRL_CLKDIV_DIV2 (MXC_V_SMON_EXTSCTRL_CLKDIV_DIV2 << MXC_F_SMON_EXTSCTRL_CLKDIV_POS) /**< EXTSCTRL_CLKDIV_DIV2 Setting */ 158 #define MXC_V_SMON_EXTSCTRL_CLKDIV_DIV4 ((uint32_t)0x2UL) /**< EXTSCTRL_CLKDIV_DIV4 Value */ 159 #define MXC_S_SMON_EXTSCTRL_CLKDIV_DIV4 (MXC_V_SMON_EXTSCTRL_CLKDIV_DIV4 << MXC_F_SMON_EXTSCTRL_CLKDIV_POS) /**< EXTSCTRL_CLKDIV_DIV4 Setting */ 160 #define MXC_V_SMON_EXTSCTRL_CLKDIV_DIV8 ((uint32_t)0x3UL) /**< EXTSCTRL_CLKDIV_DIV8 Value */ 161 #define MXC_S_SMON_EXTSCTRL_CLKDIV_DIV8 (MXC_V_SMON_EXTSCTRL_CLKDIV_DIV8 << MXC_F_SMON_EXTSCTRL_CLKDIV_POS) /**< EXTSCTRL_CLKDIV_DIV8 Setting */ 162 #define MXC_V_SMON_EXTSCTRL_CLKDIV_DIV16 ((uint32_t)0x4UL) /**< EXTSCTRL_CLKDIV_DIV16 Value */ 163 #define MXC_S_SMON_EXTSCTRL_CLKDIV_DIV16 (MXC_V_SMON_EXTSCTRL_CLKDIV_DIV16 << MXC_F_SMON_EXTSCTRL_CLKDIV_POS) /**< EXTSCTRL_CLKDIV_DIV16 Setting */ 164 #define MXC_V_SMON_EXTSCTRL_CLKDIV_DIV32 ((uint32_t)0x5UL) /**< EXTSCTRL_CLKDIV_DIV32 Value */ 165 #define MXC_S_SMON_EXTSCTRL_CLKDIV_DIV32 (MXC_V_SMON_EXTSCTRL_CLKDIV_DIV32 << MXC_F_SMON_EXTSCTRL_CLKDIV_POS) /**< EXTSCTRL_CLKDIV_DIV32 Setting */ 166 #define MXC_V_SMON_EXTSCTRL_CLKDIV_DIV64 ((uint32_t)0x6UL) /**< EXTSCTRL_CLKDIV_DIV64 Value */ 167 #define MXC_S_SMON_EXTSCTRL_CLKDIV_DIV64 (MXC_V_SMON_EXTSCTRL_CLKDIV_DIV64 << MXC_F_SMON_EXTSCTRL_CLKDIV_POS) /**< EXTSCTRL_CLKDIV_DIV64 Setting */ 168 169 #define MXC_F_SMON_EXTSCTRL_BUSY_POS 30 /**< EXTSCTRL_BUSY Position */ 170 #define MXC_F_SMON_EXTSCTRL_BUSY ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCTRL_BUSY_POS)) /**< EXTSCTRL_BUSY Mask */ 171 172 #define MXC_F_SMON_EXTSCTRL_LOCK_POS 31 /**< EXTSCTRL_LOCK Position */ 173 #define MXC_F_SMON_EXTSCTRL_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCTRL_LOCK_POS)) /**< EXTSCTRL_LOCK Mask */ 174 175 /**@} end of group SMON_EXTSCTRL_Register */ 176 177 /** 178 * @ingroup smon_registers 179 * @defgroup SMON_INTSCTRL SMON_INTSCTRL 180 * @brief Internal Sensor Control Register. 181 * @{ 182 */ 183 #define MXC_F_SMON_INTSCTRL_SHIELD_EN_POS 0 /**< INTSCTRL_SHIELD_EN Position */ 184 #define MXC_F_SMON_INTSCTRL_SHIELD_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCTRL_SHIELD_EN_POS)) /**< INTSCTRL_SHIELD_EN Mask */ 185 186 #define MXC_F_SMON_INTSCTRL_TEMP_EN_POS 1 /**< INTSCTRL_TEMP_EN Position */ 187 #define MXC_F_SMON_INTSCTRL_TEMP_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCTRL_TEMP_EN_POS)) /**< INTSCTRL_TEMP_EN Mask */ 188 189 #define MXC_F_SMON_INTSCTRL_VBAT_EN_POS 2 /**< INTSCTRL_VBAT_EN Position */ 190 #define MXC_F_SMON_INTSCTRL_VBAT_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCTRL_VBAT_EN_POS)) /**< INTSCTRL_VBAT_EN Mask */ 191 192 #define MXC_F_SMON_INTSCTRL_DFD_EN_POS 3 /**< INTSCTRL_DFD_EN Position */ 193 #define MXC_F_SMON_INTSCTRL_DFD_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCTRL_DFD_EN_POS)) /**< INTSCTRL_DFD_EN Mask */ 194 195 #define MXC_F_SMON_INTSCTRL_DFD_NMI_EN_POS 4 /**< INTSCTRL_DFD_NMI_EN Position */ 196 #define MXC_F_SMON_INTSCTRL_DFD_NMI_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCTRL_DFD_NMI_EN_POS)) /**< INTSCTRL_DFD_NMI_EN Mask */ 197 198 #define MXC_F_SMON_INTSCTRL_TAMPOUT_EN_POS 7 /**< INTSCTRL_TAMPOUT_EN Position */ 199 #define MXC_F_SMON_INTSCTRL_TAMPOUT_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCTRL_TAMPOUT_EN_POS)) /**< INTSCTRL_TAMPOUT_EN Mask */ 200 201 #define MXC_F_SMON_INTSCTRL_LOTEMP_SEL_POS 16 /**< INTSCTRL_LOTEMP_SEL Position */ 202 #define MXC_F_SMON_INTSCTRL_LOTEMP_SEL ((uint32_t)(0x1UL << MXC_F_SMON_INTSCTRL_LOTEMP_SEL_POS)) /**< INTSCTRL_LOTEMP_SEL Mask */ 203 204 #define MXC_F_SMON_INTSCTRL_HITEMP_SEL_POS 17 /**< INTSCTRL_HITEMP_SEL Position */ 205 #define MXC_F_SMON_INTSCTRL_HITEMP_SEL ((uint32_t)(0x1UL << MXC_F_SMON_INTSCTRL_HITEMP_SEL_POS)) /**< INTSCTRL_HITEMP_SEL Mask */ 206 207 #define MXC_F_SMON_INTSCTRL_VCORELO_EN_POS 18 /**< INTSCTRL_VCORELO_EN Position */ 208 #define MXC_F_SMON_INTSCTRL_VCORELO_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCTRL_VCORELO_EN_POS)) /**< INTSCTRL_VCORELO_EN Mask */ 209 210 #define MXC_F_SMON_INTSCTRL_VCOREHI_EN_POS 19 /**< INTSCTRL_VCOREHI_EN Position */ 211 #define MXC_F_SMON_INTSCTRL_VCOREHI_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCTRL_VCOREHI_EN_POS)) /**< INTSCTRL_VCOREHI_EN Mask */ 212 213 #define MXC_F_SMON_INTSCTRL_VDDLO_EN_POS 20 /**< INTSCTRL_VDDLO_EN Position */ 214 #define MXC_F_SMON_INTSCTRL_VDDLO_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCTRL_VDDLO_EN_POS)) /**< INTSCTRL_VDDLO_EN Mask */ 215 216 #define MXC_F_SMON_INTSCTRL_VDDHI_EN_POS 21 /**< INTSCTRL_VDDHI_EN Position */ 217 #define MXC_F_SMON_INTSCTRL_VDDHI_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCTRL_VDDHI_EN_POS)) /**< INTSCTRL_VDDHI_EN Mask */ 218 219 #define MXC_F_SMON_INTSCTRL_VGL_EN_POS 22 /**< INTSCTRL_VGL_EN Position */ 220 #define MXC_F_SMON_INTSCTRL_VGL_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCTRL_VGL_EN_POS)) /**< INTSCTRL_VGL_EN Mask */ 221 222 #define MXC_F_SMON_INTSCTRL_LOCK_POS 31 /**< INTSCTRL_LOCK Position */ 223 #define MXC_F_SMON_INTSCTRL_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_INTSCTRL_LOCK_POS)) /**< INTSCTRL_LOCK Mask */ 224 225 /**@} end of group SMON_INTSCTRL_Register */ 226 227 /** 228 * @ingroup smon_registers 229 * @defgroup SMON_SECALM SMON_SECALM 230 * @brief Security Alarm Register. 231 * @{ 232 */ 233 #define MXC_F_SMON_SECALM_DRS_POS 0 /**< SECALM_DRS Position */ 234 #define MXC_F_SMON_SECALM_DRS ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_DRS_POS)) /**< SECALM_DRS Mask */ 235 236 #define MXC_F_SMON_SECALM_KEYWIPE_POS 1 /**< SECALM_KEYWIPE Position */ 237 #define MXC_F_SMON_SECALM_KEYWIPE ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_KEYWIPE_POS)) /**< SECALM_KEYWIPE Mask */ 238 239 #define MXC_F_SMON_SECALM_SHIELD_FL_POS 2 /**< SECALM_SHIELD_FL Position */ 240 #define MXC_F_SMON_SECALM_SHIELD_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_SHIELD_FL_POS)) /**< SECALM_SHIELD_FL Mask */ 241 242 #define MXC_F_SMON_SECALM_LOTEMP_FL_POS 3 /**< SECALM_LOTEMP_FL Position */ 243 #define MXC_F_SMON_SECALM_LOTEMP_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_LOTEMP_FL_POS)) /**< SECALM_LOTEMP_FL Mask */ 244 245 #define MXC_F_SMON_SECALM_HITEMP_FL_POS 4 /**< SECALM_HITEMP_FL Position */ 246 #define MXC_F_SMON_SECALM_HITEMP_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_HITEMP_FL_POS)) /**< SECALM_HITEMP_FL Mask */ 247 248 #define MXC_F_SMON_SECALM_BATLO_FL_POS 5 /**< SECALM_BATLO_FL Position */ 249 #define MXC_F_SMON_SECALM_BATLO_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_BATLO_FL_POS)) /**< SECALM_BATLO_FL Mask */ 250 251 #define MXC_F_SMON_SECALM_BATHI_FL_POS 6 /**< SECALM_BATHI_FL Position */ 252 #define MXC_F_SMON_SECALM_BATHI_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_BATHI_FL_POS)) /**< SECALM_BATHI_FL Mask */ 253 254 #define MXC_F_SMON_SECALM_EXTS_FL_POS 7 /**< SECALM_EXTS_FL Position */ 255 #define MXC_F_SMON_SECALM_EXTS_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTS_FL_POS)) /**< SECALM_EXTS_FL Mask */ 256 257 #define MXC_F_SMON_SECALM_DFD_FL_POS 8 /**< SECALM_DFD_FL Position */ 258 #define MXC_F_SMON_SECALM_DFD_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_DFD_FL_POS)) /**< SECALM_DFD_FL Mask */ 259 260 #define MXC_F_SMON_SECALM_VMAINPF_FL_POS 9 /**< SECALM_VMAINPF_FL Position */ 261 #define MXC_F_SMON_SECALM_VMAINPF_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VMAINPF_FL_POS)) /**< SECALM_VMAINPF_FL Mask */ 262 263 #define MXC_F_SMON_SECALM_VCOREHI_FL_POS 10 /**< SECALM_VCOREHI_FL Position */ 264 #define MXC_F_SMON_SECALM_VCOREHI_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VCOREHI_FL_POS)) /**< SECALM_VCOREHI_FL Mask */ 265 266 #define MXC_F_SMON_SECALM_VDDHI_FL_POS 11 /**< SECALM_VDDHI_FL Position */ 267 #define MXC_F_SMON_SECALM_VDDHI_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VDDHI_FL_POS)) /**< SECALM_VDDHI_FL Mask */ 268 269 #define MXC_F_SMON_SECALM_VGL_FL_POS 12 /**< SECALM_VGL_FL Position */ 270 #define MXC_F_SMON_SECALM_VGL_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VGL_FL_POS)) /**< SECALM_VGL_FL Mask */ 271 272 #define MXC_F_SMON_SECALM_EXTSTAT0_FL_POS 16 /**< SECALM_EXTSTAT0_FL Position */ 273 #define MXC_F_SMON_SECALM_EXTSTAT0_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT0_FL_POS)) /**< SECALM_EXTSTAT0_FL Mask */ 274 275 #define MXC_F_SMON_SECALM_EXTSTAT1_FL_POS 17 /**< SECALM_EXTSTAT1_FL Position */ 276 #define MXC_F_SMON_SECALM_EXTSTAT1_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT1_FL_POS)) /**< SECALM_EXTSTAT1_FL Mask */ 277 278 #define MXC_F_SMON_SECALM_EXTSTAT2_FL_POS 18 /**< SECALM_EXTSTAT2_FL Position */ 279 #define MXC_F_SMON_SECALM_EXTSTAT2_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT2_FL_POS)) /**< SECALM_EXTSTAT2_FL Mask */ 280 281 #define MXC_F_SMON_SECALM_EXTSTAT3_FL_POS 19 /**< SECALM_EXTSTAT3_FL Position */ 282 #define MXC_F_SMON_SECALM_EXTSTAT3_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT3_FL_POS)) /**< SECALM_EXTSTAT3_FL Mask */ 283 284 #define MXC_F_SMON_SECALM_EXTSTAT4_FL_POS 20 /**< SECALM_EXTSTAT4_FL Position */ 285 #define MXC_F_SMON_SECALM_EXTSTAT4_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT4_FL_POS)) /**< SECALM_EXTSTAT4_FL Mask */ 286 287 #define MXC_F_SMON_SECALM_EXTSTAT5_FL_POS 21 /**< SECALM_EXTSTAT5_FL Position */ 288 #define MXC_F_SMON_SECALM_EXTSTAT5_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT5_FL_POS)) /**< SECALM_EXTSTAT5_FL Mask */ 289 290 #define MXC_F_SMON_SECALM_EXTSWARN0_FL_POS 24 /**< SECALM_EXTSWARN0_FL Position */ 291 #define MXC_F_SMON_SECALM_EXTSWARN0_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN0_FL_POS)) /**< SECALM_EXTSWARN0_FL Mask */ 292 293 #define MXC_F_SMON_SECALM_EXTSWARN1_FL_POS 25 /**< SECALM_EXTSWARN1_FL Position */ 294 #define MXC_F_SMON_SECALM_EXTSWARN1_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN1_FL_POS)) /**< SECALM_EXTSWARN1_FL Mask */ 295 296 #define MXC_F_SMON_SECALM_EXTSWARN2_FL_POS 26 /**< SECALM_EXTSWARN2_FL Position */ 297 #define MXC_F_SMON_SECALM_EXTSWARN2_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN2_FL_POS)) /**< SECALM_EXTSWARN2_FL Mask */ 298 299 #define MXC_F_SMON_SECALM_EXTSWARN3_FL_POS 27 /**< SECALM_EXTSWARN3_FL Position */ 300 #define MXC_F_SMON_SECALM_EXTSWARN3_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN3_FL_POS)) /**< SECALM_EXTSWARN3_FL Mask */ 301 302 #define MXC_F_SMON_SECALM_EXTSWARN4_FL_POS 28 /**< SECALM_EXTSWARN4_FL Position */ 303 #define MXC_F_SMON_SECALM_EXTSWARN4_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN4_FL_POS)) /**< SECALM_EXTSWARN4_FL Mask */ 304 305 #define MXC_F_SMON_SECALM_EXTSWARN5_FL_POS 29 /**< SECALM_EXTSWARN5_FL Position */ 306 #define MXC_F_SMON_SECALM_EXTSWARN5_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN5_FL_POS)) /**< SECALM_EXTSWARN5_FL Mask */ 307 308 /**@} end of group SMON_SECALM_Register */ 309 310 /** 311 * @ingroup smon_registers 312 * @defgroup SMON_SECDIAG SMON_SECDIAG 313 * @brief Security Diagnostic Register. 314 * @{ 315 */ 316 #define MXC_F_SMON_SECDIAG_POR_FL_POS 0 /**< SECDIAG_POR_FL Position */ 317 #define MXC_F_SMON_SECDIAG_POR_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_POR_FL_POS)) /**< SECDIAG_POR_FL Mask */ 318 319 #define MXC_F_SMON_SECDIAG_SHIELD_FL_POS 2 /**< SECDIAG_SHIELD_FL Position */ 320 #define MXC_F_SMON_SECDIAG_SHIELD_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_SHIELD_FL_POS)) /**< SECDIAG_SHIELD_FL Mask */ 321 322 #define MXC_F_SMON_SECDIAG_LOTEMP_FL_POS 3 /**< SECDIAG_LOTEMP_FL Position */ 323 #define MXC_F_SMON_SECDIAG_LOTEMP_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_LOTEMP_FL_POS)) /**< SECDIAG_LOTEMP_FL Mask */ 324 325 #define MXC_F_SMON_SECDIAG_HITEMP_FL_POS 4 /**< SECDIAG_HITEMP_FL Position */ 326 #define MXC_F_SMON_SECDIAG_HITEMP_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_HITEMP_FL_POS)) /**< SECDIAG_HITEMP_FL Mask */ 327 328 #define MXC_F_SMON_SECDIAG_BATLO_FL_POS 5 /**< SECDIAG_BATLO_FL Position */ 329 #define MXC_F_SMON_SECDIAG_BATLO_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BATLO_FL_POS)) /**< SECDIAG_BATLO_FL Mask */ 330 331 #define MXC_F_SMON_SECDIAG_BATHI_FL_POS 6 /**< SECDIAG_BATHI_FL Position */ 332 #define MXC_F_SMON_SECDIAG_BATHI_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BATHI_FL_POS)) /**< SECDIAG_BATHI_FL Mask */ 333 334 #define MXC_F_SMON_SECDIAG_DYNS_FL_POS 7 /**< SECDIAG_DYNS_FL Position */ 335 #define MXC_F_SMON_SECDIAG_DYNS_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_DYNS_FL_POS)) /**< SECDIAG_DYNS_FL Mask */ 336 337 #define MXC_F_SMON_SECDIAG_AESKT_MEU_POS 8 /**< SECDIAG_AESKT_MEU Position */ 338 #define MXC_F_SMON_SECDIAG_AESKT_MEU ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_AESKT_MEU_POS)) /**< SECDIAG_AESKT_MEU Mask */ 339 340 #define MXC_F_SMON_SECDIAG_AESKT_MEMPROT_XIP_POS 9 /**< SECDIAG_AESKT_MEMPROT_XIP Position */ 341 #define MXC_F_SMON_SECDIAG_AESKT_MEMPROT_XIP ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_AESKT_MEMPROT_XIP_POS)) /**< SECDIAG_AESKT_MEMPROT_XIP Mask */ 342 343 #define MXC_F_SMON_SECDIAG_KEY0_ZERO_POS 10 /**< SECDIAG_KEY0_ZERO Position */ 344 #define MXC_F_SMON_SECDIAG_KEY0_ZERO ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_KEY0_ZERO_POS)) /**< SECDIAG_KEY0_ZERO Mask */ 345 346 #define MXC_F_SMON_SECDIAG_KEY1_ZERO_POS 11 /**< SECDIAG_KEY1_ZERO Position */ 347 #define MXC_F_SMON_SECDIAG_KEY1_ZERO ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_KEY1_ZERO_POS)) /**< SECDIAG_KEY1_ZERO Mask */ 348 349 #define MXC_F_SMON_SECDIAG_DFD_FL_POS 15 /**< SECDIAG_DFD_FL Position */ 350 #define MXC_F_SMON_SECDIAG_DFD_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_DFD_FL_POS)) /**< SECDIAG_DFD_FL Mask */ 351 352 #define MXC_F_SMON_SECDIAG_EXTS0_FL_POS 16 /**< SECDIAG_EXTS0_FL Position */ 353 #define MXC_F_SMON_SECDIAG_EXTS0_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTS0_FL_POS)) /**< SECDIAG_EXTS0_FL Mask */ 354 355 #define MXC_F_SMON_SECDIAG_EXTS1_FL_POS 17 /**< SECDIAG_EXTS1_FL Position */ 356 #define MXC_F_SMON_SECDIAG_EXTS1_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTS1_FL_POS)) /**< SECDIAG_EXTS1_FL Mask */ 357 358 #define MXC_F_SMON_SECDIAG_EXTS2_FL_POS 18 /**< SECDIAG_EXTS2_FL Position */ 359 #define MXC_F_SMON_SECDIAG_EXTS2_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTS2_FL_POS)) /**< SECDIAG_EXTS2_FL Mask */ 360 361 #define MXC_F_SMON_SECDIAG_EXTS3_FL_POS 19 /**< SECDIAG_EXTS3_FL Position */ 362 #define MXC_F_SMON_SECDIAG_EXTS3_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTS3_FL_POS)) /**< SECDIAG_EXTS3_FL Mask */ 363 364 #define MXC_F_SMON_SECDIAG_EXTS4_FL_POS 20 /**< SECDIAG_EXTS4_FL Position */ 365 #define MXC_F_SMON_SECDIAG_EXTS4_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTS4_FL_POS)) /**< SECDIAG_EXTS4_FL Mask */ 366 367 #define MXC_F_SMON_SECDIAG_EXTS5_FL_POS 21 /**< SECDIAG_EXTS5_FL Position */ 368 #define MXC_F_SMON_SECDIAG_EXTS5_FL ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTS5_FL_POS)) /**< SECDIAG_EXTS5_FL Mask */ 369 370 /**@} end of group SMON_SECDIAG_Register */ 371 372 /** 373 * @ingroup smon_registers 374 * @defgroup SMON_DLRTC SMON_DLRTC 375 * @brief DRS Log RTC Value. This register contains the 32 bit value in the RTC second 376 * register when the last DRS event occurred. 377 * @{ 378 */ 379 #define MXC_F_SMON_DLRTC_DLRTC_POS 0 /**< DLRTC_DLRTC Position */ 380 #define MXC_F_SMON_DLRTC_DLRTC ((uint32_t)(0xFFFFFFFFUL << MXC_F_SMON_DLRTC_DLRTC_POS)) /**< DLRTC_DLRTC Mask */ 381 382 /**@} end of group SMON_DLRTC_Register */ 383 384 /** 385 * @ingroup smon_registers 386 * @defgroup SMON_MEUCTRL SMON_MEUCTRL 387 * @brief MEU Configuration 388 * @{ 389 */ 390 #define MXC_F_SMON_MEUCTRL_ENC_EN_POS 0 /**< MEUCTRL_ENC_EN Position */ 391 #define MXC_F_SMON_MEUCTRL_ENC_EN ((uint32_t)(0x7FUL << MXC_F_SMON_MEUCTRL_ENC_EN_POS)) /**< MEUCTRL_ENC_EN Mask */ 392 393 #define MXC_F_SMON_MEUCTRL_LOCK_POS 31 /**< MEUCTRL_LOCK Position */ 394 #define MXC_F_SMON_MEUCTRL_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_MEUCTRL_LOCK_POS)) /**< MEUCTRL_LOCK Mask */ 395 396 /**@} end of group SMON_MEUCTRL_Register */ 397 398 /** 399 * @ingroup smon_registers 400 * @defgroup SMON_SECST SMON_SECST 401 * @brief Security Monitor Status Register. 402 * @{ 403 */ 404 #define MXC_F_SMON_SECST_EXTSCTRL_POS 0 /**< SECST_EXTSCTRL Position */ 405 #define MXC_F_SMON_SECST_EXTSCTRL ((uint32_t)(0x1UL << MXC_F_SMON_SECST_EXTSCTRL_POS)) /**< SECST_EXTSCTRL Mask */ 406 407 #define MXC_F_SMON_SECST_INTSCTRL_POS 1 /**< SECST_INTSCTRL Position */ 408 #define MXC_F_SMON_SECST_INTSCTRL ((uint32_t)(0x1UL << MXC_F_SMON_SECST_INTSCTRL_POS)) /**< SECST_INTSCTRL Mask */ 409 410 #define MXC_F_SMON_SECST_SECALM_POS 2 /**< SECST_SECALM Position */ 411 #define MXC_F_SMON_SECST_SECALM ((uint32_t)(0x1UL << MXC_F_SMON_SECST_SECALM_POS)) /**< SECST_SECALM Mask */ 412 413 #define MXC_F_SMON_SECST_MEUCTRL_POS 7 /**< SECST_MEUCTRL Position */ 414 #define MXC_F_SMON_SECST_MEUCTRL ((uint32_t)(0x1UL << MXC_F_SMON_SECST_MEUCTRL_POS)) /**< SECST_MEUCTRL Mask */ 415 416 /**@} end of group SMON_SECST_Register */ 417 418 /** 419 * @ingroup smon_registers 420 * @defgroup SMON_SDBE SMON_SDBE 421 * @brief Security Monitor Self Destruct Byte. 422 * @{ 423 */ 424 #define MXC_F_SMON_SDBE_SDBYTE_POS 0 /**< SDBE_SDBYTE Position */ 425 #define MXC_F_SMON_SDBE_SDBYTE ((uint32_t)(0xFFUL << MXC_F_SMON_SDBE_SDBYTE_POS)) /**< SDBE_SDBYTE Mask */ 426 427 #define MXC_F_SMON_SDBE_SDBYTE_EN_POS 31 /**< SDBE_SDBYTE_EN Position */ 428 #define MXC_F_SMON_SDBE_SDBYTE_EN ((uint32_t)(0x1UL << MXC_F_SMON_SDBE_SDBYTE_EN_POS)) /**< SDBE_SDBYTE_EN Mask */ 429 430 /**@} end of group SMON_SDBE_Register */ 431 432 #ifdef __cplusplus 433 } 434 #endif 435 436 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SMON_REGS_H_ 437
