1 /** 2 * @file scn_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SCN Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup scn_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SCN_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SCN_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup scn 67 * @defgroup scn_registers SCN_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SCN Peripheral Module. 69 * @details Smart Card Interface. 70 */ 71 72 /** 73 * @ingroup scn_registers 74 * Structure type to access the SCN Registers. 75 */ 76 typedef struct { 77 __IO uint32_t cr; /**< <tt>\b 0x00:</tt> SCN CR Register */ 78 __IO uint32_t sr; /**< <tt>\b 0x04:</tt> SCN SR Register */ 79 __IO uint32_t pn; /**< <tt>\b 0x08:</tt> SCN PN Register */ 80 __IO uint32_t etur; /**< <tt>\b 0x0C:</tt> SCN ETUR Register */ 81 __IO uint32_t gtr; /**< <tt>\b 0x10:</tt> SCN GTR Register */ 82 __IO uint32_t wt0r; /**< <tt>\b 0x14:</tt> SCN WT0R Register */ 83 __IO uint32_t wt1r; /**< <tt>\b 0x18:</tt> SCN WT1R Register */ 84 __IO uint32_t ier; /**< <tt>\b 0x1C:</tt> SCN IER Register */ 85 __IO uint32_t isr; /**< <tt>\b 0x20:</tt> SCN ISR Register */ 86 __IO uint32_t txr; /**< <tt>\b 0x24:</tt> SCN TXR Register */ 87 __IO uint32_t rxr; /**< <tt>\b 0x28:</tt> SCN RXR Register */ 88 __IO uint32_t ccr; /**< <tt>\b 0x2C:</tt> SCN CCR Register */ 89 } mxc_scn_regs_t; 90 91 /* Register offsets for module SCN */ 92 /** 93 * @ingroup scn_registers 94 * @defgroup SCN_Register_Offsets Register Offsets 95 * @brief SCN Peripheral Register Offsets from the SCN Base Peripheral Address. 96 * @{ 97 */ 98 #define MXC_R_SCN_CR ((uint32_t)0x00000000UL) /**< Offset from SCN Base Address: <tt> 0x0000</tt> */ 99 #define MXC_R_SCN_SR ((uint32_t)0x00000004UL) /**< Offset from SCN Base Address: <tt> 0x0004</tt> */ 100 #define MXC_R_SCN_PN ((uint32_t)0x00000008UL) /**< Offset from SCN Base Address: <tt> 0x0008</tt> */ 101 #define MXC_R_SCN_ETUR ((uint32_t)0x0000000CUL) /**< Offset from SCN Base Address: <tt> 0x000C</tt> */ 102 #define MXC_R_SCN_GTR ((uint32_t)0x00000010UL) /**< Offset from SCN Base Address: <tt> 0x0010</tt> */ 103 #define MXC_R_SCN_WT0R ((uint32_t)0x00000014UL) /**< Offset from SCN Base Address: <tt> 0x0014</tt> */ 104 #define MXC_R_SCN_WT1R ((uint32_t)0x00000018UL) /**< Offset from SCN Base Address: <tt> 0x0018</tt> */ 105 #define MXC_R_SCN_IER ((uint32_t)0x0000001CUL) /**< Offset from SCN Base Address: <tt> 0x001C</tt> */ 106 #define MXC_R_SCN_ISR ((uint32_t)0x00000020UL) /**< Offset from SCN Base Address: <tt> 0x0020</tt> */ 107 #define MXC_R_SCN_TXR ((uint32_t)0x00000024UL) /**< Offset from SCN Base Address: <tt> 0x0024</tt> */ 108 #define MXC_R_SCN_RXR ((uint32_t)0x00000028UL) /**< Offset from SCN Base Address: <tt> 0x0028</tt> */ 109 #define MXC_R_SCN_CCR ((uint32_t)0x0000002CUL) /**< Offset from SCN Base Address: <tt> 0x002C</tt> */ 110 /**@} end of group scn_registers */ 111 112 /** 113 * @ingroup scn_registers 114 * @defgroup SCN_CR SCN_CR 115 * @brief Control Register. 116 * @{ 117 */ 118 #define MXC_F_SCN_CR_CONV_POS 0 /**< CR_CONV Position */ 119 #define MXC_F_SCN_CR_CONV ((uint32_t)(0x1UL << MXC_F_SCN_CR_CONV_POS)) /**< CR_CONV Mask */ 120 121 #define MXC_F_SCN_CR_CREP_POS 1 /**< CR_CREP Position */ 122 #define MXC_F_SCN_CR_CREP ((uint32_t)(0x1UL << MXC_F_SCN_CR_CREP_POS)) /**< CR_CREP Mask */ 123 124 #define MXC_F_SCN_CR_WTEN_POS 2 /**< CR_WTEN Position */ 125 #define MXC_F_SCN_CR_WTEN ((uint32_t)(0x1UL << MXC_F_SCN_CR_WTEN_POS)) /**< CR_WTEN Mask */ 126 127 #define MXC_F_SCN_CR_UART_POS 3 /**< CR_UART Position */ 128 #define MXC_F_SCN_CR_UART ((uint32_t)(0x1UL << MXC_F_SCN_CR_UART_POS)) /**< CR_UART Mask */ 129 130 #define MXC_F_SCN_CR_CCEN_POS 4 /**< CR_CCEN Position */ 131 #define MXC_F_SCN_CR_CCEN ((uint32_t)(0x1UL << MXC_F_SCN_CR_CCEN_POS)) /**< CR_CCEN Mask */ 132 133 #define MXC_F_SCN_CR_RXFLUSH_POS 5 /**< CR_RXFLUSH Position */ 134 #define MXC_F_SCN_CR_RXFLUSH ((uint32_t)(0x1UL << MXC_F_SCN_CR_RXFLUSH_POS)) /**< CR_RXFLUSH Mask */ 135 136 #define MXC_F_SCN_CR_TXFLUSH_POS 6 /**< CR_TXFLUSH Position */ 137 #define MXC_F_SCN_CR_TXFLUSH ((uint32_t)(0x1UL << MXC_F_SCN_CR_TXFLUSH_POS)) /**< CR_TXFLUSH Mask */ 138 139 #define MXC_F_SCN_CR_RXTHD_POS 8 /**< CR_RXTHD Position */ 140 #define MXC_F_SCN_CR_RXTHD ((uint32_t)(0xFUL << MXC_F_SCN_CR_RXTHD_POS)) /**< CR_RXTHD Mask */ 141 142 #define MXC_F_SCN_CR_TXTHD_POS 12 /**< CR_TXTHD Position */ 143 #define MXC_F_SCN_CR_TXTHD ((uint32_t)(0xFUL << MXC_F_SCN_CR_TXTHD_POS)) /**< CR_TXTHD Mask */ 144 145 #define MXC_F_SCN_CR_DUAL_MODE_POS 23 /**< CR_DUAL_MODE Position */ 146 #define MXC_F_SCN_CR_DUAL_MODE ((uint32_t)(0x1UL << MXC_F_SCN_CR_DUAL_MODE_POS)) /**< CR_DUAL_MODE Mask */ 147 148 /**@} end of group SCN_CR_Register */ 149 150 /** 151 * @ingroup scn_registers 152 * @defgroup SCN_SR SCN_SR 153 * @brief Status Register. 154 * @{ 155 */ 156 #define MXC_F_SCN_SR_PAR_POS 0 /**< SR_PAR Position */ 157 #define MXC_F_SCN_SR_PAR ((uint32_t)(0x1UL << MXC_F_SCN_SR_PAR_POS)) /**< SR_PAR Mask */ 158 159 #define MXC_F_SCN_SR_WTOV_POS 1 /**< SR_WTOV Position */ 160 #define MXC_F_SCN_SR_WTOV ((uint32_t)(0x1UL << MXC_F_SCN_SR_WTOV_POS)) /**< SR_WTOV Mask */ 161 162 #define MXC_F_SCN_SR_CCOV_POS 2 /**< SR_CCOV Position */ 163 #define MXC_F_SCN_SR_CCOV ((uint32_t)(0x1UL << MXC_F_SCN_SR_CCOV_POS)) /**< SR_CCOV Mask */ 164 165 #define MXC_F_SCN_SR_TXCF_POS 3 /**< SR_TXCF Position */ 166 #define MXC_F_SCN_SR_TXCF ((uint32_t)(0x1UL << MXC_F_SCN_SR_TXCF_POS)) /**< SR_TXCF Mask */ 167 168 #define MXC_F_SCN_SR_RXEMPTY_POS 4 /**< SR_RXEMPTY Position */ 169 #define MXC_F_SCN_SR_RXEMPTY ((uint32_t)(0x1UL << MXC_F_SCN_SR_RXEMPTY_POS)) /**< SR_RXEMPTY Mask */ 170 171 #define MXC_F_SCN_SR_RXFULL_POS 5 /**< SR_RXFULL Position */ 172 #define MXC_F_SCN_SR_RXFULL ((uint32_t)(0x1UL << MXC_F_SCN_SR_RXFULL_POS)) /**< SR_RXFULL Mask */ 173 174 #define MXC_F_SCN_SR_TXEMPTY_POS 6 /**< SR_TXEMPTY Position */ 175 #define MXC_F_SCN_SR_TXEMPTY ((uint32_t)(0x1UL << MXC_F_SCN_SR_TXEMPTY_POS)) /**< SR_TXEMPTY Mask */ 176 177 #define MXC_F_SCN_SR_TXFULL_POS 7 /**< SR_TXFULL Position */ 178 #define MXC_F_SCN_SR_TXFULL ((uint32_t)(0x1UL << MXC_F_SCN_SR_TXFULL_POS)) /**< SR_TXFULL Mask */ 179 180 #define MXC_F_SCN_SR_RXELT_POS 8 /**< SR_RXELT Position */ 181 #define MXC_F_SCN_SR_RXELT ((uint32_t)(0xFUL << MXC_F_SCN_SR_RXELT_POS)) /**< SR_RXELT Mask */ 182 183 #define MXC_F_SCN_SR_TXELT_POS 12 /**< SR_TXELT Position */ 184 #define MXC_F_SCN_SR_TXELT ((uint32_t)(0xFUL << MXC_F_SCN_SR_TXELT_POS)) /**< SR_TXELT Mask */ 185 186 /**@} end of group SCN_SR_Register */ 187 188 /** 189 * @ingroup scn_registers 190 * @defgroup SCN_PN SCN_PN 191 * @brief Pin Register. 192 * @{ 193 */ 194 #define MXC_F_SCN_PN_CRDRST_POS 0 /**< PN_CRDRST Position */ 195 #define MXC_F_SCN_PN_CRDRST ((uint32_t)(0x1UL << MXC_F_SCN_PN_CRDRST_POS)) /**< PN_CRDRST Mask */ 196 197 #define MXC_F_SCN_PN_CRDCLK_POS 1 /**< PN_CRDCLK Position */ 198 #define MXC_F_SCN_PN_CRDCLK ((uint32_t)(0x1UL << MXC_F_SCN_PN_CRDCLK_POS)) /**< PN_CRDCLK Mask */ 199 200 #define MXC_F_SCN_PN_CRDIO_POS 2 /**< PN_CRDIO Position */ 201 #define MXC_F_SCN_PN_CRDIO ((uint32_t)(0x1UL << MXC_F_SCN_PN_CRDIO_POS)) /**< PN_CRDIO Mask */ 202 203 #define MXC_F_SCN_PN_CRDC4_POS 3 /**< PN_CRDC4 Position */ 204 #define MXC_F_SCN_PN_CRDC4 ((uint32_t)(0x1UL << MXC_F_SCN_PN_CRDC4_POS)) /**< PN_CRDC4 Mask */ 205 206 #define MXC_F_SCN_PN_CRDC8_POS 4 /**< PN_CRDC8 Position */ 207 #define MXC_F_SCN_PN_CRDC8 ((uint32_t)(0x1UL << MXC_F_SCN_PN_CRDC8_POS)) /**< PN_CRDC8 Mask */ 208 209 #define MXC_F_SCN_PN_CLKSEL_POS 5 /**< PN_CLKSEL Position */ 210 #define MXC_F_SCN_PN_CLKSEL ((uint32_t)(0x1UL << MXC_F_SCN_PN_CLKSEL_POS)) /**< PN_CLKSEL Mask */ 211 212 #define MXC_F_SCN_PN_IO_C48_EN_POS 16 /**< PN_IO_C48_EN Position */ 213 #define MXC_F_SCN_PN_IO_C48_EN ((uint32_t)(0x1UL << MXC_F_SCN_PN_IO_C48_EN_POS)) /**< PN_IO_C48_EN Mask */ 214 215 /**@} end of group SCN_PN_Register */ 216 217 /** 218 * @ingroup scn_registers 219 * @defgroup SCN_ETUR SCN_ETUR 220 * @brief ETU Register. 221 * @{ 222 */ 223 #define MXC_F_SCN_ETUR_ETU_POS 0 /**< ETUR_ETU Position */ 224 #define MXC_F_SCN_ETUR_ETU ((uint32_t)(0x7FFFUL << MXC_F_SCN_ETUR_ETU_POS)) /**< ETUR_ETU Mask */ 225 226 #define MXC_F_SCN_ETUR_COMP_POS 15 /**< ETUR_COMP Position */ 227 #define MXC_F_SCN_ETUR_COMP ((uint32_t)(0x1UL << MXC_F_SCN_ETUR_COMP_POS)) /**< ETUR_COMP Mask */ 228 229 #define MXC_F_SCN_ETUR_HALF_POS 16 /**< ETUR_HALF Position */ 230 #define MXC_F_SCN_ETUR_HALF ((uint32_t)(0x1UL << MXC_F_SCN_ETUR_HALF_POS)) /**< ETUR_HALF Mask */ 231 232 /**@} end of group SCN_ETUR_Register */ 233 234 /** 235 * @ingroup scn_registers 236 * @defgroup SCN_GTR SCN_GTR 237 * @brief Guard Time Register. 238 * @{ 239 */ 240 #define MXC_F_SCN_GTR_GT_POS 0 /**< GTR_GT Position */ 241 #define MXC_F_SCN_GTR_GT ((uint32_t)(0xFFFFUL << MXC_F_SCN_GTR_GT_POS)) /**< GTR_GT Mask */ 242 243 /**@} end of group SCN_GTR_Register */ 244 245 /** 246 * @ingroup scn_registers 247 * @defgroup SCN_WT0R SCN_WT0R 248 * @brief Waiting Time 0 Register. 249 * @{ 250 */ 251 #define MXC_F_SCN_WT0R_WT_POS 0 /**< WT0R_WT Position */ 252 #define MXC_F_SCN_WT0R_WT ((uint32_t)(0xFFFFFFFFUL << MXC_F_SCN_WT0R_WT_POS)) /**< WT0R_WT Mask */ 253 254 /**@} end of group SCN_WT0R_Register */ 255 256 /** 257 * @ingroup scn_registers 258 * @defgroup SCN_WT1R SCN_WT1R 259 * @brief Waiting Time 1 Register. 260 * @{ 261 */ 262 #define MXC_F_SCN_WT1R_WT_POS 0 /**< WT1R_WT Position */ 263 #define MXC_F_SCN_WT1R_WT ((uint32_t)(0xFFUL << MXC_F_SCN_WT1R_WT_POS)) /**< WT1R_WT Mask */ 264 265 /**@} end of group SCN_WT1R_Register */ 266 267 /** 268 * @ingroup scn_registers 269 * @defgroup SCN_IER SCN_IER 270 * @brief Interrupt Enable Register. 271 * @{ 272 */ 273 #define MXC_F_SCN_IER_PARIE_POS 0 /**< IER_PARIE Position */ 274 #define MXC_F_SCN_IER_PARIE ((uint32_t)(0x1UL << MXC_F_SCN_IER_PARIE_POS)) /**< IER_PARIE Mask */ 275 276 #define MXC_F_SCN_IER_WTIE_POS 1 /**< IER_WTIE Position */ 277 #define MXC_F_SCN_IER_WTIE ((uint32_t)(0x1UL << MXC_F_SCN_IER_WTIE_POS)) /**< IER_WTIE Mask */ 278 279 #define MXC_F_SCN_IER_CTIE_POS 2 /**< IER_CTIE Position */ 280 #define MXC_F_SCN_IER_CTIE ((uint32_t)(0x1UL << MXC_F_SCN_IER_CTIE_POS)) /**< IER_CTIE Mask */ 281 282 #define MXC_F_SCN_IER_TCIE_POS 3 /**< IER_TCIE Position */ 283 #define MXC_F_SCN_IER_TCIE ((uint32_t)(0x1UL << MXC_F_SCN_IER_TCIE_POS)) /**< IER_TCIE Mask */ 284 285 #define MXC_F_SCN_IER_RXEIE_POS 4 /**< IER_RXEIE Position */ 286 #define MXC_F_SCN_IER_RXEIE ((uint32_t)(0x1UL << MXC_F_SCN_IER_RXEIE_POS)) /**< IER_RXEIE Mask */ 287 288 #define MXC_F_SCN_IER_RXTIE_POS 5 /**< IER_RXTIE Position */ 289 #define MXC_F_SCN_IER_RXTIE ((uint32_t)(0x1UL << MXC_F_SCN_IER_RXTIE_POS)) /**< IER_RXTIE Mask */ 290 291 #define MXC_F_SCN_IER_RXFIE_POS 6 /**< IER_RXFIE Position */ 292 #define MXC_F_SCN_IER_RXFIE ((uint32_t)(0x1UL << MXC_F_SCN_IER_RXFIE_POS)) /**< IER_RXFIE Mask */ 293 294 #define MXC_F_SCN_IER_TXEIE_POS 7 /**< IER_TXEIE Position */ 295 #define MXC_F_SCN_IER_TXEIE ((uint32_t)(0x1UL << MXC_F_SCN_IER_TXEIE_POS)) /**< IER_TXEIE Mask */ 296 297 #define MXC_F_SCN_IER_TXTIE_POS 8 /**< IER_TXTIE Position */ 298 #define MXC_F_SCN_IER_TXTIE ((uint32_t)(0x1UL << MXC_F_SCN_IER_TXTIE_POS)) /**< IER_TXTIE Mask */ 299 300 /**@} end of group SCN_IER_Register */ 301 302 /** 303 * @ingroup scn_registers 304 * @defgroup SCN_ISR SCN_ISR 305 * @brief Interrupt Status Register. 306 * @{ 307 */ 308 #define MXC_F_SCN_ISR_PARIS_POS 0 /**< ISR_PARIS Position */ 309 #define MXC_F_SCN_ISR_PARIS ((uint32_t)(0x1UL << MXC_F_SCN_ISR_PARIS_POS)) /**< ISR_PARIS Mask */ 310 311 #define MXC_F_SCN_ISR_WTIS_POS 1 /**< ISR_WTIS Position */ 312 #define MXC_F_SCN_ISR_WTIS ((uint32_t)(0x1UL << MXC_F_SCN_ISR_WTIS_POS)) /**< ISR_WTIS Mask */ 313 314 #define MXC_F_SCN_ISR_CTIS_POS 2 /**< ISR_CTIS Position */ 315 #define MXC_F_SCN_ISR_CTIS ((uint32_t)(0x1UL << MXC_F_SCN_ISR_CTIS_POS)) /**< ISR_CTIS Mask */ 316 317 #define MXC_F_SCN_ISR_TCIS_POS 3 /**< ISR_TCIS Position */ 318 #define MXC_F_SCN_ISR_TCIS ((uint32_t)(0x1UL << MXC_F_SCN_ISR_TCIS_POS)) /**< ISR_TCIS Mask */ 319 320 #define MXC_F_SCN_ISR_RXEIS_POS 4 /**< ISR_RXEIS Position */ 321 #define MXC_F_SCN_ISR_RXEIS ((uint32_t)(0x1UL << MXC_F_SCN_ISR_RXEIS_POS)) /**< ISR_RXEIS Mask */ 322 323 #define MXC_F_SCN_ISR_RXTIS_POS 5 /**< ISR_RXTIS Position */ 324 #define MXC_F_SCN_ISR_RXTIS ((uint32_t)(0x1UL << MXC_F_SCN_ISR_RXTIS_POS)) /**< ISR_RXTIS Mask */ 325 326 #define MXC_F_SCN_ISR_RXFIS_POS 6 /**< ISR_RXFIS Position */ 327 #define MXC_F_SCN_ISR_RXFIS ((uint32_t)(0x1UL << MXC_F_SCN_ISR_RXFIS_POS)) /**< ISR_RXFIS Mask */ 328 329 #define MXC_F_SCN_ISR_TXEIS_POS 7 /**< ISR_TXEIS Position */ 330 #define MXC_F_SCN_ISR_TXEIS ((uint32_t)(0x1UL << MXC_F_SCN_ISR_TXEIS_POS)) /**< ISR_TXEIS Mask */ 331 332 #define MXC_F_SCN_ISR_TXTIS_POS 8 /**< ISR_TXTIS Position */ 333 #define MXC_F_SCN_ISR_TXTIS ((uint32_t)(0x1UL << MXC_F_SCN_ISR_TXTIS_POS)) /**< ISR_TXTIS Mask */ 334 335 /**@} end of group SCN_ISR_Register */ 336 337 /** 338 * @ingroup scn_registers 339 * @defgroup SCN_TXR SCN_TXR 340 * @brief Transmit Register. 341 * @{ 342 */ 343 #define MXC_F_SCN_TXR_DATA_POS 0 /**< TXR_DATA Position */ 344 #define MXC_F_SCN_TXR_DATA ((uint32_t)(0xFFUL << MXC_F_SCN_TXR_DATA_POS)) /**< TXR_DATA Mask */ 345 346 /**@} end of group SCN_TXR_Register */ 347 348 /** 349 * @ingroup scn_registers 350 * @defgroup SCN_RXR SCN_RXR 351 * @brief Receive Register. 352 * @{ 353 */ 354 #define MXC_F_SCN_RXR_DATA_POS 0 /**< RXR_DATA Position */ 355 #define MXC_F_SCN_RXR_DATA ((uint32_t)(0xFFUL << MXC_F_SCN_RXR_DATA_POS)) /**< RXR_DATA Mask */ 356 357 #define MXC_F_SCN_RXR_PARER_POS 8 /**< RXR_PARER Position */ 358 #define MXC_F_SCN_RXR_PARER ((uint32_t)(0x1UL << MXC_F_SCN_RXR_PARER_POS)) /**< RXR_PARER Mask */ 359 360 /**@} end of group SCN_RXR_Register */ 361 362 /** 363 * @ingroup scn_registers 364 * @defgroup SCN_CCR SCN_CCR 365 * @brief Clock Counter Register. 366 * @{ 367 */ 368 #define MXC_F_SCN_CCR_CCYC_POS 0 /**< CCR_CCYC Position */ 369 #define MXC_F_SCN_CCR_CCYC ((uint32_t)(0xFFFFFFUL << MXC_F_SCN_CCR_CCYC_POS)) /**< CCR_CCYC Mask */ 370 371 #define MXC_F_SCN_CCR_MAN_POS 31 /**< CCR_MAN Position */ 372 #define MXC_F_SCN_CCR_MAN ((uint32_t)(0x1UL << MXC_F_SCN_CCR_MAN_POS)) /**< CCR_MAN Mask */ 373 374 /**@} end of group SCN_CCR_Register */ 375 376 #ifdef __cplusplus 377 } 378 #endif 379 380 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SCN_REGS_H_ 381
