1 /** 2 * @file pwrseq_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup pwrseq_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_PWRSEQ_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_PWRSEQ_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup pwrseq 67 * @defgroup pwrseq_registers PWRSEQ_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. 69 * @details Power Sequencer / Low Power Control Register. 70 */ 71 72 /** 73 * @ingroup pwrseq_registers 74 * Structure type to access the PWRSEQ Registers. 75 */ 76 typedef struct { 77 __IO uint32_t lpctrl; /**< <tt>\b 0x00:</tt> PWRSEQ LPCTRL Register */ 78 __IO uint32_t lpwkfl0; /**< <tt>\b 0x04:</tt> PWRSEQ LPWKFL0 Register */ 79 __IO uint32_t lpwken0; /**< <tt>\b 0x08:</tt> PWRSEQ LPWKEN0 Register */ 80 __IO uint32_t lpwkfl1; /**< <tt>\b 0x0C:</tt> PWRSEQ LPWKFL1 Register */ 81 __IO uint32_t lpwken1; /**< <tt>\b 0x10:</tt> PWRSEQ LPWKEN1 Register */ 82 __IO uint32_t lpwkfl2; /**< <tt>\b 0x14:</tt> PWRSEQ LPWKFL2 Register */ 83 __IO uint32_t lpwken2; /**< <tt>\b 0x18:</tt> PWRSEQ LPWKEN2 Register */ 84 __IO uint32_t lpwkfl3; /**< <tt>\b 0x1C:</tt> PWRSEQ LPWKFL3 Register */ 85 __IO uint32_t lpwken3; /**< <tt>\b 0x20:</tt> PWRSEQ LPWKEN3 Register */ 86 __R uint32_t rsv_0x24_0x2f[3]; 87 __IO uint32_t lppwkfl; /**< <tt>\b 0x30:</tt> PWRSEQ LPPWKFL Register */ 88 __IO uint32_t lppwken; /**< <tt>\b 0x34:</tt> PWRSEQ LPPWKEN Register */ 89 __R uint32_t rsv_0x38_0x3f[2]; 90 __IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */ 91 __IO uint32_t lpvddpd; /**< <tt>\b 0x44:</tt> PWRSEQ LPVDDPD Register */ 92 __IO uint32_t gp0; /**< <tt>\b 0x48:</tt> PWRSEQ GP0 Register */ 93 __IO uint32_t gp1; /**< <tt>\b 0x4C:</tt> PWRSEQ GP1 Register */ 94 } mxc_pwrseq_regs_t; 95 96 /* Register offsets for module PWRSEQ */ 97 /** 98 * @ingroup pwrseq_registers 99 * @defgroup PWRSEQ_Register_Offsets Register Offsets 100 * @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. 101 * @{ 102 */ 103 #define MXC_R_PWRSEQ_LPCTRL ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0000</tt> */ 104 #define MXC_R_PWRSEQ_LPWKFL0 ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0004</tt> */ 105 #define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0008</tt> */ 106 #define MXC_R_PWRSEQ_LPWKFL1 ((uint32_t)0x0000000CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x000C</tt> */ 107 #define MXC_R_PWRSEQ_LPWKEN1 ((uint32_t)0x00000010UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0010</tt> */ 108 #define MXC_R_PWRSEQ_LPWKFL2 ((uint32_t)0x00000014UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0014</tt> */ 109 #define MXC_R_PWRSEQ_LPWKEN2 ((uint32_t)0x00000018UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0018</tt> */ 110 #define MXC_R_PWRSEQ_LPWKFL3 ((uint32_t)0x0000001CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x001C</tt> */ 111 #define MXC_R_PWRSEQ_LPWKEN3 ((uint32_t)0x00000020UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0020</tt> */ 112 #define MXC_R_PWRSEQ_LPPWKFL ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0030</tt> */ 113 #define MXC_R_PWRSEQ_LPPWKEN ((uint32_t)0x00000034UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0034</tt> */ 114 #define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0040</tt> */ 115 #define MXC_R_PWRSEQ_LPVDDPD ((uint32_t)0x00000044UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0044</tt> */ 116 #define MXC_R_PWRSEQ_GP0 ((uint32_t)0x00000048UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0048</tt> */ 117 #define MXC_R_PWRSEQ_GP1 ((uint32_t)0x0000004CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x004C</tt> */ 118 /**@} end of group pwrseq_registers */ 119 120 /** 121 * @ingroup pwrseq_registers 122 * @defgroup PWRSEQ_LPCTRL PWRSEQ_LPCTRL 123 * @brief Low Power Control Register. 124 * @{ 125 */ 126 #define MXC_F_PWRSEQ_LPCTRL_RAMRET_EN_POS 0 /**< LPCTRL_RAMRET_EN Position */ 127 #define MXC_F_PWRSEQ_LPCTRL_RAMRET_EN ((uint32_t)(0xFUL << MXC_F_PWRSEQ_LPCTRL_RAMRET_EN_POS)) /**< LPCTRL_RAMRET_EN Mask */ 128 129 #define MXC_F_PWRSEQ_LPCTRL_OVR_POS 4 /**< LPCTRL_OVR Position */ 130 #define MXC_F_PWRSEQ_LPCTRL_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCTRL_OVR_POS)) /**< LPCTRL_OVR Mask */ 131 #define MXC_V_PWRSEQ_LPCTRL_OVR_1_1V ((uint32_t)0x2UL) /**< LPCTRL_OVR_1_1V Value */ 132 #define MXC_S_PWRSEQ_LPCTRL_OVR_1_1V (MXC_V_PWRSEQ_LPCTRL_OVR_1_1V << MXC_F_PWRSEQ_LPCTRL_OVR_POS) /**< LPCTRL_OVR_1_1V Setting */ 133 134 #define MXC_F_PWRSEQ_LPCTRL_RETREG_EN_POS 8 /**< LPCTRL_RETREG_EN Position */ 135 #define MXC_F_PWRSEQ_LPCTRL_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_RETREG_EN_POS)) /**< LPCTRL_RETREG_EN Mask */ 136 137 #define MXC_F_PWRSEQ_LPCTRL_FASTWK_EN_POS 10 /**< LPCTRL_FASTWK_EN Position */ 138 #define MXC_F_PWRSEQ_LPCTRL_FASTWK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_FASTWK_EN_POS)) /**< LPCTRL_FASTWK_EN Mask */ 139 140 #define MXC_F_PWRSEQ_LPCTRL_BGOFF_POS 11 /**< LPCTRL_BGOFF Position */ 141 #define MXC_F_PWRSEQ_LPCTRL_BGOFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_BGOFF_POS)) /**< LPCTRL_BGOFF Mask */ 142 143 #define MXC_F_PWRSEQ_LPCTRL_VCOREPOR_DIS_POS 12 /**< LPCTRL_VCOREPOR_DIS Position */ 144 #define MXC_F_PWRSEQ_LPCTRL_VCOREPOR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VCOREPOR_DIS_POS)) /**< LPCTRL_VCOREPOR_DIS Mask */ 145 146 #define MXC_F_PWRSEQ_LPCTRL_VDDIOHHVMON_DIS_POS 17 /**< LPCTRL_VDDIOHHVMON_DIS Position */ 147 #define MXC_F_PWRSEQ_LPCTRL_VDDIOHHVMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDIOHHVMON_DIS_POS)) /**< LPCTRL_VDDIOHHVMON_DIS Mask */ 148 149 #define MXC_F_PWRSEQ_LPCTRL_VDDIOHVMON_DIS_POS 18 /**< LPCTRL_VDDIOHVMON_DIS Position */ 150 #define MXC_F_PWRSEQ_LPCTRL_VDDIOHVMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDIOHVMON_DIS_POS)) /**< LPCTRL_VDDIOHVMON_DIS Mask */ 151 152 #define MXC_F_PWRSEQ_LPCTRL_VCOREHVMON_DIS_POS 19 /**< LPCTRL_VCOREHVMON_DIS Position */ 153 #define MXC_F_PWRSEQ_LPCTRL_VCOREHVMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VCOREHVMON_DIS_POS)) /**< LPCTRL_VCOREHVMON_DIS Mask */ 154 155 #define MXC_F_PWRSEQ_LPCTRL_VCOREMON_DIS_POS 20 /**< LPCTRL_VCOREMON_DIS Position */ 156 #define MXC_F_PWRSEQ_LPCTRL_VCOREMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VCOREMON_DIS_POS)) /**< LPCTRL_VCOREMON_DIS Mask */ 157 158 #define MXC_F_PWRSEQ_LPCTRL_VRTCMON_DIS_POS 21 /**< LPCTRL_VRTCMON_DIS Position */ 159 #define MXC_F_PWRSEQ_LPCTRL_VRTCMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VRTCMON_DIS_POS)) /**< LPCTRL_VRTCMON_DIS Mask */ 160 161 #define MXC_F_PWRSEQ_LPCTRL_VDDAMON_DIS_POS 22 /**< LPCTRL_VDDAMON_DIS Position */ 162 #define MXC_F_PWRSEQ_LPCTRL_VDDAMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDAMON_DIS_POS)) /**< LPCTRL_VDDAMON_DIS Mask */ 163 164 #define MXC_F_PWRSEQ_LPCTRL_VDDIOMON_DIS_POS 23 /**< LPCTRL_VDDIOMON_DIS Position */ 165 #define MXC_F_PWRSEQ_LPCTRL_VDDIOMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDIOMON_DIS_POS)) /**< LPCTRL_VDDIOMON_DIS Mask */ 166 167 #define MXC_F_PWRSEQ_LPCTRL_VDDIOHMON_DIS_POS 24 /**< LPCTRL_VDDIOHMON_DIS Position */ 168 #define MXC_F_PWRSEQ_LPCTRL_VDDIOHMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDIOHMON_DIS_POS)) /**< LPCTRL_VDDIOHMON_DIS Mask */ 169 170 #define MXC_F_PWRSEQ_LPCTRL_VDDBMON_DIS_POS 27 /**< LPCTRL_VDDBMON_DIS Position */ 171 #define MXC_F_PWRSEQ_LPCTRL_VDDBMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDBMON_DIS_POS)) /**< LPCTRL_VDDBMON_DIS Mask */ 172 173 #define MXC_F_PWRSEQ_LPCTRL_DEEPSLEEP_PDOUT_DIS_POS 30 /**< LPCTRL_DEEPSLEEP_PDOUT_DIS Position */ 174 #define MXC_F_PWRSEQ_LPCTRL_DEEPSLEEP_PDOUT_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_DEEPSLEEP_PDOUT_DIS_POS)) /**< LPCTRL_DEEPSLEEP_PDOUT_DIS Mask */ 175 176 /**@} end of group PWRSEQ_LPCTRL_Register */ 177 178 /** 179 * @ingroup pwrseq_registers 180 * @defgroup PWRSEQ_LPWKFL0 PWRSEQ_LPWKFL0 181 * @brief Low Power I/O Wakeup Status Register 0. This register indicates the low power 182 * wakeup status for GPIO0. 183 * @{ 184 */ 185 #define MXC_F_PWRSEQ_LPWKFL0_WAKEST_POS 0 /**< LPWKFL0_WAKEST Position */ 186 #define MXC_F_PWRSEQ_LPWKFL0_WAKEST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPWKFL0_WAKEST_POS)) /**< LPWKFL0_WAKEST Mask */ 187 188 /**@} end of group PWRSEQ_LPWKFL0_Register */ 189 190 /** 191 * @ingroup pwrseq_registers 192 * @defgroup PWRSEQ_LPWKEN0 PWRSEQ_LPWKEN0 193 * @brief Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup 194 * functionality for GPIO0. 195 * @{ 196 */ 197 #define MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS 0 /**< LPWKEN0_WAKEEN Position */ 198 #define MXC_F_PWRSEQ_LPWKEN0_WAKEEN ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS)) /**< LPWKEN0_WAKEEN Mask */ 199 200 /**@} end of group PWRSEQ_LPWKEN0_Register */ 201 202 /** 203 * @ingroup pwrseq_registers 204 * @defgroup PWRSEQ_LPPWKFL PWRSEQ_LPPWKFL 205 * @brief Low Power Peripheral Wakeup Status Register. 206 * @{ 207 */ 208 #define MXC_F_PWRSEQ_LPPWKFL_USBLS_POS 0 /**< LPPWKFL_USBLS Position */ 209 #define MXC_F_PWRSEQ_LPPWKFL_USBLS ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPPWKFL_USBLS_POS)) /**< LPPWKFL_USBLS Mask */ 210 211 #define MXC_F_PWRSEQ_LPPWKFL_USBVBUS_POS 2 /**< LPPWKFL_USBVBUS Position */ 212 #define MXC_F_PWRSEQ_LPPWKFL_USBVBUS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_USBVBUS_POS)) /**< LPPWKFL_USBVBUS Mask */ 213 214 #define MXC_F_PWRSEQ_LPPWKFL_CPU1_POS 3 /**< LPPWKFL_CPU1 Position */ 215 #define MXC_F_PWRSEQ_LPPWKFL_CPU1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_CPU1_POS)) /**< LPPWKFL_CPU1 Mask */ 216 217 #define MXC_F_PWRSEQ_LPPWKFL_BACKUP_POS 16 /**< LPPWKFL_BACKUP Position */ 218 #define MXC_F_PWRSEQ_LPPWKFL_BACKUP ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_BACKUP_POS)) /**< LPPWKFL_BACKUP Mask */ 219 220 #define MXC_F_PWRSEQ_LPPWKFL_RESET_POS 17 /**< LPPWKFL_RESET Position */ 221 #define MXC_F_PWRSEQ_LPPWKFL_RESET ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_RESET_POS)) /**< LPPWKFL_RESET Mask */ 222 223 #define MXC_F_PWRSEQ_LPPWKFL_DRS_EVT_POS 19 /**< LPPWKFL_DRS_EVT Position */ 224 #define MXC_F_PWRSEQ_LPPWKFL_DRS_EVT ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_DRS_EVT_POS)) /**< LPPWKFL_DRS_EVT Mask */ 225 226 /**@} end of group PWRSEQ_LPPWKFL_Register */ 227 228 /** 229 * @ingroup pwrseq_registers 230 * @defgroup PWRSEQ_LPPWKEN PWRSEQ_LPPWKEN 231 * @brief Low Power Peripheral Wakeup Enable Register. 232 * @{ 233 */ 234 #define MXC_F_PWRSEQ_LPPWKEN_USBLS_POS 0 /**< LPPWKEN_USBLS Position */ 235 #define MXC_F_PWRSEQ_LPPWKEN_USBLS ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPPWKEN_USBLS_POS)) /**< LPPWKEN_USBLS Mask */ 236 237 #define MXC_F_PWRSEQ_LPPWKEN_USBVBUS_POS 2 /**< LPPWKEN_USBVBUS Position */ 238 #define MXC_F_PWRSEQ_LPPWKEN_USBVBUS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_USBVBUS_POS)) /**< LPPWKEN_USBVBUS Mask */ 239 240 #define MXC_F_PWRSEQ_LPPWKEN_CPU1_POS 3 /**< LPPWKEN_CPU1 Position */ 241 #define MXC_F_PWRSEQ_LPPWKEN_CPU1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_CPU1_POS)) /**< LPPWKEN_CPU1 Mask */ 242 243 /**@} end of group PWRSEQ_LPPWKEN_Register */ 244 245 /** 246 * @ingroup pwrseq_registers 247 * @defgroup PWRSEQ_LPMEMSD PWRSEQ_LPMEMSD 248 * @brief Low Power Memory Shutdown Control. 249 * @{ 250 */ 251 #define MXC_F_PWRSEQ_LPMEMSD_RAM0_POS 0 /**< LPMEMSD_RAM0 Position */ 252 #define MXC_F_PWRSEQ_LPMEMSD_RAM0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM0_POS)) /**< LPMEMSD_RAM0 Mask */ 253 254 #define MXC_F_PWRSEQ_LPMEMSD_RAM1_POS 1 /**< LPMEMSD_RAM1 Position */ 255 #define MXC_F_PWRSEQ_LPMEMSD_RAM1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM1_POS)) /**< LPMEMSD_RAM1 Mask */ 256 257 #define MXC_F_PWRSEQ_LPMEMSD_RAM2_POS 2 /**< LPMEMSD_RAM2 Position */ 258 #define MXC_F_PWRSEQ_LPMEMSD_RAM2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM2_POS)) /**< LPMEMSD_RAM2 Mask */ 259 260 #define MXC_F_PWRSEQ_LPMEMSD_RAM3_POS 3 /**< LPMEMSD_RAM3 Position */ 261 #define MXC_F_PWRSEQ_LPMEMSD_RAM3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM3_POS)) /**< LPMEMSD_RAM3 Mask */ 262 263 #define MXC_F_PWRSEQ_LPMEMSD_RAM4_POS 4 /**< LPMEMSD_RAM4 Position */ 264 #define MXC_F_PWRSEQ_LPMEMSD_RAM4 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM4_POS)) /**< LPMEMSD_RAM4 Mask */ 265 266 #define MXC_F_PWRSEQ_LPMEMSD_RAM5_POS 5 /**< LPMEMSD_RAM5 Position */ 267 #define MXC_F_PWRSEQ_LPMEMSD_RAM5 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM5_POS)) /**< LPMEMSD_RAM5 Mask */ 268 269 #define MXC_F_PWRSEQ_LPMEMSD_RAM6_POS 6 /**< LPMEMSD_RAM6 Position */ 270 #define MXC_F_PWRSEQ_LPMEMSD_RAM6 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM6_POS)) /**< LPMEMSD_RAM6 Mask */ 271 272 #define MXC_F_PWRSEQ_LPMEMSD_ICCXIP_POS 8 /**< LPMEMSD_ICCXIP Position */ 273 #define MXC_F_PWRSEQ_LPMEMSD_ICCXIP ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICCXIP_POS)) /**< LPMEMSD_ICCXIP Mask */ 274 275 #define MXC_F_PWRSEQ_LPMEMSD_CRYPTO_POS 10 /**< LPMEMSD_CRYPTO Position */ 276 #define MXC_F_PWRSEQ_LPMEMSD_CRYPTO ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_CRYPTO_POS)) /**< LPMEMSD_CRYPTO Mask */ 277 278 #define MXC_F_PWRSEQ_LPMEMSD_USBFIFO_POS 11 /**< LPMEMSD_USBFIFO Position */ 279 #define MXC_F_PWRSEQ_LPMEMSD_USBFIFO ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_USBFIFO_POS)) /**< LPMEMSD_USBFIFO Mask */ 280 281 #define MXC_F_PWRSEQ_LPMEMSD_ROM0_POS 12 /**< LPMEMSD_ROM0 Position */ 282 #define MXC_F_PWRSEQ_LPMEMSD_ROM0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROM0_POS)) /**< LPMEMSD_ROM0 Mask */ 283 284 #define MXC_F_PWRSEQ_LPMEMSD_MEUMEM_POS 13 /**< LPMEMSD_MEUMEM Position */ 285 #define MXC_F_PWRSEQ_LPMEMSD_MEUMEM ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_MEUMEM_POS)) /**< LPMEMSD_MEUMEM Mask */ 286 287 #define MXC_F_PWRSEQ_LPMEMSD_ROM1_POS 15 /**< LPMEMSD_ROM1 Position */ 288 #define MXC_F_PWRSEQ_LPMEMSD_ROM1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROM1_POS)) /**< LPMEMSD_ROM1 Mask */ 289 290 /**@} end of group PWRSEQ_LPMEMSD_Register */ 291 292 #ifdef __cplusplus 293 } 294 #endif 295 296 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_PWRSEQ_REGS_H_ 297
