1 /** 2 * @file ptg_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the PTG Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup ptg_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_PTG_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_PTG_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup ptg 67 * @defgroup ptg_registers PTG_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the PTG Peripheral Module. 69 * @details Pulse Train Generation 70 */ 71 72 /** 73 * @ingroup ptg_registers 74 * Structure type to access the PTG Registers. 75 */ 76 typedef struct { 77 __IO uint32_t enable; /**< <tt>\b 0x0000:</tt> PTG ENABLE Register */ 78 __IO uint32_t resync; /**< <tt>\b 0x0004:</tt> PTG RESYNC Register */ 79 __IO uint32_t stop_intfl; /**< <tt>\b 0x0008:</tt> PTG STOP_INTFL Register */ 80 __IO uint32_t stop_inten; /**< <tt>\b 0x000C:</tt> PTG STOP_INTEN Register */ 81 __O uint32_t safe_en; /**< <tt>\b 0x0010:</tt> PTG SAFE_EN Register */ 82 __O uint32_t safe_dis; /**< <tt>\b 0x0014:</tt> PTG SAFE_DIS Register */ 83 __IO uint32_t ready_intfl; /**< <tt>\b 0x0018:</tt> PTG READY_INTFL Register */ 84 __IO uint32_t ready_inten; /**< <tt>\b 0x001C:</tt> PTG READY_INTEN Register */ 85 } mxc_ptg_regs_t; 86 87 /* Register offsets for module PTG */ 88 /** 89 * @ingroup ptg_registers 90 * @defgroup PTG_Register_Offsets Register Offsets 91 * @brief PTG Peripheral Register Offsets from the PTG Base Peripheral Address. 92 * @{ 93 */ 94 #define MXC_R_PTG_ENABLE ((uint32_t)0x00000000UL) /**< Offset from PTG Base Address: <tt> 0x0000</tt> */ 95 #define MXC_R_PTG_RESYNC ((uint32_t)0x00000004UL) /**< Offset from PTG Base Address: <tt> 0x0004</tt> */ 96 #define MXC_R_PTG_STOP_INTFL ((uint32_t)0x00000008UL) /**< Offset from PTG Base Address: <tt> 0x0008</tt> */ 97 #define MXC_R_PTG_STOP_INTEN ((uint32_t)0x0000000CUL) /**< Offset from PTG Base Address: <tt> 0x000C</tt> */ 98 #define MXC_R_PTG_SAFE_EN ((uint32_t)0x00000010UL) /**< Offset from PTG Base Address: <tt> 0x0010</tt> */ 99 #define MXC_R_PTG_SAFE_DIS ((uint32_t)0x00000014UL) /**< Offset from PTG Base Address: <tt> 0x0014</tt> */ 100 #define MXC_R_PTG_READY_INTFL ((uint32_t)0x00000018UL) /**< Offset from PTG Base Address: <tt> 0x0018</tt> */ 101 #define MXC_R_PTG_READY_INTEN ((uint32_t)0x0000001CUL) /**< Offset from PTG Base Address: <tt> 0x001C</tt> */ 102 /**@} end of group ptg_registers */ 103 104 /** 105 * @ingroup ptg_registers 106 * @defgroup PTG_ENABLE PTG_ENABLE 107 * @brief Global Enable/Disable Controls for All Pulse Trains 108 * @{ 109 */ 110 #define MXC_F_PTG_ENABLE_PT0_POS 0 /**< ENABLE_PT0 Position */ 111 #define MXC_F_PTG_ENABLE_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT0_POS)) /**< ENABLE_PT0 Mask */ 112 113 #define MXC_F_PTG_ENABLE_PT1_POS 1 /**< ENABLE_PT1 Position */ 114 #define MXC_F_PTG_ENABLE_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT1_POS)) /**< ENABLE_PT1 Mask */ 115 116 #define MXC_F_PTG_ENABLE_PT2_POS 2 /**< ENABLE_PT2 Position */ 117 #define MXC_F_PTG_ENABLE_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT2_POS)) /**< ENABLE_PT2 Mask */ 118 119 #define MXC_F_PTG_ENABLE_PT3_POS 3 /**< ENABLE_PT3 Position */ 120 #define MXC_F_PTG_ENABLE_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT3_POS)) /**< ENABLE_PT3 Mask */ 121 122 #define MXC_F_PTG_ENABLE_PT4_POS 4 /**< ENABLE_PT4 Position */ 123 #define MXC_F_PTG_ENABLE_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT4_POS)) /**< ENABLE_PT4 Mask */ 124 125 #define MXC_F_PTG_ENABLE_PT5_POS 5 /**< ENABLE_PT5 Position */ 126 #define MXC_F_PTG_ENABLE_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT5_POS)) /**< ENABLE_PT5 Mask */ 127 128 #define MXC_F_PTG_ENABLE_PT6_POS 6 /**< ENABLE_PT6 Position */ 129 #define MXC_F_PTG_ENABLE_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT6_POS)) /**< ENABLE_PT6 Mask */ 130 131 #define MXC_F_PTG_ENABLE_PT7_POS 7 /**< ENABLE_PT7 Position */ 132 #define MXC_F_PTG_ENABLE_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT7_POS)) /**< ENABLE_PT7 Mask */ 133 134 /**@} end of group PTG_ENABLE_Register */ 135 136 /** 137 * @ingroup ptg_registers 138 * @defgroup PTG_RESYNC PTG_RESYNC 139 * @brief Global Resync (All Pulse Trains) Control 140 * @{ 141 */ 142 #define MXC_F_PTG_RESYNC_PT0_POS 0 /**< RESYNC_PT0 Position */ 143 #define MXC_F_PTG_RESYNC_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT0_POS)) /**< RESYNC_PT0 Mask */ 144 145 #define MXC_F_PTG_RESYNC_PT1_POS 1 /**< RESYNC_PT1 Position */ 146 #define MXC_F_PTG_RESYNC_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT1_POS)) /**< RESYNC_PT1 Mask */ 147 148 #define MXC_F_PTG_RESYNC_PT2_POS 2 /**< RESYNC_PT2 Position */ 149 #define MXC_F_PTG_RESYNC_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT2_POS)) /**< RESYNC_PT2 Mask */ 150 151 #define MXC_F_PTG_RESYNC_PT3_POS 3 /**< RESYNC_PT3 Position */ 152 #define MXC_F_PTG_RESYNC_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT3_POS)) /**< RESYNC_PT3 Mask */ 153 154 #define MXC_F_PTG_RESYNC_PT4_POS 4 /**< RESYNC_PT4 Position */ 155 #define MXC_F_PTG_RESYNC_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT4_POS)) /**< RESYNC_PT4 Mask */ 156 157 #define MXC_F_PTG_RESYNC_PT5_POS 5 /**< RESYNC_PT5 Position */ 158 #define MXC_F_PTG_RESYNC_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT5_POS)) /**< RESYNC_PT5 Mask */ 159 160 #define MXC_F_PTG_RESYNC_PT6_POS 6 /**< RESYNC_PT6 Position */ 161 #define MXC_F_PTG_RESYNC_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT6_POS)) /**< RESYNC_PT6 Mask */ 162 163 #define MXC_F_PTG_RESYNC_PT7_POS 7 /**< RESYNC_PT7 Position */ 164 #define MXC_F_PTG_RESYNC_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT7_POS)) /**< RESYNC_PT7 Mask */ 165 166 /**@} end of group PTG_RESYNC_Register */ 167 168 /** 169 * @ingroup ptg_registers 170 * @defgroup PTG_STOP_INTFL PTG_STOP_INTFL 171 * @brief Pulse Train Stop Interrupt Flags 172 * @{ 173 */ 174 #define MXC_F_PTG_STOP_INTFL_PT0_POS 0 /**< STOP_INTFL_PT0 Position */ 175 #define MXC_F_PTG_STOP_INTFL_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT0_POS)) /**< STOP_INTFL_PT0 Mask */ 176 177 #define MXC_F_PTG_STOP_INTFL_PT1_POS 1 /**< STOP_INTFL_PT1 Position */ 178 #define MXC_F_PTG_STOP_INTFL_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT1_POS)) /**< STOP_INTFL_PT1 Mask */ 179 180 #define MXC_F_PTG_STOP_INTFL_PT2_POS 2 /**< STOP_INTFL_PT2 Position */ 181 #define MXC_F_PTG_STOP_INTFL_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT2_POS)) /**< STOP_INTFL_PT2 Mask */ 182 183 #define MXC_F_PTG_STOP_INTFL_PT3_POS 3 /**< STOP_INTFL_PT3 Position */ 184 #define MXC_F_PTG_STOP_INTFL_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT3_POS)) /**< STOP_INTFL_PT3 Mask */ 185 186 #define MXC_F_PTG_STOP_INTFL_PT4_POS 4 /**< STOP_INTFL_PT4 Position */ 187 #define MXC_F_PTG_STOP_INTFL_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT4_POS)) /**< STOP_INTFL_PT4 Mask */ 188 189 #define MXC_F_PTG_STOP_INTFL_PT5_POS 5 /**< STOP_INTFL_PT5 Position */ 190 #define MXC_F_PTG_STOP_INTFL_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT5_POS)) /**< STOP_INTFL_PT5 Mask */ 191 192 #define MXC_F_PTG_STOP_INTFL_PT6_POS 6 /**< STOP_INTFL_PT6 Position */ 193 #define MXC_F_PTG_STOP_INTFL_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT6_POS)) /**< STOP_INTFL_PT6 Mask */ 194 195 #define MXC_F_PTG_STOP_INTFL_PT7_POS 7 /**< STOP_INTFL_PT7 Position */ 196 #define MXC_F_PTG_STOP_INTFL_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT7_POS)) /**< STOP_INTFL_PT7 Mask */ 197 198 /**@} end of group PTG_STOP_INTFL_Register */ 199 200 /** 201 * @ingroup ptg_registers 202 * @defgroup PTG_STOP_INTEN PTG_STOP_INTEN 203 * @brief Pulse Train Stop Interrupt Enable/Disable 204 * @{ 205 */ 206 #define MXC_F_PTG_STOP_INTEN_PT0_POS 0 /**< STOP_INTEN_PT0 Position */ 207 #define MXC_F_PTG_STOP_INTEN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT0_POS)) /**< STOP_INTEN_PT0 Mask */ 208 209 #define MXC_F_PTG_STOP_INTEN_PT1_POS 1 /**< STOP_INTEN_PT1 Position */ 210 #define MXC_F_PTG_STOP_INTEN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT1_POS)) /**< STOP_INTEN_PT1 Mask */ 211 212 #define MXC_F_PTG_STOP_INTEN_PT2_POS 2 /**< STOP_INTEN_PT2 Position */ 213 #define MXC_F_PTG_STOP_INTEN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT2_POS)) /**< STOP_INTEN_PT2 Mask */ 214 215 #define MXC_F_PTG_STOP_INTEN_PT3_POS 3 /**< STOP_INTEN_PT3 Position */ 216 #define MXC_F_PTG_STOP_INTEN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT3_POS)) /**< STOP_INTEN_PT3 Mask */ 217 218 #define MXC_F_PTG_STOP_INTEN_PT4_POS 4 /**< STOP_INTEN_PT4 Position */ 219 #define MXC_F_PTG_STOP_INTEN_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT4_POS)) /**< STOP_INTEN_PT4 Mask */ 220 221 #define MXC_F_PTG_STOP_INTEN_PT5_POS 5 /**< STOP_INTEN_PT5 Position */ 222 #define MXC_F_PTG_STOP_INTEN_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT5_POS)) /**< STOP_INTEN_PT5 Mask */ 223 224 #define MXC_F_PTG_STOP_INTEN_PT6_POS 6 /**< STOP_INTEN_PT6 Position */ 225 #define MXC_F_PTG_STOP_INTEN_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT6_POS)) /**< STOP_INTEN_PT6 Mask */ 226 227 #define MXC_F_PTG_STOP_INTEN_PT7_POS 7 /**< STOP_INTEN_PT7 Position */ 228 #define MXC_F_PTG_STOP_INTEN_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT7_POS)) /**< STOP_INTEN_PT7 Mask */ 229 230 /**@} end of group PTG_STOP_INTEN_Register */ 231 232 /** 233 * @ingroup ptg_registers 234 * @defgroup PTG_SAFE_EN PTG_SAFE_EN 235 * @brief Pulse Train Global Safe Enable. 236 * @{ 237 */ 238 #define MXC_F_PTG_SAFE_EN_PT0_POS 0 /**< SAFE_EN_PT0 Position */ 239 #define MXC_F_PTG_SAFE_EN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT0_POS)) /**< SAFE_EN_PT0 Mask */ 240 241 #define MXC_F_PTG_SAFE_EN_PT1_POS 1 /**< SAFE_EN_PT1 Position */ 242 #define MXC_F_PTG_SAFE_EN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT1_POS)) /**< SAFE_EN_PT1 Mask */ 243 244 #define MXC_F_PTG_SAFE_EN_PT2_POS 2 /**< SAFE_EN_PT2 Position */ 245 #define MXC_F_PTG_SAFE_EN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT2_POS)) /**< SAFE_EN_PT2 Mask */ 246 247 #define MXC_F_PTG_SAFE_EN_PT3_POS 3 /**< SAFE_EN_PT3 Position */ 248 #define MXC_F_PTG_SAFE_EN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT3_POS)) /**< SAFE_EN_PT3 Mask */ 249 250 #define MXC_F_PTG_SAFE_EN_PT4_POS 4 /**< SAFE_EN_PT4 Position */ 251 #define MXC_F_PTG_SAFE_EN_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT4_POS)) /**< SAFE_EN_PT4 Mask */ 252 253 #define MXC_F_PTG_SAFE_EN_PT5_POS 5 /**< SAFE_EN_PT5 Position */ 254 #define MXC_F_PTG_SAFE_EN_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT5_POS)) /**< SAFE_EN_PT5 Mask */ 255 256 #define MXC_F_PTG_SAFE_EN_PT6_POS 6 /**< SAFE_EN_PT6 Position */ 257 #define MXC_F_PTG_SAFE_EN_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT6_POS)) /**< SAFE_EN_PT6 Mask */ 258 259 #define MXC_F_PTG_SAFE_EN_PT7_POS 7 /**< SAFE_EN_PT7 Position */ 260 #define MXC_F_PTG_SAFE_EN_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT7_POS)) /**< SAFE_EN_PT7 Mask */ 261 262 /**@} end of group PTG_SAFE_EN_Register */ 263 264 /** 265 * @ingroup ptg_registers 266 * @defgroup PTG_SAFE_DIS PTG_SAFE_DIS 267 * @brief Pulse Train Global Safe Disable. 268 * @{ 269 */ 270 #define MXC_F_PTG_SAFE_DIS_PT0_POS 0 /**< SAFE_DIS_PT0 Position */ 271 #define MXC_F_PTG_SAFE_DIS_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT0_POS)) /**< SAFE_DIS_PT0 Mask */ 272 273 #define MXC_F_PTG_SAFE_DIS_PT1_POS 1 /**< SAFE_DIS_PT1 Position */ 274 #define MXC_F_PTG_SAFE_DIS_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT1_POS)) /**< SAFE_DIS_PT1 Mask */ 275 276 #define MXC_F_PTG_SAFE_DIS_PT2_POS 2 /**< SAFE_DIS_PT2 Position */ 277 #define MXC_F_PTG_SAFE_DIS_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT2_POS)) /**< SAFE_DIS_PT2 Mask */ 278 279 #define MXC_F_PTG_SAFE_DIS_PT3_POS 3 /**< SAFE_DIS_PT3 Position */ 280 #define MXC_F_PTG_SAFE_DIS_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT3_POS)) /**< SAFE_DIS_PT3 Mask */ 281 282 #define MXC_F_PTG_SAFE_DIS_PT4_POS 4 /**< SAFE_DIS_PT4 Position */ 283 #define MXC_F_PTG_SAFE_DIS_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT4_POS)) /**< SAFE_DIS_PT4 Mask */ 284 285 #define MXC_F_PTG_SAFE_DIS_PT5_POS 5 /**< SAFE_DIS_PT5 Position */ 286 #define MXC_F_PTG_SAFE_DIS_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT5_POS)) /**< SAFE_DIS_PT5 Mask */ 287 288 #define MXC_F_PTG_SAFE_DIS_PT6_POS 6 /**< SAFE_DIS_PT6 Position */ 289 #define MXC_F_PTG_SAFE_DIS_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT6_POS)) /**< SAFE_DIS_PT6 Mask */ 290 291 #define MXC_F_PTG_SAFE_DIS_PT7_POS 7 /**< SAFE_DIS_PT7 Position */ 292 #define MXC_F_PTG_SAFE_DIS_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT7_POS)) /**< SAFE_DIS_PT7 Mask */ 293 294 /**@} end of group PTG_SAFE_DIS_Register */ 295 296 /** 297 * @ingroup ptg_registers 298 * @defgroup PTG_READY_INTFL PTG_READY_INTFL 299 * @brief Pulse Train Ready Interrupt Flags 300 * @{ 301 */ 302 #define MXC_F_PTG_READY_INTFL_PT0_POS 0 /**< READY_INTFL_PT0 Position */ 303 #define MXC_F_PTG_READY_INTFL_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT0_POS)) /**< READY_INTFL_PT0 Mask */ 304 305 #define MXC_F_PTG_READY_INTFL_PT1_POS 1 /**< READY_INTFL_PT1 Position */ 306 #define MXC_F_PTG_READY_INTFL_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT1_POS)) /**< READY_INTFL_PT1 Mask */ 307 308 #define MXC_F_PTG_READY_INTFL_PT2_POS 2 /**< READY_INTFL_PT2 Position */ 309 #define MXC_F_PTG_READY_INTFL_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT2_POS)) /**< READY_INTFL_PT2 Mask */ 310 311 #define MXC_F_PTG_READY_INTFL_PT3_POS 3 /**< READY_INTFL_PT3 Position */ 312 #define MXC_F_PTG_READY_INTFL_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT3_POS)) /**< READY_INTFL_PT3 Mask */ 313 314 #define MXC_F_PTG_READY_INTFL_PT4_POS 4 /**< READY_INTFL_PT4 Position */ 315 #define MXC_F_PTG_READY_INTFL_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT4_POS)) /**< READY_INTFL_PT4 Mask */ 316 317 #define MXC_F_PTG_READY_INTFL_PT5_POS 5 /**< READY_INTFL_PT5 Position */ 318 #define MXC_F_PTG_READY_INTFL_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT5_POS)) /**< READY_INTFL_PT5 Mask */ 319 320 #define MXC_F_PTG_READY_INTFL_PT6_POS 6 /**< READY_INTFL_PT6 Position */ 321 #define MXC_F_PTG_READY_INTFL_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT6_POS)) /**< READY_INTFL_PT6 Mask */ 322 323 #define MXC_F_PTG_READY_INTFL_PT7_POS 7 /**< READY_INTFL_PT7 Position */ 324 #define MXC_F_PTG_READY_INTFL_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT7_POS)) /**< READY_INTFL_PT7 Mask */ 325 326 /**@} end of group PTG_READY_INTFL_Register */ 327 328 /** 329 * @ingroup ptg_registers 330 * @defgroup PTG_READY_INTEN PTG_READY_INTEN 331 * @brief Pulse Train Ready Interrupt Enable/Disable 332 * @{ 333 */ 334 #define MXC_F_PTG_READY_INTEN_PT0_POS 0 /**< READY_INTEN_PT0 Position */ 335 #define MXC_F_PTG_READY_INTEN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT0_POS)) /**< READY_INTEN_PT0 Mask */ 336 337 #define MXC_F_PTG_READY_INTEN_PT1_POS 1 /**< READY_INTEN_PT1 Position */ 338 #define MXC_F_PTG_READY_INTEN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT1_POS)) /**< READY_INTEN_PT1 Mask */ 339 340 #define MXC_F_PTG_READY_INTEN_PT2_POS 2 /**< READY_INTEN_PT2 Position */ 341 #define MXC_F_PTG_READY_INTEN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT2_POS)) /**< READY_INTEN_PT2 Mask */ 342 343 #define MXC_F_PTG_READY_INTEN_PT3_POS 3 /**< READY_INTEN_PT3 Position */ 344 #define MXC_F_PTG_READY_INTEN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT3_POS)) /**< READY_INTEN_PT3 Mask */ 345 346 #define MXC_F_PTG_READY_INTEN_PT4_POS 4 /**< READY_INTEN_PT4 Position */ 347 #define MXC_F_PTG_READY_INTEN_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT4_POS)) /**< READY_INTEN_PT4 Mask */ 348 349 #define MXC_F_PTG_READY_INTEN_PT5_POS 5 /**< READY_INTEN_PT5 Position */ 350 #define MXC_F_PTG_READY_INTEN_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT5_POS)) /**< READY_INTEN_PT5 Mask */ 351 352 #define MXC_F_PTG_READY_INTEN_PT6_POS 6 /**< READY_INTEN_PT6 Position */ 353 #define MXC_F_PTG_READY_INTEN_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT6_POS)) /**< READY_INTEN_PT6 Mask */ 354 355 #define MXC_F_PTG_READY_INTEN_PT7_POS 7 /**< READY_INTEN_PT7 Position */ 356 #define MXC_F_PTG_READY_INTEN_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT7_POS)) /**< READY_INTEN_PT7 Mask */ 357 358 /**@} end of group PTG_READY_INTEN_Register */ 359 360 #ifdef __cplusplus 361 } 362 #endif 363 364 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_PTG_REGS_H_ 365
