1 /** 2 * @file pt_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the PT Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup pt_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_PT_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_PT_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup pt 67 * @defgroup pt_registers PT_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the PT Peripheral Module. 69 * @details Pulse Train 70 */ 71 72 /** 73 * @ingroup pt_registers 74 * Structure type to access the PT Registers. 75 */ 76 typedef struct { 77 __IO uint32_t rate_length; /**< <tt>\b 0x0000:</tt> PT RATE_LENGTH Register */ 78 __IO uint32_t train; /**< <tt>\b 0x0004:</tt> PT TRAIN Register */ 79 __IO uint32_t loop; /**< <tt>\b 0x0008:</tt> PT LOOP Register */ 80 __IO uint32_t restart; /**< <tt>\b 0x000C:</tt> PT RESTART Register */ 81 } mxc_pt_regs_t; 82 83 /* Register offsets for module PT */ 84 /** 85 * @ingroup pt_registers 86 * @defgroup PT_Register_Offsets Register Offsets 87 * @brief PT Peripheral Register Offsets from the PT Base Peripheral Address. 88 * @{ 89 */ 90 #define MXC_R_PT_RATE_LENGTH ((uint32_t)0x00000000UL) /**< Offset from PT Base Address: <tt> 0x0000</tt> */ 91 #define MXC_R_PT_TRAIN ((uint32_t)0x00000004UL) /**< Offset from PT Base Address: <tt> 0x0004</tt> */ 92 #define MXC_R_PT_LOOP ((uint32_t)0x00000008UL) /**< Offset from PT Base Address: <tt> 0x0008</tt> */ 93 #define MXC_R_PT_RESTART ((uint32_t)0x0000000CUL) /**< Offset from PT Base Address: <tt> 0x000C</tt> */ 94 /**@} end of group pt_registers */ 95 96 /** 97 * @ingroup pt_registers 98 * @defgroup PT_RATE_LENGTH PT_RATE_LENGTH 99 * @brief Pulse Train Configuration 100 * @{ 101 */ 102 #define MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS 0 /**< RATE_LENGTH_RATE_CONTROL Position */ 103 #define MXC_F_PT_RATE_LENGTH_RATE_CONTROL ((uint32_t)(0x7FFFFFFUL << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS)) /**< RATE_LENGTH_RATE_CONTROL Mask */ 104 105 #define MXC_F_PT_RATE_LENGTH_MODE_POS 27 /**< RATE_LENGTH_MODE Position */ 106 #define MXC_F_PT_RATE_LENGTH_MODE ((uint32_t)(0x1FUL << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< RATE_LENGTH_MODE Mask */ 107 #define MXC_V_PT_RATE_LENGTH_MODE_32_BIT ((uint32_t)0x0UL) /**< RATE_LENGTH_MODE_32_BIT Value */ 108 #define MXC_S_PT_RATE_LENGTH_MODE_32_BIT (MXC_V_PT_RATE_LENGTH_MODE_32_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_32_BIT Setting */ 109 #define MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)0x1UL) /**< RATE_LENGTH_MODE_SQUARE_WAVE Value */ 110 #define MXC_S_PT_RATE_LENGTH_MODE_SQUARE_WAVE (MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_SQUARE_WAVE Setting */ 111 #define MXC_V_PT_RATE_LENGTH_MODE_2_BIT ((uint32_t)0x2UL) /**< RATE_LENGTH_MODE_2_BIT Value */ 112 #define MXC_S_PT_RATE_LENGTH_MODE_2_BIT (MXC_V_PT_RATE_LENGTH_MODE_2_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_2_BIT Setting */ 113 #define MXC_V_PT_RATE_LENGTH_MODE_3_BIT ((uint32_t)0x3UL) /**< RATE_LENGTH_MODE_3_BIT Value */ 114 #define MXC_S_PT_RATE_LENGTH_MODE_3_BIT (MXC_V_PT_RATE_LENGTH_MODE_3_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_3_BIT Setting */ 115 #define MXC_V_PT_RATE_LENGTH_MODE_4_BIT ((uint32_t)0x4UL) /**< RATE_LENGTH_MODE_4_BIT Value */ 116 #define MXC_S_PT_RATE_LENGTH_MODE_4_BIT (MXC_V_PT_RATE_LENGTH_MODE_4_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_4_BIT Setting */ 117 #define MXC_V_PT_RATE_LENGTH_MODE_5_BIT ((uint32_t)0x5UL) /**< RATE_LENGTH_MODE_5_BIT Value */ 118 #define MXC_S_PT_RATE_LENGTH_MODE_5_BIT (MXC_V_PT_RATE_LENGTH_MODE_5_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_5_BIT Setting */ 119 #define MXC_V_PT_RATE_LENGTH_MODE_6_BIT ((uint32_t)0x6UL) /**< RATE_LENGTH_MODE_6_BIT Value */ 120 #define MXC_S_PT_RATE_LENGTH_MODE_6_BIT (MXC_V_PT_RATE_LENGTH_MODE_6_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_6_BIT Setting */ 121 #define MXC_V_PT_RATE_LENGTH_MODE_7_BIT ((uint32_t)0x7UL) /**< RATE_LENGTH_MODE_7_BIT Value */ 122 #define MXC_S_PT_RATE_LENGTH_MODE_7_BIT (MXC_V_PT_RATE_LENGTH_MODE_7_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_7_BIT Setting */ 123 #define MXC_V_PT_RATE_LENGTH_MODE_8_BIT ((uint32_t)0x8UL) /**< RATE_LENGTH_MODE_8_BIT Value */ 124 #define MXC_S_PT_RATE_LENGTH_MODE_8_BIT (MXC_V_PT_RATE_LENGTH_MODE_8_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_8_BIT Setting */ 125 #define MXC_V_PT_RATE_LENGTH_MODE_9_BIT ((uint32_t)0x9UL) /**< RATE_LENGTH_MODE_9_BIT Value */ 126 #define MXC_S_PT_RATE_LENGTH_MODE_9_BIT (MXC_V_PT_RATE_LENGTH_MODE_9_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_9_BIT Setting */ 127 #define MXC_V_PT_RATE_LENGTH_MODE_10_BIT ((uint32_t)0xAUL) /**< RATE_LENGTH_MODE_10_BIT Value */ 128 #define MXC_S_PT_RATE_LENGTH_MODE_10_BIT (MXC_V_PT_RATE_LENGTH_MODE_10_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_10_BIT Setting */ 129 #define MXC_V_PT_RATE_LENGTH_MODE_11_BIT ((uint32_t)0xBUL) /**< RATE_LENGTH_MODE_11_BIT Value */ 130 #define MXC_S_PT_RATE_LENGTH_MODE_11_BIT (MXC_V_PT_RATE_LENGTH_MODE_11_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_11_BIT Setting */ 131 #define MXC_V_PT_RATE_LENGTH_MODE_12_BIT ((uint32_t)0xCUL) /**< RATE_LENGTH_MODE_12_BIT Value */ 132 #define MXC_S_PT_RATE_LENGTH_MODE_12_BIT (MXC_V_PT_RATE_LENGTH_MODE_12_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_12_BIT Setting */ 133 #define MXC_V_PT_RATE_LENGTH_MODE_13_BIT ((uint32_t)0xDUL) /**< RATE_LENGTH_MODE_13_BIT Value */ 134 #define MXC_S_PT_RATE_LENGTH_MODE_13_BIT (MXC_V_PT_RATE_LENGTH_MODE_13_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_13_BIT Setting */ 135 #define MXC_V_PT_RATE_LENGTH_MODE_14_BIT ((uint32_t)0xEUL) /**< RATE_LENGTH_MODE_14_BIT Value */ 136 #define MXC_S_PT_RATE_LENGTH_MODE_14_BIT (MXC_V_PT_RATE_LENGTH_MODE_14_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_14_BIT Setting */ 137 #define MXC_V_PT_RATE_LENGTH_MODE_15_BIT ((uint32_t)0xFUL) /**< RATE_LENGTH_MODE_15_BIT Value */ 138 #define MXC_S_PT_RATE_LENGTH_MODE_15_BIT (MXC_V_PT_RATE_LENGTH_MODE_15_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_15_BIT Setting */ 139 #define MXC_V_PT_RATE_LENGTH_MODE_16_BIT ((uint32_t)0x10UL) /**< RATE_LENGTH_MODE_16_BIT Value */ 140 #define MXC_S_PT_RATE_LENGTH_MODE_16_BIT (MXC_V_PT_RATE_LENGTH_MODE_16_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_16_BIT Setting */ 141 #define MXC_V_PT_RATE_LENGTH_MODE_17_BIT ((uint32_t)0x11UL) /**< RATE_LENGTH_MODE_17_BIT Value */ 142 #define MXC_S_PT_RATE_LENGTH_MODE_17_BIT (MXC_V_PT_RATE_LENGTH_MODE_17_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_17_BIT Setting */ 143 #define MXC_V_PT_RATE_LENGTH_MODE_18_BIT ((uint32_t)0x12UL) /**< RATE_LENGTH_MODE_18_BIT Value */ 144 #define MXC_S_PT_RATE_LENGTH_MODE_18_BIT (MXC_V_PT_RATE_LENGTH_MODE_18_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_18_BIT Setting */ 145 #define MXC_V_PT_RATE_LENGTH_MODE_19_BIT ((uint32_t)0x13UL) /**< RATE_LENGTH_MODE_19_BIT Value */ 146 #define MXC_S_PT_RATE_LENGTH_MODE_19_BIT (MXC_V_PT_RATE_LENGTH_MODE_19_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_19_BIT Setting */ 147 #define MXC_V_PT_RATE_LENGTH_MODE_20_BIT ((uint32_t)0x14UL) /**< RATE_LENGTH_MODE_20_BIT Value */ 148 #define MXC_S_PT_RATE_LENGTH_MODE_20_BIT (MXC_V_PT_RATE_LENGTH_MODE_20_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_20_BIT Setting */ 149 #define MXC_V_PT_RATE_LENGTH_MODE_21_BIT ((uint32_t)0x15UL) /**< RATE_LENGTH_MODE_21_BIT Value */ 150 #define MXC_S_PT_RATE_LENGTH_MODE_21_BIT (MXC_V_PT_RATE_LENGTH_MODE_21_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_21_BIT Setting */ 151 #define MXC_V_PT_RATE_LENGTH_MODE_22_BIT ((uint32_t)0x16UL) /**< RATE_LENGTH_MODE_22_BIT Value */ 152 #define MXC_S_PT_RATE_LENGTH_MODE_22_BIT (MXC_V_PT_RATE_LENGTH_MODE_22_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_22_BIT Setting */ 153 #define MXC_V_PT_RATE_LENGTH_MODE_23_BIT ((uint32_t)0x17UL) /**< RATE_LENGTH_MODE_23_BIT Value */ 154 #define MXC_S_PT_RATE_LENGTH_MODE_23_BIT (MXC_V_PT_RATE_LENGTH_MODE_23_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_23_BIT Setting */ 155 #define MXC_V_PT_RATE_LENGTH_MODE_24_BIT ((uint32_t)0x18UL) /**< RATE_LENGTH_MODE_24_BIT Value */ 156 #define MXC_S_PT_RATE_LENGTH_MODE_24_BIT (MXC_V_PT_RATE_LENGTH_MODE_24_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_24_BIT Setting */ 157 #define MXC_V_PT_RATE_LENGTH_MODE_25_BIT ((uint32_t)0x19UL) /**< RATE_LENGTH_MODE_25_BIT Value */ 158 #define MXC_S_PT_RATE_LENGTH_MODE_25_BIT (MXC_V_PT_RATE_LENGTH_MODE_25_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_25_BIT Setting */ 159 #define MXC_V_PT_RATE_LENGTH_MODE_26_BIT ((uint32_t)0x1AUL) /**< RATE_LENGTH_MODE_26_BIT Value */ 160 #define MXC_S_PT_RATE_LENGTH_MODE_26_BIT (MXC_V_PT_RATE_LENGTH_MODE_26_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_26_BIT Setting */ 161 #define MXC_V_PT_RATE_LENGTH_MODE_27_BIT ((uint32_t)0x1BUL) /**< RATE_LENGTH_MODE_27_BIT Value */ 162 #define MXC_S_PT_RATE_LENGTH_MODE_27_BIT (MXC_V_PT_RATE_LENGTH_MODE_27_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_27_BIT Setting */ 163 #define MXC_V_PT_RATE_LENGTH_MODE_28_BIT ((uint32_t)0x1CUL) /**< RATE_LENGTH_MODE_28_BIT Value */ 164 #define MXC_S_PT_RATE_LENGTH_MODE_28_BIT (MXC_V_PT_RATE_LENGTH_MODE_28_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_28_BIT Setting */ 165 #define MXC_V_PT_RATE_LENGTH_MODE_29_BIT ((uint32_t)0x1DUL) /**< RATE_LENGTH_MODE_29_BIT Value */ 166 #define MXC_S_PT_RATE_LENGTH_MODE_29_BIT (MXC_V_PT_RATE_LENGTH_MODE_29_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_29_BIT Setting */ 167 #define MXC_V_PT_RATE_LENGTH_MODE_30_BIT ((uint32_t)0x1EUL) /**< RATE_LENGTH_MODE_30_BIT Value */ 168 #define MXC_S_PT_RATE_LENGTH_MODE_30_BIT (MXC_V_PT_RATE_LENGTH_MODE_30_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_30_BIT Setting */ 169 #define MXC_V_PT_RATE_LENGTH_MODE_31_BIT ((uint32_t)0x1FUL) /**< RATE_LENGTH_MODE_31_BIT Value */ 170 #define MXC_S_PT_RATE_LENGTH_MODE_31_BIT (MXC_V_PT_RATE_LENGTH_MODE_31_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_31_BIT Setting */ 171 172 /**@} end of group PT_RATE_LENGTH_Register */ 173 174 /** 175 * @ingroup pt_registers 176 * @defgroup PT_LOOP PT_LOOP 177 * @brief Pulse Train Loop Count 178 * @{ 179 */ 180 #define MXC_F_PT_LOOP_COUNT_POS 0 /**< LOOP_COUNT Position */ 181 #define MXC_F_PT_LOOP_COUNT ((uint32_t)(0xFFFFUL << MXC_F_PT_LOOP_COUNT_POS)) /**< LOOP_COUNT Mask */ 182 183 #define MXC_F_PT_LOOP_DELAY_POS 16 /**< LOOP_DELAY Position */ 184 #define MXC_F_PT_LOOP_DELAY ((uint32_t)(0xFFFUL << MXC_F_PT_LOOP_DELAY_POS)) /**< LOOP_DELAY Mask */ 185 186 /**@} end of group PT_LOOP_Register */ 187 188 /** 189 * @ingroup pt_registers 190 * @defgroup PT_RESTART PT_RESTART 191 * @brief Pulse Train Auto-Restart Configuration. 192 * @{ 193 */ 194 #define MXC_F_PT_RESTART_PT_X_SELECT_POS 0 /**< RESTART_PT_X_SELECT Position */ 195 #define MXC_F_PT_RESTART_PT_X_SELECT ((uint32_t)(0x1FUL << MXC_F_PT_RESTART_PT_X_SELECT_POS)) /**< RESTART_PT_X_SELECT Mask */ 196 197 #define MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT_POS 7 /**< RESTART_ON_PT_X_LOOP_EXIT Position */ 198 #define MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT ((uint32_t)(0x1UL << MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT_POS)) /**< RESTART_ON_PT_X_LOOP_EXIT Mask */ 199 200 #define MXC_F_PT_RESTART_PT_Y_SELECT_POS 8 /**< RESTART_PT_Y_SELECT Position */ 201 #define MXC_F_PT_RESTART_PT_Y_SELECT ((uint32_t)(0x1FUL << MXC_F_PT_RESTART_PT_Y_SELECT_POS)) /**< RESTART_PT_Y_SELECT Mask */ 202 203 #define MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT_POS 15 /**< RESTART_ON_PT_Y_LOOP_EXIT Position */ 204 #define MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT ((uint32_t)(0x1UL << MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT_POS)) /**< RESTART_ON_PT_Y_LOOP_EXIT Mask */ 205 206 /**@} end of group PT_RESTART_Register */ 207 208 #ifdef __cplusplus 209 } 210 #endif 211 212 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_PT_REGS_H_ 213
