1 /** 2 * @file otp_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the OTP Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup otp_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_OTP_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_OTP_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup otp 67 * @defgroup otp_registers OTP_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the OTP Peripheral Module. 69 * @details One-Time Programmable (OTP) Memory Controller. 70 */ 71 72 /** 73 * @ingroup otp_registers 74 * Structure type to access the OTP Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> OTP CTRL Register */ 78 __IO uint32_t clkdiv; /**< <tt>\b 0x04:</tt> OTP CLKDIV Register */ 79 __IO uint32_t rdata; /**< <tt>\b 0x08:</tt> OTP RDATA Register */ 80 __IO uint32_t status; /**< <tt>\b 0x0C:</tt> OTP STATUS Register */ 81 __R uint32_t rsv_0x10_0x2f[8]; 82 __IO uint32_t wdata; /**< <tt>\b 0x30:</tt> OTP WDATA Register */ 83 __R uint32_t rsv_0x34_0x3b[2]; 84 __IO uint32_t actrl0; /**< <tt>\b 0x3C:</tt> OTP ACTRL0 Register */ 85 __IO uint32_t actrl1; /**< <tt>\b 0x40:</tt> OTP ACTRL1 Register */ 86 } mxc_otp_regs_t; 87 88 /* Register offsets for module OTP */ 89 /** 90 * @ingroup otp_registers 91 * @defgroup OTP_Register_Offsets Register Offsets 92 * @brief OTP Peripheral Register Offsets from the OTP Base Peripheral Address. 93 * @{ 94 */ 95 #define MXC_R_OTP_CTRL ((uint32_t)0x00000000UL) /**< Offset from OTP Base Address: <tt> 0x0000</tt> */ 96 #define MXC_R_OTP_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from OTP Base Address: <tt> 0x0004</tt> */ 97 #define MXC_R_OTP_RDATA ((uint32_t)0x00000008UL) /**< Offset from OTP Base Address: <tt> 0x0008</tt> */ 98 #define MXC_R_OTP_STATUS ((uint32_t)0x0000000CUL) /**< Offset from OTP Base Address: <tt> 0x000C</tt> */ 99 #define MXC_R_OTP_WDATA ((uint32_t)0x00000030UL) /**< Offset from OTP Base Address: <tt> 0x0030</tt> */ 100 #define MXC_R_OTP_ACTRL0 ((uint32_t)0x0000003CUL) /**< Offset from OTP Base Address: <tt> 0x003C</tt> */ 101 #define MXC_R_OTP_ACTRL1 ((uint32_t)0x00000040UL) /**< Offset from OTP Base Address: <tt> 0x0040</tt> */ 102 /**@} end of group otp_registers */ 103 104 /** 105 * @ingroup otp_registers 106 * @defgroup OTP_CTRL OTP_CTRL 107 * @brief OTP Control Register. 108 * @{ 109 */ 110 #define MXC_F_OTP_CTRL_ADDR_POS 0 /**< CTRL_ADDR Position */ 111 #define MXC_F_OTP_CTRL_ADDR ((uint32_t)(0xFFFFUL << MXC_F_OTP_CTRL_ADDR_POS)) /**< CTRL_ADDR Mask */ 112 113 #define MXC_F_OTP_CTRL_READ_POS 24 /**< CTRL_READ Position */ 114 #define MXC_F_OTP_CTRL_READ ((uint32_t)(0x1UL << MXC_F_OTP_CTRL_READ_POS)) /**< CTRL_READ Mask */ 115 116 #define MXC_F_OTP_CTRL_WRITE_POS 25 /**< CTRL_WRITE Position */ 117 #define MXC_F_OTP_CTRL_WRITE ((uint32_t)(0x1UL << MXC_F_OTP_CTRL_WRITE_POS)) /**< CTRL_WRITE Mask */ 118 119 /**@} end of group OTP_CTRL_Register */ 120 121 /** 122 * @ingroup otp_registers 123 * @defgroup OTP_CLKDIV OTP_CLKDIV 124 * @brief OTP Clock Divide Register. 125 * @{ 126 */ 127 #define MXC_F_OTP_CLKDIV_PCLKDIV_POS 0 /**< CLKDIV_PCLKDIV Position */ 128 #define MXC_F_OTP_CLKDIV_PCLKDIV ((uint32_t)(0x3FUL << MXC_F_OTP_CLKDIV_PCLKDIV_POS)) /**< CLKDIV_PCLKDIV Mask */ 129 #define MXC_V_OTP_CLKDIV_PCLKDIV_DIV2 ((uint32_t)0x1UL) /**< CLKDIV_PCLKDIV_DIV2 Value */ 130 #define MXC_S_OTP_CLKDIV_PCLKDIV_DIV2 (MXC_V_OTP_CLKDIV_PCLKDIV_DIV2 << MXC_F_OTP_CLKDIV_PCLKDIV_POS) /**< CLKDIV_PCLKDIV_DIV2 Setting */ 131 #define MXC_V_OTP_CLKDIV_PCLKDIV_DIV4 ((uint32_t)0x3UL) /**< CLKDIV_PCLKDIV_DIV4 Value */ 132 #define MXC_S_OTP_CLKDIV_PCLKDIV_DIV4 (MXC_V_OTP_CLKDIV_PCLKDIV_DIV4 << MXC_F_OTP_CLKDIV_PCLKDIV_POS) /**< CLKDIV_PCLKDIV_DIV4 Setting */ 133 #define MXC_V_OTP_CLKDIV_PCLKDIV_DIV8 ((uint32_t)0x7UL) /**< CLKDIV_PCLKDIV_DIV8 Value */ 134 #define MXC_S_OTP_CLKDIV_PCLKDIV_DIV8 (MXC_V_OTP_CLKDIV_PCLKDIV_DIV8 << MXC_F_OTP_CLKDIV_PCLKDIV_POS) /**< CLKDIV_PCLKDIV_DIV8 Setting */ 135 #define MXC_V_OTP_CLKDIV_PCLKDIV_DIV16 ((uint32_t)0xFUL) /**< CLKDIV_PCLKDIV_DIV16 Value */ 136 #define MXC_S_OTP_CLKDIV_PCLKDIV_DIV16 (MXC_V_OTP_CLKDIV_PCLKDIV_DIV16 << MXC_F_OTP_CLKDIV_PCLKDIV_POS) /**< CLKDIV_PCLKDIV_DIV16 Setting */ 137 #define MXC_V_OTP_CLKDIV_PCLKDIV_DIV32 ((uint32_t)0x1FUL) /**< CLKDIV_PCLKDIV_DIV32 Value */ 138 #define MXC_S_OTP_CLKDIV_PCLKDIV_DIV32 (MXC_V_OTP_CLKDIV_PCLKDIV_DIV32 << MXC_F_OTP_CLKDIV_PCLKDIV_POS) /**< CLKDIV_PCLKDIV_DIV32 Setting */ 139 140 #define MXC_F_OTP_CLKDIV_SPWE_POS 8 /**< CLKDIV_SPWE Position */ 141 #define MXC_F_OTP_CLKDIV_SPWE ((uint32_t)(0x1UL << MXC_F_OTP_CLKDIV_SPWE_POS)) /**< CLKDIV_SPWE Mask */ 142 143 #define MXC_F_OTP_CLKDIV_PD_POS 9 /**< CLKDIV_PD Position */ 144 #define MXC_F_OTP_CLKDIV_PD ((uint32_t)(0x1UL << MXC_F_OTP_CLKDIV_PD_POS)) /**< CLKDIV_PD Mask */ 145 146 #define MXC_F_OTP_CLKDIV_HCLKDIV_POS 16 /**< CLKDIV_HCLKDIV Position */ 147 #define MXC_F_OTP_CLKDIV_HCLKDIV ((uint32_t)(0x3FUL << MXC_F_OTP_CLKDIV_HCLKDIV_POS)) /**< CLKDIV_HCLKDIV Mask */ 148 149 /**@} end of group OTP_CLKDIV_Register */ 150 151 /** 152 * @ingroup otp_registers 153 * @defgroup OTP_RDATA OTP_RDATA 154 * @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this 155 * register clears the bits in the same positions in GPIO_EN to 0, without 156 * affecting other bits in that register. 157 * @{ 158 */ 159 #define MXC_F_OTP_RDATA_DATA_POS 0 /**< RDATA_DATA Position */ 160 #define MXC_F_OTP_RDATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_OTP_RDATA_DATA_POS)) /**< RDATA_DATA Mask */ 161 162 /**@} end of group OTP_RDATA_Register */ 163 164 /** 165 * @ingroup otp_registers 166 * @defgroup OTP_STATUS OTP_STATUS 167 * @brief OTP Status Register. 168 * @{ 169 */ 170 #define MXC_F_OTP_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ 171 #define MXC_F_OTP_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_OTP_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ 172 173 #define MXC_F_OTP_STATUS_FAIL_POS 1 /**< STATUS_FAIL Position */ 174 #define MXC_F_OTP_STATUS_FAIL ((uint32_t)(0x1UL << MXC_F_OTP_STATUS_FAIL_POS)) /**< STATUS_FAIL Mask */ 175 176 #define MXC_F_OTP_STATUS_UNLOCK1_POS 8 /**< STATUS_UNLOCK1 Position */ 177 #define MXC_F_OTP_STATUS_UNLOCK1 ((uint32_t)(0x1UL << MXC_F_OTP_STATUS_UNLOCK1_POS)) /**< STATUS_UNLOCK1 Mask */ 178 179 #define MXC_F_OTP_STATUS_UNLOCK3_POS 9 /**< STATUS_UNLOCK3 Position */ 180 #define MXC_F_OTP_STATUS_UNLOCK3 ((uint32_t)(0x1UL << MXC_F_OTP_STATUS_UNLOCK3_POS)) /**< STATUS_UNLOCK3 Mask */ 181 182 #define MXC_F_OTP_STATUS_PWR_RDY_POS 16 /**< STATUS_PWR_RDY Position */ 183 #define MXC_F_OTP_STATUS_PWR_RDY ((uint32_t)(0x1UL << MXC_F_OTP_STATUS_PWR_RDY_POS)) /**< STATUS_PWR_RDY Mask */ 184 185 /**@} end of group OTP_STATUS_Register */ 186 187 /** 188 * @ingroup otp_registers 189 * @defgroup OTP_WDATA OTP_WDATA 190 * @brief OTP Write Data Register. 191 * @{ 192 */ 193 #define MXC_F_OTP_WDATA_DATA_POS 0 /**< WDATA_DATA Position */ 194 #define MXC_F_OTP_WDATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_OTP_WDATA_DATA_POS)) /**< WDATA_DATA Mask */ 195 196 /**@} end of group OTP_WDATA_Register */ 197 198 /** 199 * @ingroup otp_registers 200 * @defgroup OTP_ACTRL0 OTP_ACTRL0 201 * @brief Access Control for user block. 202 * @{ 203 */ 204 #define MXC_F_OTP_ACTRL0_ADATA_POS 0 /**< ACTRL0_ADATA Position */ 205 #define MXC_F_OTP_ACTRL0_ADATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_OTP_ACTRL0_ADATA_POS)) /**< ACTRL0_ADATA Mask */ 206 207 /**@} end of group OTP_ACTRL0_Register */ 208 209 /** 210 * @ingroup otp_registers 211 * @defgroup OTP_ACTRL1 OTP_ACTRL1 212 * @brief Access Control for sys and user block. 213 * @{ 214 */ 215 #define MXC_F_OTP_ACTRL1_ADATA_POS 0 /**< ACTRL1_ADATA Position */ 216 #define MXC_F_OTP_ACTRL1_ADATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_OTP_ACTRL1_ADATA_POS)) /**< ACTRL1_ADATA Mask */ 217 218 /**@} end of group OTP_ACTRL1_Register */ 219 220 #ifdef __cplusplus 221 } 222 #endif 223 224 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_OTP_REGS_H_ 225
