1 /** 2 * @file msradc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the MSRADC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup msradc_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_MSRADC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_MSRADC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup msradc 67 * @defgroup msradc_registers MSRADC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the MSRADC Peripheral Module. 69 * @details Magnetic Strip Reader - 9 bit ADC 70 */ 71 72 /** 73 * @ingroup msradc_registers 74 * Structure type to access the MSRADC Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> MSRADC CTRL Register */ 78 __IO uint32_t cmd; /**< <tt>\b 0x0004:</tt> MSRADC CMD Register */ 79 __IO uint32_t fifo; /**< <tt>\b 0x0008:</tt> MSRADC FIFO Register */ 80 __IO uint32_t inten; /**< <tt>\b 0x000C:</tt> MSRADC INTEN Register */ 81 __IO uint32_t intfl; /**< <tt>\b 0x0010:</tt> MSRADC INTFL Register */ 82 } mxc_msradc_regs_t; 83 84 /* Register offsets for module MSRADC */ 85 /** 86 * @ingroup msradc_registers 87 * @defgroup MSRADC_Register_Offsets Register Offsets 88 * @brief MSRADC Peripheral Register Offsets from the MSRADC Base Peripheral Address. 89 * @{ 90 */ 91 #define MXC_R_MSRADC_CTRL ((uint32_t)0x00000000UL) /**< Offset from MSRADC Base Address: <tt> 0x0000</tt> */ 92 #define MXC_R_MSRADC_CMD ((uint32_t)0x00000004UL) /**< Offset from MSRADC Base Address: <tt> 0x0004</tt> */ 93 #define MXC_R_MSRADC_FIFO ((uint32_t)0x00000008UL) /**< Offset from MSRADC Base Address: <tt> 0x0008</tt> */ 94 #define MXC_R_MSRADC_INTEN ((uint32_t)0x0000000CUL) /**< Offset from MSRADC Base Address: <tt> 0x000C</tt> */ 95 #define MXC_R_MSRADC_INTFL ((uint32_t)0x00000010UL) /**< Offset from MSRADC Base Address: <tt> 0x0010</tt> */ 96 /**@} end of group msradc_registers */ 97 98 /** 99 * @ingroup msradc_registers 100 * @defgroup MSRADC_CTRL MSRADC_CTRL 101 * @brief ADC Control 102 * @{ 103 */ 104 #define MXC_F_MSRADC_CTRL_CLKDIV_POS 0 /**< CTRL_CLKDIV Position */ 105 #define MXC_F_MSRADC_CTRL_CLKDIV ((uint32_t)(0xFFUL << MXC_F_MSRADC_CTRL_CLKDIV_POS)) /**< CTRL_CLKDIV Mask */ 106 107 #define MXC_F_MSRADC_CTRL_ACHSEL_POS 8 /**< CTRL_ACHSEL Position */ 108 #define MXC_F_MSRADC_CTRL_ACHSEL ((uint32_t)(0x7UL << MXC_F_MSRADC_CTRL_ACHSEL_POS)) /**< CTRL_ACHSEL Mask */ 109 #define MXC_V_MSRADC_CTRL_ACHSEL_INVALID ((uint32_t)0x0UL) /**< CTRL_ACHSEL_INVALID Value */ 110 #define MXC_S_MSRADC_CTRL_ACHSEL_INVALID (MXC_V_MSRADC_CTRL_ACHSEL_INVALID << MXC_F_MSRADC_CTRL_ACHSEL_POS) /**< CTRL_ACHSEL_INVALID Setting */ 111 #define MXC_V_MSRADC_CTRL_ACHSEL_CH1_IN ((uint32_t)0x1UL) /**< CTRL_ACHSEL_CH1_IN Value */ 112 #define MXC_S_MSRADC_CTRL_ACHSEL_CH1_IN (MXC_V_MSRADC_CTRL_ACHSEL_CH1_IN << MXC_F_MSRADC_CTRL_ACHSEL_POS) /**< CTRL_ACHSEL_CH1_IN Setting */ 113 #define MXC_V_MSRADC_CTRL_ACHSEL_CH2_IN ((uint32_t)0x2UL) /**< CTRL_ACHSEL_CH2_IN Value */ 114 #define MXC_S_MSRADC_CTRL_ACHSEL_CH2_IN (MXC_V_MSRADC_CTRL_ACHSEL_CH2_IN << MXC_F_MSRADC_CTRL_ACHSEL_POS) /**< CTRL_ACHSEL_CH2_IN Setting */ 115 #define MXC_V_MSRADC_CTRL_ACHSEL_CH3_IN ((uint32_t)0x3UL) /**< CTRL_ACHSEL_CH3_IN Value */ 116 #define MXC_S_MSRADC_CTRL_ACHSEL_CH3_IN (MXC_V_MSRADC_CTRL_ACHSEL_CH3_IN << MXC_F_MSRADC_CTRL_ACHSEL_POS) /**< CTRL_ACHSEL_CH3_IN Setting */ 117 118 #define MXC_F_MSRADC_CTRL_BCHSEL_POS 11 /**< CTRL_BCHSEL Position */ 119 #define MXC_F_MSRADC_CTRL_BCHSEL ((uint32_t)(0x7UL << MXC_F_MSRADC_CTRL_BCHSEL_POS)) /**< CTRL_BCHSEL Mask */ 120 121 #define MXC_F_MSRADC_CTRL_CCHSEL_POS 14 /**< CTRL_CCHSEL Position */ 122 #define MXC_F_MSRADC_CTRL_CCHSEL ((uint32_t)(0x7UL << MXC_F_MSRADC_CTRL_CCHSEL_POS)) /**< CTRL_CCHSEL Mask */ 123 124 #define MXC_F_MSRADC_CTRL_DCHSEL_POS 17 /**< CTRL_DCHSEL Position */ 125 #define MXC_F_MSRADC_CTRL_DCHSEL ((uint32_t)(0x7UL << MXC_F_MSRADC_CTRL_DCHSEL_POS)) /**< CTRL_DCHSEL Mask */ 126 127 #define MXC_F_MSRADC_CTRL_ECHSEL_POS 20 /**< CTRL_ECHSEL Position */ 128 #define MXC_F_MSRADC_CTRL_ECHSEL ((uint32_t)(0x7UL << MXC_F_MSRADC_CTRL_ECHSEL_POS)) /**< CTRL_ECHSEL Mask */ 129 130 #define MXC_F_MSRADC_CTRL_FCHSEL_POS 23 /**< CTRL_FCHSEL Position */ 131 #define MXC_F_MSRADC_CTRL_FCHSEL ((uint32_t)(0x7UL << MXC_F_MSRADC_CTRL_FCHSEL_POS)) /**< CTRL_FCHSEL Mask */ 132 133 #define MXC_F_MSRADC_CTRL_GCHSEL_POS 26 /**< CTRL_GCHSEL Position */ 134 #define MXC_F_MSRADC_CTRL_GCHSEL ((uint32_t)(0x7UL << MXC_F_MSRADC_CTRL_GCHSEL_POS)) /**< CTRL_GCHSEL Mask */ 135 136 #define MXC_F_MSRADC_CTRL_HCHSEL_POS 29 /**< CTRL_HCHSEL Position */ 137 #define MXC_F_MSRADC_CTRL_HCHSEL ((uint32_t)(0x7UL << MXC_F_MSRADC_CTRL_HCHSEL_POS)) /**< CTRL_HCHSEL Mask */ 138 139 /**@} end of group MSRADC_CTRL_Register */ 140 141 /** 142 * @ingroup msradc_registers 143 * @defgroup MSRADC_CMD MSRADC_CMD 144 * @brief MSRADC Command 145 * @{ 146 */ 147 #define MXC_F_MSRADC_CMD_RST_POS 0 /**< CMD_RST Position */ 148 #define MXC_F_MSRADC_CMD_RST ((uint32_t)(0x1UL << MXC_F_MSRADC_CMD_RST_POS)) /**< CMD_RST Mask */ 149 150 #define MXC_F_MSRADC_CMD_SNGLSMPL_POS 1 /**< CMD_SNGLSMPL Position */ 151 #define MXC_F_MSRADC_CMD_SNGLSMPL ((uint32_t)(0x1UL << MXC_F_MSRADC_CMD_SNGLSMPL_POS)) /**< CMD_SNGLSMPL Mask */ 152 153 #define MXC_F_MSRADC_CMD_CONTSMPL_POS 2 /**< CMD_CONTSMPL Position */ 154 #define MXC_F_MSRADC_CMD_CONTSMPL ((uint32_t)(0x1UL << MXC_F_MSRADC_CMD_CONTSMPL_POS)) /**< CMD_CONTSMPL Mask */ 155 156 #define MXC_F_MSRADC_CMD_ROTLIMIT_POS 4 /**< CMD_ROTLIMIT Position */ 157 #define MXC_F_MSRADC_CMD_ROTLIMIT ((uint32_t)(0x7UL << MXC_F_MSRADC_CMD_ROTLIMIT_POS)) /**< CMD_ROTLIMIT Mask */ 158 #define MXC_V_MSRADC_CMD_ROTLIMIT_1_CHANNEL ((uint32_t)0x0UL) /**< CMD_ROTLIMIT_1_CHANNEL Value */ 159 #define MXC_S_MSRADC_CMD_ROTLIMIT_1_CHANNEL (MXC_V_MSRADC_CMD_ROTLIMIT_1_CHANNEL << MXC_F_MSRADC_CMD_ROTLIMIT_POS) /**< CMD_ROTLIMIT_1_CHANNEL Setting */ 160 #define MXC_V_MSRADC_CMD_ROTLIMIT_2_CHANNELS ((uint32_t)0x1UL) /**< CMD_ROTLIMIT_2_CHANNELS Value */ 161 #define MXC_S_MSRADC_CMD_ROTLIMIT_2_CHANNELS (MXC_V_MSRADC_CMD_ROTLIMIT_2_CHANNELS << MXC_F_MSRADC_CMD_ROTLIMIT_POS) /**< CMD_ROTLIMIT_2_CHANNELS Setting */ 162 #define MXC_V_MSRADC_CMD_ROTLIMIT_3_CHANNELS ((uint32_t)0x2UL) /**< CMD_ROTLIMIT_3_CHANNELS Value */ 163 #define MXC_S_MSRADC_CMD_ROTLIMIT_3_CHANNELS (MXC_V_MSRADC_CMD_ROTLIMIT_3_CHANNELS << MXC_F_MSRADC_CMD_ROTLIMIT_POS) /**< CMD_ROTLIMIT_3_CHANNELS Setting */ 164 #define MXC_V_MSRADC_CMD_ROTLIMIT_4_CHANNELS ((uint32_t)0x3UL) /**< CMD_ROTLIMIT_4_CHANNELS Value */ 165 #define MXC_S_MSRADC_CMD_ROTLIMIT_4_CHANNELS (MXC_V_MSRADC_CMD_ROTLIMIT_4_CHANNELS << MXC_F_MSRADC_CMD_ROTLIMIT_POS) /**< CMD_ROTLIMIT_4_CHANNELS Setting */ 166 #define MXC_V_MSRADC_CMD_ROTLIMIT_5_CHANNELS ((uint32_t)0x4UL) /**< CMD_ROTLIMIT_5_CHANNELS Value */ 167 #define MXC_S_MSRADC_CMD_ROTLIMIT_5_CHANNELS (MXC_V_MSRADC_CMD_ROTLIMIT_5_CHANNELS << MXC_F_MSRADC_CMD_ROTLIMIT_POS) /**< CMD_ROTLIMIT_5_CHANNELS Setting */ 168 #define MXC_V_MSRADC_CMD_ROTLIMIT_6_CHANNELS ((uint32_t)0x5UL) /**< CMD_ROTLIMIT_6_CHANNELS Value */ 169 #define MXC_S_MSRADC_CMD_ROTLIMIT_6_CHANNELS (MXC_V_MSRADC_CMD_ROTLIMIT_6_CHANNELS << MXC_F_MSRADC_CMD_ROTLIMIT_POS) /**< CMD_ROTLIMIT_6_CHANNELS Setting */ 170 #define MXC_V_MSRADC_CMD_ROTLIMIT_7_CHANNELS ((uint32_t)0x6UL) /**< CMD_ROTLIMIT_7_CHANNELS Value */ 171 #define MXC_S_MSRADC_CMD_ROTLIMIT_7_CHANNELS (MXC_V_MSRADC_CMD_ROTLIMIT_7_CHANNELS << MXC_F_MSRADC_CMD_ROTLIMIT_POS) /**< CMD_ROTLIMIT_7_CHANNELS Setting */ 172 #define MXC_V_MSRADC_CMD_ROTLIMIT_8_CHANNELS ((uint32_t)0x7UL) /**< CMD_ROTLIMIT_8_CHANNELS Value */ 173 #define MXC_S_MSRADC_CMD_ROTLIMIT_8_CHANNELS (MXC_V_MSRADC_CMD_ROTLIMIT_8_CHANNELS << MXC_F_MSRADC_CMD_ROTLIMIT_POS) /**< CMD_ROTLIMIT_8_CHANNELS Setting */ 174 175 #define MXC_F_MSRADC_CMD_CLKSEL_POS 8 /**< CMD_CLKSEL Position */ 176 #define MXC_F_MSRADC_CMD_CLKSEL ((uint32_t)(0x7UL << MXC_F_MSRADC_CMD_CLKSEL_POS)) /**< CMD_CLKSEL Mask */ 177 #define MXC_V_MSRADC_CMD_CLKSEL_3_SAMPLES ((uint32_t)0x0UL) /**< CMD_CLKSEL_3_SAMPLES Value */ 178 #define MXC_S_MSRADC_CMD_CLKSEL_3_SAMPLES (MXC_V_MSRADC_CMD_CLKSEL_3_SAMPLES << MXC_F_MSRADC_CMD_CLKSEL_POS) /**< CMD_CLKSEL_3_SAMPLES Setting */ 179 #define MXC_V_MSRADC_CMD_CLKSEL_5_SAMPLES ((uint32_t)0x1UL) /**< CMD_CLKSEL_5_SAMPLES Value */ 180 #define MXC_S_MSRADC_CMD_CLKSEL_5_SAMPLES (MXC_V_MSRADC_CMD_CLKSEL_5_SAMPLES << MXC_F_MSRADC_CMD_CLKSEL_POS) /**< CMD_CLKSEL_5_SAMPLES Setting */ 181 #define MXC_V_MSRADC_CMD_CLKSEL_4_SAMPLES ((uint32_t)0x2UL) /**< CMD_CLKSEL_4_SAMPLES Value */ 182 #define MXC_S_MSRADC_CMD_CLKSEL_4_SAMPLES (MXC_V_MSRADC_CMD_CLKSEL_4_SAMPLES << MXC_F_MSRADC_CMD_CLKSEL_POS) /**< CMD_CLKSEL_4_SAMPLES Setting */ 183 #define MXC_V_MSRADC_CMD_CLKSEL_8_SAMPLES ((uint32_t)0x3UL) /**< CMD_CLKSEL_8_SAMPLES Value */ 184 #define MXC_S_MSRADC_CMD_CLKSEL_8_SAMPLES (MXC_V_MSRADC_CMD_CLKSEL_8_SAMPLES << MXC_F_MSRADC_CMD_CLKSEL_POS) /**< CMD_CLKSEL_8_SAMPLES Setting */ 185 #define MXC_V_MSRADC_CMD_CLKSEL_16_SAMPLES ((uint32_t)0x4UL) /**< CMD_CLKSEL_16_SAMPLES Value */ 186 #define MXC_S_MSRADC_CMD_CLKSEL_16_SAMPLES (MXC_V_MSRADC_CMD_CLKSEL_16_SAMPLES << MXC_F_MSRADC_CMD_CLKSEL_POS) /**< CMD_CLKSEL_16_SAMPLES Setting */ 187 #define MXC_V_MSRADC_CMD_CLKSEL_32_SAMPLES ((uint32_t)0x5UL) /**< CMD_CLKSEL_32_SAMPLES Value */ 188 #define MXC_S_MSRADC_CMD_CLKSEL_32_SAMPLES (MXC_V_MSRADC_CMD_CLKSEL_32_SAMPLES << MXC_F_MSRADC_CMD_CLKSEL_POS) /**< CMD_CLKSEL_32_SAMPLES Setting */ 189 #define MXC_V_MSRADC_CMD_CLKSEL_64_SAMPLES ((uint32_t)0x6UL) /**< CMD_CLKSEL_64_SAMPLES Value */ 190 #define MXC_S_MSRADC_CMD_CLKSEL_64_SAMPLES (MXC_V_MSRADC_CMD_CLKSEL_64_SAMPLES << MXC_F_MSRADC_CMD_CLKSEL_POS) /**< CMD_CLKSEL_64_SAMPLES Setting */ 191 #define MXC_V_MSRADC_CMD_CLKSEL_128_SAMPLES ((uint32_t)0x7UL) /**< CMD_CLKSEL_128_SAMPLES Value */ 192 #define MXC_S_MSRADC_CMD_CLKSEL_128_SAMPLES (MXC_V_MSRADC_CMD_CLKSEL_128_SAMPLES << MXC_F_MSRADC_CMD_CLKSEL_POS) /**< CMD_CLKSEL_128_SAMPLES Setting */ 193 194 /**@} end of group MSRADC_CMD_Register */ 195 196 /** 197 * @ingroup msradc_registers 198 * @defgroup MSRADC_FIFO MSRADC_FIFO 199 * @brief ADC FIFO 200 * @{ 201 */ 202 #define MXC_F_MSRADC_FIFO_SAMPLE_POS 0 /**< FIFO_SAMPLE Position */ 203 #define MXC_F_MSRADC_FIFO_SAMPLE ((uint32_t)(0x1FFUL << MXC_F_MSRADC_FIFO_SAMPLE_POS)) /**< FIFO_SAMPLE Mask */ 204 205 #define MXC_F_MSRADC_FIFO_INPUT_POS 9 /**< FIFO_INPUT Position */ 206 #define MXC_F_MSRADC_FIFO_INPUT ((uint32_t)(0x7UL << MXC_F_MSRADC_FIFO_INPUT_POS)) /**< FIFO_INPUT Mask */ 207 #define MXC_V_MSRADC_FIFO_INPUT_INVALID ((uint32_t)0x0UL) /**< FIFO_INPUT_INVALID Value */ 208 #define MXC_S_MSRADC_FIFO_INPUT_INVALID (MXC_V_MSRADC_FIFO_INPUT_INVALID << MXC_F_MSRADC_FIFO_INPUT_POS) /**< FIFO_INPUT_INVALID Setting */ 209 #define MXC_V_MSRADC_FIFO_INPUT_CH1_IN ((uint32_t)0x1UL) /**< FIFO_INPUT_CH1_IN Value */ 210 #define MXC_S_MSRADC_FIFO_INPUT_CH1_IN (MXC_V_MSRADC_FIFO_INPUT_CH1_IN << MXC_F_MSRADC_FIFO_INPUT_POS) /**< FIFO_INPUT_CH1_IN Setting */ 211 #define MXC_V_MSRADC_FIFO_INPUT_CH2_IN ((uint32_t)0x2UL) /**< FIFO_INPUT_CH2_IN Value */ 212 #define MXC_S_MSRADC_FIFO_INPUT_CH2_IN (MXC_V_MSRADC_FIFO_INPUT_CH2_IN << MXC_F_MSRADC_FIFO_INPUT_POS) /**< FIFO_INPUT_CH2_IN Setting */ 213 #define MXC_V_MSRADC_FIFO_INPUT_CH3_IN ((uint32_t)0x3UL) /**< FIFO_INPUT_CH3_IN Value */ 214 #define MXC_S_MSRADC_FIFO_INPUT_CH3_IN (MXC_V_MSRADC_FIFO_INPUT_CH3_IN << MXC_F_MSRADC_FIFO_INPUT_POS) /**< FIFO_INPUT_CH3_IN Setting */ 215 #define MXC_V_MSRADC_FIFO_INPUT_CH4_IN ((uint32_t)0x4UL) /**< FIFO_INPUT_CH4_IN Value */ 216 #define MXC_S_MSRADC_FIFO_INPUT_CH4_IN (MXC_V_MSRADC_FIFO_INPUT_CH4_IN << MXC_F_MSRADC_FIFO_INPUT_POS) /**< FIFO_INPUT_CH4_IN Setting */ 217 #define MXC_V_MSRADC_FIFO_INPUT_CH5_IN ((uint32_t)0x5UL) /**< FIFO_INPUT_CH5_IN Value */ 218 #define MXC_S_MSRADC_FIFO_INPUT_CH5_IN (MXC_V_MSRADC_FIFO_INPUT_CH5_IN << MXC_F_MSRADC_FIFO_INPUT_POS) /**< FIFO_INPUT_CH5_IN Setting */ 219 #define MXC_V_MSRADC_FIFO_INPUT_CH6_IN ((uint32_t)0x6UL) /**< FIFO_INPUT_CH6_IN Value */ 220 #define MXC_S_MSRADC_FIFO_INPUT_CH6_IN (MXC_V_MSRADC_FIFO_INPUT_CH6_IN << MXC_F_MSRADC_FIFO_INPUT_POS) /**< FIFO_INPUT_CH6_IN Setting */ 221 #define MXC_V_MSRADC_FIFO_INPUT_CH7_IN ((uint32_t)0x7UL) /**< FIFO_INPUT_CH7_IN Value */ 222 #define MXC_S_MSRADC_FIFO_INPUT_CH7_IN (MXC_V_MSRADC_FIFO_INPUT_CH7_IN << MXC_F_MSRADC_FIFO_INPUT_POS) /**< FIFO_INPUT_CH7_IN Setting */ 223 224 #define MXC_F_MSRADC_FIFO_INCOMPLETE_POS 12 /**< FIFO_INCOMPLETE Position */ 225 #define MXC_F_MSRADC_FIFO_INCOMPLETE ((uint32_t)(0x1UL << MXC_F_MSRADC_FIFO_INCOMPLETE_POS)) /**< FIFO_INCOMPLETE Mask */ 226 227 /**@} end of group MSRADC_FIFO_Register */ 228 229 /** 230 * @ingroup msradc_registers 231 * @defgroup MSRADC_INTEN MSRADC_INTEN 232 * @brief ADC Interrupt Enable Register 233 * @{ 234 */ 235 #define MXC_F_MSRADC_INTEN_SET_FIFOLVL_POS 0 /**< INTEN_SET_FIFOLVL Position */ 236 #define MXC_F_MSRADC_INTEN_SET_FIFOLVL ((uint32_t)(0x1FUL << MXC_F_MSRADC_INTEN_SET_FIFOLVL_POS)) /**< INTEN_SET_FIFOLVL Mask */ 237 #define MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_1 ((uint32_t)0x0UL) /**< INTEN_SET_FIFOLVL_AT_LEAST_1 Value */ 238 #define MXC_S_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_1 (MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_1 << MXC_F_MSRADC_INTEN_SET_FIFOLVL_POS) /**< INTEN_SET_FIFOLVL_AT_LEAST_1 Setting */ 239 #define MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_2 ((uint32_t)0x1UL) /**< INTEN_SET_FIFOLVL_AT_LEAST_2 Value */ 240 #define MXC_S_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_2 (MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_2 << MXC_F_MSRADC_INTEN_SET_FIFOLVL_POS) /**< INTEN_SET_FIFOLVL_AT_LEAST_2 Setting */ 241 #define MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_3 ((uint32_t)0x2UL) /**< INTEN_SET_FIFOLVL_AT_LEAST_3 Value */ 242 #define MXC_S_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_3 (MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_3 << MXC_F_MSRADC_INTEN_SET_FIFOLVL_POS) /**< INTEN_SET_FIFOLVL_AT_LEAST_3 Setting */ 243 #define MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_4 ((uint32_t)0x3UL) /**< INTEN_SET_FIFOLVL_AT_LEAST_4 Value */ 244 #define MXC_S_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_4 (MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_4 << MXC_F_MSRADC_INTEN_SET_FIFOLVL_POS) /**< INTEN_SET_FIFOLVL_AT_LEAST_4 Setting */ 245 #define MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_5 ((uint32_t)0x4UL) /**< INTEN_SET_FIFOLVL_AT_LEAST_5 Value */ 246 #define MXC_S_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_5 (MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_5 << MXC_F_MSRADC_INTEN_SET_FIFOLVL_POS) /**< INTEN_SET_FIFOLVL_AT_LEAST_5 Setting */ 247 #define MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_6 ((uint32_t)0x5UL) /**< INTEN_SET_FIFOLVL_AT_LEAST_6 Value */ 248 #define MXC_S_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_6 (MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_6 << MXC_F_MSRADC_INTEN_SET_FIFOLVL_POS) /**< INTEN_SET_FIFOLVL_AT_LEAST_6 Setting */ 249 #define MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_7 ((uint32_t)0x6UL) /**< INTEN_SET_FIFOLVL_AT_LEAST_7 Value */ 250 #define MXC_S_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_7 (MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_7 << MXC_F_MSRADC_INTEN_SET_FIFOLVL_POS) /**< INTEN_SET_FIFOLVL_AT_LEAST_7 Setting */ 251 #define MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_8 ((uint32_t)0x7UL) /**< INTEN_SET_FIFOLVL_AT_LEAST_8 Value */ 252 #define MXC_S_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_8 (MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_8 << MXC_F_MSRADC_INTEN_SET_FIFOLVL_POS) /**< INTEN_SET_FIFOLVL_AT_LEAST_8 Setting */ 253 #define MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_9 ((uint32_t)0x8UL) /**< INTEN_SET_FIFOLVL_AT_LEAST_9 Value */ 254 #define MXC_S_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_9 (MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_9 << MXC_F_MSRADC_INTEN_SET_FIFOLVL_POS) /**< INTEN_SET_FIFOLVL_AT_LEAST_9 Setting */ 255 #define MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_10 ((uint32_t)0x9UL) /**< INTEN_SET_FIFOLVL_AT_LEAST_10 Value */ 256 #define MXC_S_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_10 (MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_10 << MXC_F_MSRADC_INTEN_SET_FIFOLVL_POS) /**< INTEN_SET_FIFOLVL_AT_LEAST_10 Setting */ 257 #define MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_11 ((uint32_t)0xAUL) /**< INTEN_SET_FIFOLVL_AT_LEAST_11 Value */ 258 #define MXC_S_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_11 (MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_11 << MXC_F_MSRADC_INTEN_SET_FIFOLVL_POS) /**< INTEN_SET_FIFOLVL_AT_LEAST_11 Setting */ 259 #define MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_12 ((uint32_t)0xBUL) /**< INTEN_SET_FIFOLVL_AT_LEAST_12 Value */ 260 #define MXC_S_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_12 (MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_12 << MXC_F_MSRADC_INTEN_SET_FIFOLVL_POS) /**< INTEN_SET_FIFOLVL_AT_LEAST_12 Setting */ 261 #define MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_13 ((uint32_t)0xCUL) /**< INTEN_SET_FIFOLVL_AT_LEAST_13 Value */ 262 #define MXC_S_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_13 (MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_13 << MXC_F_MSRADC_INTEN_SET_FIFOLVL_POS) /**< INTEN_SET_FIFOLVL_AT_LEAST_13 Setting */ 263 #define MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_14 ((uint32_t)0xDUL) /**< INTEN_SET_FIFOLVL_AT_LEAST_14 Value */ 264 #define MXC_S_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_14 (MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_14 << MXC_F_MSRADC_INTEN_SET_FIFOLVL_POS) /**< INTEN_SET_FIFOLVL_AT_LEAST_14 Setting */ 265 #define MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_15 ((uint32_t)0xEUL) /**< INTEN_SET_FIFOLVL_AT_LEAST_15 Value */ 266 #define MXC_S_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_15 (MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_15 << MXC_F_MSRADC_INTEN_SET_FIFOLVL_POS) /**< INTEN_SET_FIFOLVL_AT_LEAST_15 Setting */ 267 #define MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_16 ((uint32_t)0xFUL) /**< INTEN_SET_FIFOLVL_AT_LEAST_16 Value */ 268 #define MXC_S_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_16 (MXC_V_MSRADC_INTEN_SET_FIFOLVL_AT_LEAST_16 << MXC_F_MSRADC_INTEN_SET_FIFOLVL_POS) /**< INTEN_SET_FIFOLVL_AT_LEAST_16 Setting */ 269 270 #define MXC_F_MSRADC_INTEN_DMAREQ_POS 5 /**< INTEN_DMAREQ Position */ 271 #define MXC_F_MSRADC_INTEN_DMAREQ ((uint32_t)(0x1UL << MXC_F_MSRADC_INTEN_DMAREQ_POS)) /**< INTEN_DMAREQ Mask */ 272 273 #define MXC_F_MSRADC_INTEN_FIFO_OV_POS 6 /**< INTEN_FIFO_OV Position */ 274 #define MXC_F_MSRADC_INTEN_FIFO_OV ((uint32_t)(0x1UL << MXC_F_MSRADC_INTEN_FIFO_OV_POS)) /**< INTEN_FIFO_OV Mask */ 275 276 #define MXC_F_MSRADC_INTEN_FIFO_UN_POS 7 /**< INTEN_FIFO_UN Position */ 277 #define MXC_F_MSRADC_INTEN_FIFO_UN ((uint32_t)(0x1UL << MXC_F_MSRADC_INTEN_FIFO_UN_POS)) /**< INTEN_FIFO_UN Mask */ 278 279 #define MXC_F_MSRADC_INTEN_FIFO_LVL_POS 8 /**< INTEN_FIFO_LVL Position */ 280 #define MXC_F_MSRADC_INTEN_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_MSRADC_INTEN_FIFO_LVL_POS)) /**< INTEN_FIFO_LVL Mask */ 281 282 #define MXC_F_MSRADC_INTEN_GLOBAL_POS 9 /**< INTEN_GLOBAL Position */ 283 #define MXC_F_MSRADC_INTEN_GLOBAL ((uint32_t)(0x1UL << MXC_F_MSRADC_INTEN_GLOBAL_POS)) /**< INTEN_GLOBAL Mask */ 284 285 /**@} end of group MSRADC_INTEN_Register */ 286 287 /** 288 * @ingroup msradc_registers 289 * @defgroup MSRADC_INTFL MSRADC_INTFL 290 * @brief ADC Interrupt Flag Register. 291 * @{ 292 */ 293 #define MXC_F_MSRADC_INTFL_FIFOCNT_POS 0 /**< INTFL_FIFOCNT Position */ 294 #define MXC_F_MSRADC_INTFL_FIFOCNT ((uint32_t)(0x3FUL << MXC_F_MSRADC_INTFL_FIFOCNT_POS)) /**< INTFL_FIFOCNT Mask */ 295 296 #define MXC_F_MSRADC_INTFL_FIFO_FULL_ST_POS 6 /**< INTFL_FIFO_FULL_ST Position */ 297 #define MXC_F_MSRADC_INTFL_FIFO_FULL_ST ((uint32_t)(0x1UL << MXC_F_MSRADC_INTFL_FIFO_FULL_ST_POS)) /**< INTFL_FIFO_FULL_ST Mask */ 298 299 #define MXC_F_MSRADC_INTFL_FIFO_EM_ST_POS 7 /**< INTFL_FIFO_EM_ST Position */ 300 #define MXC_F_MSRADC_INTFL_FIFO_EM_ST ((uint32_t)(0x1UL << MXC_F_MSRADC_INTFL_FIFO_EM_ST_POS)) /**< INTFL_FIFO_EM_ST Mask */ 301 302 #define MXC_F_MSRADC_INTFL_FIFO_OV_POS 8 /**< INTFL_FIFO_OV Position */ 303 #define MXC_F_MSRADC_INTFL_FIFO_OV ((uint32_t)(0x1UL << MXC_F_MSRADC_INTFL_FIFO_OV_POS)) /**< INTFL_FIFO_OV Mask */ 304 305 #define MXC_F_MSRADC_INTFL_FIFO_UN_POS 9 /**< INTFL_FIFO_UN Position */ 306 #define MXC_F_MSRADC_INTFL_FIFO_UN ((uint32_t)(0x1UL << MXC_F_MSRADC_INTFL_FIFO_UN_POS)) /**< INTFL_FIFO_UN Mask */ 307 308 #define MXC_F_MSRADC_INTFL_FIFO_LVL_POS 10 /**< INTFL_FIFO_LVL Position */ 309 #define MXC_F_MSRADC_INTFL_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_MSRADC_INTFL_FIFO_LVL_POS)) /**< INTFL_FIFO_LVL Mask */ 310 311 #define MXC_F_MSRADC_INTFL_GLOBAL_POS 11 /**< INTFL_GLOBAL Position */ 312 #define MXC_F_MSRADC_INTFL_GLOBAL ((uint32_t)(0x1UL << MXC_F_MSRADC_INTFL_GLOBAL_POS)) /**< INTFL_GLOBAL Mask */ 313 314 /**@} end of group MSRADC_INTFL_Register */ 315 316 #ifdef __cplusplus 317 } 318 #endif 319 320 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_MSRADC_REGS_H_ 321
