1 /** 2 * @file mcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup mcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_MCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_MCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup mcr 67 * @defgroup mcr_registers MCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. 69 * @details Misc Control. 70 */ 71 72 /** 73 * @ingroup mcr_registers 74 * Structure type to access the MCR Registers. 75 */ 76 typedef struct { 77 __R uint32_t rsv_0x0_0x7[2]; 78 __IO uint32_t pdown; /**< <tt>\b 0x08:</tt> MCR PDOWN Register */ 79 __R uint32_t rsv_0xc; 80 __IO uint32_t ctrl; /**< <tt>\b 0x10:</tt> MCR CTRL Register */ 81 __IO uint32_t clkctrl; /**< <tt>\b 0x14:</tt> MCR CLKCTRL Register */ 82 __IO uint32_t rst; /**< <tt>\b 0x18:</tt> MCR RST Register */ 83 __IO uint32_t rtctrim; /**< <tt>\b 0x1C:</tt> MCR RTCTRIM Register */ 84 __R uint32_t rsv_0x20_0x5f[16]; 85 __IO uint32_t ldoctrl; /**< <tt>\b 0x60:</tt> MCR LDOCTRL Register */ 86 __IO uint32_t pwrmonst; /**< <tt>\b 0x64:</tt> MCR PWRMONST Register */ 87 } mxc_mcr_regs_t; 88 89 /* Register offsets for module MCR */ 90 /** 91 * @ingroup mcr_registers 92 * @defgroup MCR_Register_Offsets Register Offsets 93 * @brief MCR Peripheral Register Offsets from the MCR Base Peripheral Address. 94 * @{ 95 */ 96 #define MXC_R_MCR_PDOWN ((uint32_t)0x00000008UL) /**< Offset from MCR Base Address: <tt> 0x0008</tt> */ 97 #define MXC_R_MCR_CTRL ((uint32_t)0x00000010UL) /**< Offset from MCR Base Address: <tt> 0x0010</tt> */ 98 #define MXC_R_MCR_CLKCTRL ((uint32_t)0x00000014UL) /**< Offset from MCR Base Address: <tt> 0x0014</tt> */ 99 #define MXC_R_MCR_RST ((uint32_t)0x00000018UL) /**< Offset from MCR Base Address: <tt> 0x0018</tt> */ 100 #define MXC_R_MCR_RTCTRIM ((uint32_t)0x0000001CUL) /**< Offset from MCR Base Address: <tt> 0x001C</tt> */ 101 #define MXC_R_MCR_LDOCTRL ((uint32_t)0x00000060UL) /**< Offset from MCR Base Address: <tt> 0x0060</tt> */ 102 #define MXC_R_MCR_PWRMONST ((uint32_t)0x00000064UL) /**< Offset from MCR Base Address: <tt> 0x0064</tt> */ 103 /**@} end of group mcr_registers */ 104 105 /** 106 * @ingroup mcr_registers 107 * @defgroup MCR_PDOWN MCR_PDOWN 108 * @brief PDOWN Drive Strength 109 * @{ 110 */ 111 #define MXC_F_MCR_PDOWN_PDOWNDS_POS 0 /**< PDOWN_PDOWNDS Position */ 112 #define MXC_F_MCR_PDOWN_PDOWNDS ((uint32_t)(0x3UL << MXC_F_MCR_PDOWN_PDOWNDS_POS)) /**< PDOWN_PDOWNDS Mask */ 113 114 #define MXC_F_MCR_PDOWN_PDOWNVS_POS 2 /**< PDOWN_PDOWNVS Position */ 115 #define MXC_F_MCR_PDOWN_PDOWNVS ((uint32_t)(0x1UL << MXC_F_MCR_PDOWN_PDOWNVS_POS)) /**< PDOWN_PDOWNVS Mask */ 116 117 /**@} end of group MCR_PDOWN_Register */ 118 119 /** 120 * @ingroup mcr_registers 121 * @defgroup MCR_CTRL MCR_CTRL 122 * @brief Misc Power State Control Register 123 * @{ 124 */ 125 #define MXC_F_MCR_CTRL_VDDCSW_POS 1 /**< CTRL_VDDCSW Position */ 126 #define MXC_F_MCR_CTRL_VDDCSW ((uint32_t)(0x3UL << MXC_F_MCR_CTRL_VDDCSW_POS)) /**< CTRL_VDDCSW Mask */ 127 128 #define MXC_F_MCR_CTRL_USBSWEN_N_POS 3 /**< CTRL_USBSWEN_N Position */ 129 #define MXC_F_MCR_CTRL_USBSWEN_N ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_USBSWEN_N_POS)) /**< CTRL_USBSWEN_N Mask */ 130 131 #define MXC_F_MCR_CTRL_P1M_POS 9 /**< CTRL_P1M Position */ 132 #define MXC_F_MCR_CTRL_P1M ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_P1M_POS)) /**< CTRL_P1M Mask */ 133 134 #define MXC_F_MCR_CTRL_RSTN_VOLTAGE_SEL_POS 10 /**< CTRL_RSTN_VOLTAGE_SEL Position */ 135 #define MXC_F_MCR_CTRL_RSTN_VOLTAGE_SEL ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_RSTN_VOLTAGE_SEL_POS)) /**< CTRL_RSTN_VOLTAGE_SEL Mask */ 136 137 /**@} end of group MCR_CTRL_Register */ 138 139 /** 140 * @ingroup mcr_registers 141 * @defgroup MCR_CLKCTRL MCR_CLKCTRL 142 * @brief Clock Control Register. 143 * @{ 144 */ 145 #define MXC_F_MCR_CLKCTRL_ERTCO_PD_POS 16 /**< CLKCTRL_ERTCO_PD Position */ 146 #define MXC_F_MCR_CLKCTRL_ERTCO_PD ((uint32_t)(0x1UL << MXC_F_MCR_CLKCTRL_ERTCO_PD_POS)) /**< CLKCTRL_ERTCO_PD Mask */ 147 148 #define MXC_F_MCR_CLKCTRL_ERTCO_EN_POS 17 /**< CLKCTRL_ERTCO_EN Position */ 149 #define MXC_F_MCR_CLKCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CLKCTRL_ERTCO_EN_POS)) /**< CLKCTRL_ERTCO_EN Mask */ 150 151 /**@} end of group MCR_CLKCTRL_Register */ 152 153 /** 154 * @ingroup mcr_registers 155 * @defgroup MCR_RST MCR_RST 156 * @brief Reset Register. 157 * @{ 158 */ 159 #define MXC_F_MCR_RST_RTC_POS 0 /**< RST_RTC Position */ 160 #define MXC_F_MCR_RST_RTC ((uint32_t)(0x1UL << MXC_F_MCR_RST_RTC_POS)) /**< RST_RTC Mask */ 161 162 /**@} end of group MCR_RST_Register */ 163 164 /** 165 * @ingroup mcr_registers 166 * @defgroup MCR_RTCTRIM MCR_RTCTRIM 167 * @brief RTC Trim Register. 168 * @{ 169 */ 170 #define MXC_F_MCR_RTCTRIM_TRIM_X1_POS 0 /**< RTCTRIM_TRIM_X1 Position */ 171 #define MXC_F_MCR_RTCTRIM_TRIM_X1 ((uint32_t)(0x1FUL << MXC_F_MCR_RTCTRIM_TRIM_X1_POS)) /**< RTCTRIM_TRIM_X1 Mask */ 172 173 #define MXC_F_MCR_RTCTRIM_TRIM_X2_POS 8 /**< RTCTRIM_TRIM_X2 Position */ 174 #define MXC_F_MCR_RTCTRIM_TRIM_X2 ((uint32_t)(0x1FUL << MXC_F_MCR_RTCTRIM_TRIM_X2_POS)) /**< RTCTRIM_TRIM_X2 Mask */ 175 176 /**@} end of group MCR_RTCTRIM_Register */ 177 178 /** 179 * @ingroup mcr_registers 180 * @defgroup MCR_LDOCTRL MCR_LDOCTRL 181 * @brief LDO Control Register. 182 * @{ 183 */ 184 #define MXC_F_MCR_LDOCTRL_0P9V_EN_POS 0 /**< LDOCTRL_0P9V_EN Position */ 185 #define MXC_F_MCR_LDOCTRL_0P9V_EN ((uint32_t)(0x1UL << MXC_F_MCR_LDOCTRL_0P9V_EN_POS)) /**< LDOCTRL_0P9V_EN Mask */ 186 187 /**@} end of group MCR_LDOCTRL_Register */ 188 189 /** 190 * @ingroup mcr_registers 191 * @defgroup MCR_PWRMONST MCR_PWRMONST 192 * @brief Power Monitor Statuses Register. 193 * @{ 194 */ 195 #define MXC_F_MCR_PWRMONST_PORZ_VLOSS_POS 0 /**< PWRMONST_PORZ_VLOSS Position */ 196 #define MXC_F_MCR_PWRMONST_PORZ_VLOSS ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VLOSS_POS)) /**< PWRMONST_PORZ_VLOSS Mask */ 197 198 #define MXC_F_MCR_PWRMONST_PORZ_VBAT_POS 1 /**< PWRMONST_PORZ_VBAT Position */ 199 #define MXC_F_MCR_PWRMONST_PORZ_VBAT ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VBAT_POS)) /**< PWRMONST_PORZ_VBAT Mask */ 200 201 #define MXC_F_MCR_PWRMONST_PORZ_VRTC_POS 2 /**< PWRMONST_PORZ_VRTC Position */ 202 #define MXC_F_MCR_PWRMONST_PORZ_VRTC ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VRTC_POS)) /**< PWRMONST_PORZ_VRTC Mask */ 203 204 #define MXC_F_MCR_PWRMONST_PORZ_VDDC_POS 5 /**< PWRMONST_PORZ_VDDC Position */ 205 #define MXC_F_MCR_PWRMONST_PORZ_VDDC ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VDDC_POS)) /**< PWRMONST_PORZ_VDDC Mask */ 206 207 #define MXC_F_MCR_PWRMONST_PORZ_VDDA_POS 6 /**< PWRMONST_PORZ_VDDA Position */ 208 #define MXC_F_MCR_PWRMONST_PORZ_VDDA ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VDDA_POS)) /**< PWRMONST_PORZ_VDDA Mask */ 209 210 #define MXC_F_MCR_PWRMONST_PORZ_VDDB_POS 7 /**< PWRMONST_PORZ_VDDB Position */ 211 #define MXC_F_MCR_PWRMONST_PORZ_VDDB ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VDDB_POS)) /**< PWRMONST_PORZ_VDDB Mask */ 212 213 #define MXC_F_MCR_PWRMONST_RSTZ_VDDC_POS 9 /**< PWRMONST_RSTZ_VDDC Position */ 214 #define MXC_F_MCR_PWRMONST_RSTZ_VDDC ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDC_POS)) /**< PWRMONST_RSTZ_VDDC Mask */ 215 216 #define MXC_F_MCR_PWRMONST_RSTZ_VDDA_POS 10 /**< PWRMONST_RSTZ_VDDA Position */ 217 #define MXC_F_MCR_PWRMONST_RSTZ_VDDA ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDA_POS)) /**< PWRMONST_RSTZ_VDDA Mask */ 218 219 #define MXC_F_MCR_PWRMONST_RSTZ_VDDB_POS 11 /**< PWRMONST_RSTZ_VDDB Position */ 220 #define MXC_F_MCR_PWRMONST_RSTZ_VDDB ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDB_POS)) /**< PWRMONST_RSTZ_VDDB Mask */ 221 222 #define MXC_F_MCR_PWRMONST_RSTZ_VDDIO_POS 12 /**< PWRMONST_RSTZ_VDDIO Position */ 223 #define MXC_F_MCR_PWRMONST_RSTZ_VDDIO ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDIO_POS)) /**< PWRMONST_RSTZ_VDDIO Mask */ 224 225 #define MXC_F_MCR_PWRMONST_RSTZ_VDDIOH_POS 13 /**< PWRMONST_RSTZ_VDDIOH Position */ 226 #define MXC_F_MCR_PWRMONST_RSTZ_VDDIOH ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDIOH_POS)) /**< PWRMONST_RSTZ_VDDIOH Mask */ 227 228 #define MXC_F_MCR_PWRMONST_RSTZ_VRTC_POS 14 /**< PWRMONST_RSTZ_VRTC Position */ 229 #define MXC_F_MCR_PWRMONST_RSTZ_VRTC ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VRTC_POS)) /**< PWRMONST_RSTZ_VRTC Mask */ 230 231 #define MXC_F_MCR_PWRMONST_RSTZ_LDO_0P9V_POS 16 /**< PWRMONST_RSTZ_LDO_0P9V Position */ 232 #define MXC_F_MCR_PWRMONST_RSTZ_LDO_0P9V ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_LDO_0P9V_POS)) /**< PWRMONST_RSTZ_LDO_0P9V Mask */ 233 234 #define MXC_F_MCR_PWRMONST_RSTZ_VDDCA_POS 17 /**< PWRMONST_RSTZ_VDDCA Position */ 235 #define MXC_F_MCR_PWRMONST_RSTZ_VDDCA ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDCA_POS)) /**< PWRMONST_RSTZ_VDDCA Mask */ 236 237 #define MXC_F_MCR_PWRMONST_RSTZ_VCOREHV_POS 18 /**< PWRMONST_RSTZ_VCOREHV Position */ 238 #define MXC_F_MCR_PWRMONST_RSTZ_VCOREHV ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VCOREHV_POS)) /**< PWRMONST_RSTZ_VCOREHV Mask */ 239 240 #define MXC_F_MCR_PWRMONST_RSTZ_VDDIOHV_POS 19 /**< PWRMONST_RSTZ_VDDIOHV Position */ 241 #define MXC_F_MCR_PWRMONST_RSTZ_VDDIOHV ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDIOHV_POS)) /**< PWRMONST_RSTZ_VDDIOHV Mask */ 242 243 #define MXC_F_MCR_PWRMONST_RSTZ_VDDIOHHV_POS 20 /**< PWRMONST_RSTZ_VDDIOHHV Position */ 244 #define MXC_F_MCR_PWRMONST_RSTZ_VDDIOHHV ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDIOHHV_POS)) /**< PWRMONST_RSTZ_VDDIOHHV Mask */ 245 246 /**@} end of group MCR_PWRMONST_Register */ 247 248 #ifdef __cplusplus 249 } 250 #endif 251 252 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_MCR_REGS_H_ 253
