1 /** 2 * @file gcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup gcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_GCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_GCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup gcr 67 * @defgroup gcr_registers GCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. 69 * @details Global Control Registers. 70 */ 71 72 /** 73 * @ingroup gcr_registers 74 * Structure type to access the GCR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t sysctrl; /**< <tt>\b 0x00:</tt> GCR SYSCTRL Register */ 78 __IO uint32_t rst0; /**< <tt>\b 0x04:</tt> GCR RST0 Register */ 79 __IO uint32_t clkctrl; /**< <tt>\b 0x08:</tt> GCR CLKCTRL Register */ 80 __IO uint32_t pm; /**< <tt>\b 0x0C:</tt> GCR PM Register */ 81 __R uint32_t rsv_0x10_0x17[2]; 82 __IO uint32_t pclkdiv; /**< <tt>\b 0x18:</tt> GCR PCLKDIV Register */ 83 __R uint32_t rsv_0x1c_0x23[2]; 84 __IO uint32_t pclkdis0; /**< <tt>\b 0x24:</tt> GCR PCLKDIS0 Register */ 85 __IO uint32_t memctrl; /**< <tt>\b 0x28:</tt> GCR MEMCTRL Register */ 86 __IO uint32_t memz; /**< <tt>\b 0x2C:</tt> GCR MEMZ Register */ 87 __R uint32_t rsv_0x30; 88 __IO uint32_t scclkctrl; /**< <tt>\b 0x34:</tt> GCR SCCLKCTRL Register */ 89 __R uint32_t rsv_0x38_0x3f[2]; 90 __IO uint32_t sysst; /**< <tt>\b 0x40:</tt> GCR SYSST Register */ 91 __IO uint32_t rst1; /**< <tt>\b 0x44:</tt> GCR RST1 Register */ 92 __IO uint32_t pclkdis1; /**< <tt>\b 0x48:</tt> GCR PCLKDIS1 Register */ 93 __IO uint32_t eventen; /**< <tt>\b 0x4C:</tt> GCR EVENTEN Register */ 94 __I uint32_t revision; /**< <tt>\b 0x50:</tt> GCR REVISION Register */ 95 __IO uint32_t sysie; /**< <tt>\b 0x54:</tt> GCR SYSIE Register */ 96 __IO uint32_t ipocnt; /**< <tt>\b 0x58:</tt> GCR IPOCNT Register */ 97 } mxc_gcr_regs_t; 98 99 /* Register offsets for module GCR */ 100 /** 101 * @ingroup gcr_registers 102 * @defgroup GCR_Register_Offsets Register Offsets 103 * @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address. 104 * @{ 105 */ 106 #define MXC_R_GCR_SYSCTRL ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt> 0x0000</tt> */ 107 #define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt> 0x0004</tt> */ 108 #define MXC_R_GCR_CLKCTRL ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt> 0x0008</tt> */ 109 #define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt> 0x000C</tt> */ 110 #define MXC_R_GCR_PCLKDIV ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt> 0x0018</tt> */ 111 #define MXC_R_GCR_PCLKDIS0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt> 0x0024</tt> */ 112 #define MXC_R_GCR_MEMCTRL ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt> 0x0028</tt> */ 113 #define MXC_R_GCR_MEMZ ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt> 0x002C</tt> */ 114 #define MXC_R_GCR_SCCLKCTRL ((uint32_t)0x00000034UL) /**< Offset from GCR Base Address: <tt> 0x0034</tt> */ 115 #define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt> 0x0040</tt> */ 116 #define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt> 0x0044</tt> */ 117 #define MXC_R_GCR_PCLKDIS1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt> 0x0048</tt> */ 118 #define MXC_R_GCR_EVENTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt> 0x004C</tt> */ 119 #define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> 0x0050</tt> */ 120 #define MXC_R_GCR_SYSIE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> 0x0054</tt> */ 121 #define MXC_R_GCR_IPOCNT ((uint32_t)0x00000058UL) /**< Offset from GCR Base Address: <tt> 0x0058</tt> */ 122 /**@} end of group gcr_registers */ 123 124 /** 125 * @ingroup gcr_registers 126 * @defgroup GCR_SYSCTRL GCR_SYSCTRL 127 * @brief System Control. 128 * @{ 129 */ 130 #define MXC_F_GCR_SYSCTRL_BSTAPEN_POS 0 /**< SYSCTRL_BSTAPEN Position */ 131 #define MXC_F_GCR_SYSCTRL_BSTAPEN ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_BSTAPEN_POS)) /**< SYSCTRL_BSTAPEN Mask */ 132 133 #define MXC_F_GCR_SYSCTRL_SBUSARB_POS 1 /**< SYSCTRL_SBUSARB Position */ 134 #define MXC_F_GCR_SYSCTRL_SBUSARB ((uint32_t)(0x3UL << MXC_F_GCR_SYSCTRL_SBUSARB_POS)) /**< SYSCTRL_SBUSARB Mask */ 135 #define MXC_V_GCR_SYSCTRL_SBUSARB_FIX ((uint32_t)0x0UL) /**< SYSCTRL_SBUSARB_FIX Value */ 136 #define MXC_S_GCR_SYSCTRL_SBUSARB_FIX (MXC_V_GCR_SYSCTRL_SBUSARB_FIX << MXC_F_GCR_SYSCTRL_SBUSARB_POS) /**< SYSCTRL_SBUSARB_FIX Setting */ 137 #define MXC_V_GCR_SYSCTRL_SBUSARB_ROUND ((uint32_t)0x1UL) /**< SYSCTRL_SBUSARB_ROUND Value */ 138 #define MXC_S_GCR_SYSCTRL_SBUSARB_ROUND (MXC_V_GCR_SYSCTRL_SBUSARB_ROUND << MXC_F_GCR_SYSCTRL_SBUSARB_POS) /**< SYSCTRL_SBUSARB_ROUND Setting */ 139 140 #define MXC_F_GCR_SYSCTRL_FPU_DIS_POS 5 /**< SYSCTRL_FPU_DIS Position */ 141 #define MXC_F_GCR_SYSCTRL_FPU_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_FPU_DIS_POS)) /**< SYSCTRL_FPU_DIS Mask */ 142 143 #define MXC_F_GCR_SYSCTRL_SFCC_FLUSH_POS 6 /**< SYSCTRL_SFCC_FLUSH Position */ 144 #define MXC_F_GCR_SYSCTRL_SFCC_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SFCC_FLUSH_POS)) /**< SYSCTRL_SFCC_FLUSH Mask */ 145 146 #define MXC_F_GCR_SYSCTRL_CHKRES1_POS 11 /**< SYSCTRL_CHKRES1 Position */ 147 #define MXC_F_GCR_SYSCTRL_CHKRES1 ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES1_POS)) /**< SYSCTRL_CHKRES1 Mask */ 148 149 #define MXC_F_GCR_SYSCTRL_CCHK1_POS 12 /**< SYSCTRL_CCHK1 Position */ 150 #define MXC_F_GCR_SYSCTRL_CCHK1 ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK1_POS)) /**< SYSCTRL_CCHK1 Mask */ 151 152 #define MXC_F_GCR_SYSCTRL_CCHK0_POS 13 /**< SYSCTRL_CCHK0 Position */ 153 #define MXC_F_GCR_SYSCTRL_CCHK0 ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK0_POS)) /**< SYSCTRL_CCHK0 Mask */ 154 155 #define MXC_F_GCR_SYSCTRL_SWD_DIS_POS 14 /**< SYSCTRL_SWD_DIS Position */ 156 #define MXC_F_GCR_SYSCTRL_SWD_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SWD_DIS_POS)) /**< SYSCTRL_SWD_DIS Mask */ 157 158 #define MXC_F_GCR_SYSCTRL_CHKRES0_POS 15 /**< SYSCTRL_CHKRES0 Position */ 159 #define MXC_F_GCR_SYSCTRL_CHKRES0 ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES0_POS)) /**< SYSCTRL_CHKRES0 Mask */ 160 161 /**@} end of group GCR_SYSCTRL_Register */ 162 163 /** 164 * @ingroup gcr_registers 165 * @defgroup GCR_RST0 GCR_RST0 166 * @brief Reset. 167 * @{ 168 */ 169 #define MXC_F_GCR_RST0_DMA_POS 0 /**< RST0_DMA Position */ 170 #define MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) /**< RST0_DMA Mask */ 171 172 #define MXC_F_GCR_RST0_WDT0_POS 1 /**< RST0_WDT0 Position */ 173 #define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) /**< RST0_WDT0 Mask */ 174 175 #define MXC_F_GCR_RST0_GPIO0_POS 2 /**< RST0_GPIO0 Position */ 176 #define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) /**< RST0_GPIO0 Mask */ 177 178 #define MXC_F_GCR_RST0_GPIO1_POS 3 /**< RST0_GPIO1 Position */ 179 #define MXC_F_GCR_RST0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO1_POS)) /**< RST0_GPIO1 Mask */ 180 181 #define MXC_F_GCR_RST0_TMR0_POS 5 /**< RST0_TMR0 Position */ 182 #define MXC_F_GCR_RST0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR0_POS)) /**< RST0_TMR0 Mask */ 183 184 #define MXC_F_GCR_RST0_TMR1_POS 6 /**< RST0_TMR1 Position */ 185 #define MXC_F_GCR_RST0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR1_POS)) /**< RST0_TMR1 Mask */ 186 187 #define MXC_F_GCR_RST0_TMR2_POS 7 /**< RST0_TMR2 Position */ 188 #define MXC_F_GCR_RST0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR2_POS)) /**< RST0_TMR2 Mask */ 189 190 #define MXC_F_GCR_RST0_TMR3_POS 8 /**< RST0_TMR3 Position */ 191 #define MXC_F_GCR_RST0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR3_POS)) /**< RST0_TMR3 Mask */ 192 193 #define MXC_F_GCR_RST0_TMR4_POS 9 /**< RST0_TMR4 Position */ 194 #define MXC_F_GCR_RST0_TMR4 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR4_POS)) /**< RST0_TMR4 Mask */ 195 196 #define MXC_F_GCR_RST0_TMR5_POS 10 /**< RST0_TMR5 Position */ 197 #define MXC_F_GCR_RST0_TMR5 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR5_POS)) /**< RST0_TMR5 Mask */ 198 199 #define MXC_F_GCR_RST0_UART0_POS 11 /**< RST0_UART0 Position */ 200 #define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) /**< RST0_UART0 Mask */ 201 202 #define MXC_F_GCR_RST0_UART1_POS 12 /**< RST0_UART1 Position */ 203 #define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) /**< RST0_UART1 Mask */ 204 205 #define MXC_F_GCR_RST0_SPI0_POS 13 /**< RST0_SPI0 Position */ 206 #define MXC_F_GCR_RST0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS)) /**< RST0_SPI0 Mask */ 207 208 #define MXC_F_GCR_RST0_SPI1_POS 14 /**< RST0_SPI1 Position */ 209 #define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) /**< RST0_SPI1 Mask */ 210 211 #define MXC_F_GCR_RST0_I2C0_POS 16 /**< RST0_I2C0 Position */ 212 #define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) /**< RST0_I2C0 Mask */ 213 214 #define MXC_F_GCR_RST0_CRYPTO_POS 18 /**< RST0_CRYPTO Position */ 215 #define MXC_F_GCR_RST0_CRYPTO ((uint32_t)(0x1UL << MXC_F_GCR_RST0_CRYPTO_POS)) /**< RST0_CRYPTO Mask */ 216 217 #define MXC_F_GCR_RST0_USB_POS 23 /**< RST0_USB Position */ 218 #define MXC_F_GCR_RST0_USB ((uint32_t)(0x1UL << MXC_F_GCR_RST0_USB_POS)) /**< RST0_USB Mask */ 219 220 #define MXC_F_GCR_RST0_TRNG_POS 24 /**< RST0_TRNG Position */ 221 #define MXC_F_GCR_RST0_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TRNG_POS)) /**< RST0_TRNG Mask */ 222 223 #define MXC_F_GCR_RST0_ADC_POS 26 /**< RST0_ADC Position */ 224 #define MXC_F_GCR_RST0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_ADC_POS)) /**< RST0_ADC Mask */ 225 226 #define MXC_F_GCR_RST0_UART2_POS 28 /**< RST0_UART2 Position */ 227 #define MXC_F_GCR_RST0_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART2_POS)) /**< RST0_UART2 Mask */ 228 229 #define MXC_F_GCR_RST0_SOFT_POS 29 /**< RST0_SOFT Position */ 230 #define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) /**< RST0_SOFT Mask */ 231 232 #define MXC_F_GCR_RST0_PERIPH_POS 30 /**< RST0_PERIPH Position */ 233 #define MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) /**< RST0_PERIPH Mask */ 234 235 #define MXC_F_GCR_RST0_SYS_POS 31 /**< RST0_SYS Position */ 236 #define MXC_F_GCR_RST0_SYS ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYS_POS)) /**< RST0_SYS Mask */ 237 238 /**@} end of group GCR_RST0_Register */ 239 240 /** 241 * @ingroup gcr_registers 242 * @defgroup GCR_CLKCTRL GCR_CLKCTRL 243 * @brief Clock Control. 244 * @{ 245 */ 246 #define MXC_F_GCR_CLKCTRL_PCLK_DIV_POS 3 /**< CLKCTRL_PCLK_DIV Position */ 247 #define MXC_F_GCR_CLKCTRL_PCLK_DIV ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_PCLK_DIV_POS)) /**< CLKCTRL_PCLK_DIV Mask */ 248 #define MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_PCLK_DIV_DIV1 Value */ 249 #define MXC_S_GCR_CLKCTRL_PCLK_DIV_DIV1 (MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV1 << MXC_F_GCR_CLKCTRL_PCLK_DIV_POS) /**< CLKCTRL_PCLK_DIV_DIV1 Setting */ 250 #define MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_PCLK_DIV_DIV2 Value */ 251 #define MXC_S_GCR_CLKCTRL_PCLK_DIV_DIV2 (MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV2 << MXC_F_GCR_CLKCTRL_PCLK_DIV_POS) /**< CLKCTRL_PCLK_DIV_DIV2 Setting */ 252 #define MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_PCLK_DIV_DIV4 Value */ 253 #define MXC_S_GCR_CLKCTRL_PCLK_DIV_DIV4 (MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV4 << MXC_F_GCR_CLKCTRL_PCLK_DIV_POS) /**< CLKCTRL_PCLK_DIV_DIV4 Setting */ 254 #define MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_PCLK_DIV_DIV8 Value */ 255 #define MXC_S_GCR_CLKCTRL_PCLK_DIV_DIV8 (MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV8 << MXC_F_GCR_CLKCTRL_PCLK_DIV_POS) /**< CLKCTRL_PCLK_DIV_DIV8 Setting */ 256 257 #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS 6 /**< CLKCTRL_SYSCLK_DIV Position */ 258 #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)) /**< CLKCTRL_SYSCLK_DIV Mask */ 259 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_DIV_DIV1 Value */ 260 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV1 Setting */ 261 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_SYSCLK_DIV_DIV2 Value */ 262 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV2 Setting */ 263 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_DIV_DIV4 Value */ 264 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV4 Setting */ 265 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_DIV_DIV8 Value */ 266 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV8 Setting */ 267 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_DIV_DIV16 Value */ 268 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV16 Setting */ 269 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_DIV_DIV32 Value */ 270 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV32 Setting */ 271 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_DIV_DIV64 Value */ 272 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV64 Setting */ 273 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_DIV_DIV128 Value */ 274 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV128 Setting */ 275 276 #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS 9 /**< CLKCTRL_SYSCLK_SEL Position */ 277 #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)) /**< CLKCTRL_SYSCLK_SEL Mask */ 278 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_SEL_ISO Value */ 279 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ISO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ISO Setting */ 280 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_SEL_ERFO Value */ 281 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERFO Setting */ 282 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_SEL_INRO Value */ 283 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_INRO Setting */ 284 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_SEL_IPO Value */ 285 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IPO Setting */ 286 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_SEL_IBRO Value */ 287 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IBRO Setting */ 288 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_SEL_ERTCO Value */ 289 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERTCO Setting */ 290 291 #define MXC_F_GCR_CLKCTRL_CRYPTOCLK_DIV_POS 12 /**< CLKCTRL_CRYPTOCLK_DIV Position */ 292 #define MXC_F_GCR_CLKCTRL_CRYPTOCLK_DIV ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_CRYPTOCLK_DIV_POS)) /**< CLKCTRL_CRYPTOCLK_DIV Mask */ 293 294 #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS 13 /**< CLKCTRL_SYSCLK_RDY Position */ 295 #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS)) /**< CLKCTRL_SYSCLK_RDY Mask */ 296 297 #define MXC_F_GCR_CLKCTRL_IPO_DIV_POS 14 /**< CLKCTRL_IPO_DIV Position */ 298 #define MXC_F_GCR_CLKCTRL_IPO_DIV ((uint32_t)(0x3UL << MXC_F_GCR_CLKCTRL_IPO_DIV_POS)) /**< CLKCTRL_IPO_DIV Mask */ 299 #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_IPO_DIV_DIV1 Value */ 300 #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV1 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV1 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV1 Setting */ 301 #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_IPO_DIV_DIV2 Value */ 302 #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV2 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV2 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV2 Setting */ 303 #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_IPO_DIV_DIV4 Value */ 304 #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV4 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV4 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV4 Setting */ 305 #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_IPO_DIV_DIV8 Value */ 306 #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV8 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV8 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV8 Setting */ 307 308 #define MXC_F_GCR_CLKCTRL_ERFO_EN_POS 16 /**< CLKCTRL_ERFO_EN Position */ 309 #define MXC_F_GCR_CLKCTRL_ERFO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_EN_POS)) /**< CLKCTRL_ERFO_EN Mask */ 310 311 #define MXC_F_GCR_CLKCTRL_ISO_EN_POS 18 /**< CLKCTRL_ISO_EN Position */ 312 #define MXC_F_GCR_CLKCTRL_ISO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ISO_EN_POS)) /**< CLKCTRL_ISO_EN Mask */ 313 314 #define MXC_F_GCR_CLKCTRL_IPO_EN_POS 19 /**< CLKCTRL_IPO_EN Position */ 315 #define MXC_F_GCR_CLKCTRL_IPO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_EN_POS)) /**< CLKCTRL_IPO_EN Mask */ 316 317 #define MXC_F_GCR_CLKCTRL_IBRO_EN_POS 20 /**< CLKCTRL_IBRO_EN Position */ 318 #define MXC_F_GCR_CLKCTRL_IBRO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_EN_POS)) /**< CLKCTRL_IBRO_EN Mask */ 319 320 #define MXC_F_GCR_CLKCTRL_IBRO_VS_POS 21 /**< CLKCTRL_IBRO_VS Position */ 321 #define MXC_F_GCR_CLKCTRL_IBRO_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_VS_POS)) /**< CLKCTRL_IBRO_VS Mask */ 322 323 #define MXC_F_GCR_CLKCTRL_ERFO_RDY_POS 24 /**< CLKCTRL_ERFO_RDY Position */ 324 #define MXC_F_GCR_CLKCTRL_ERFO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_RDY_POS)) /**< CLKCTRL_ERFO_RDY Mask */ 325 326 #define MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS 25 /**< CLKCTRL_ERTCO_RDY Position */ 327 #define MXC_F_GCR_CLKCTRL_ERTCO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS)) /**< CLKCTRL_ERTCO_RDY Mask */ 328 329 #define MXC_F_GCR_CLKCTRL_ISO_RDY_POS 26 /**< CLKCTRL_ISO_RDY Position */ 330 #define MXC_F_GCR_CLKCTRL_ISO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ISO_RDY_POS)) /**< CLKCTRL_ISO_RDY Mask */ 331 332 #define MXC_F_GCR_CLKCTRL_IPO_RDY_POS 27 /**< CLKCTRL_IPO_RDY Position */ 333 #define MXC_F_GCR_CLKCTRL_IPO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_RDY_POS)) /**< CLKCTRL_IPO_RDY Mask */ 334 335 #define MXC_F_GCR_CLKCTRL_IBRO_RDY_POS 28 /**< CLKCTRL_IBRO_RDY Position */ 336 #define MXC_F_GCR_CLKCTRL_IBRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_RDY_POS)) /**< CLKCTRL_IBRO_RDY Mask */ 337 338 #define MXC_F_GCR_CLKCTRL_INRO_RDY_POS 29 /**< CLKCTRL_INRO_RDY Position */ 339 #define MXC_F_GCR_CLKCTRL_INRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_INRO_RDY_POS)) /**< CLKCTRL_INRO_RDY Mask */ 340 341 /**@} end of group GCR_CLKCTRL_Register */ 342 343 /** 344 * @ingroup gcr_registers 345 * @defgroup GCR_PM GCR_PM 346 * @brief Power Management. 347 * @{ 348 */ 349 #define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */ 350 #define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ 351 #define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ 352 #define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ 353 #define MXC_V_GCR_PM_MODE_SLEEP ((uint32_t)0x1UL) /**< PM_MODE_SLEEP Value */ 354 #define MXC_S_GCR_PM_MODE_SLEEP (MXC_V_GCR_PM_MODE_SLEEP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SLEEP Setting */ 355 #define MXC_V_GCR_PM_MODE_DEEPSLEEP ((uint32_t)0x2UL) /**< PM_MODE_DEEPSLEEP Value */ 356 #define MXC_S_GCR_PM_MODE_DEEPSLEEP (MXC_V_GCR_PM_MODE_DEEPSLEEP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_DEEPSLEEP Setting */ 357 #define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */ 358 #define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */ 359 #define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */ 360 #define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ 361 362 #define MXC_F_GCR_PM_GPIO_WE_POS 4 /**< PM_GPIO_WE Position */ 363 #define MXC_F_GCR_PM_GPIO_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIO_WE_POS)) /**< PM_GPIO_WE Mask */ 364 365 #define MXC_F_GCR_PM_RTC_WE_POS 5 /**< PM_RTC_WE Position */ 366 #define MXC_F_GCR_PM_RTC_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTC_WE_POS)) /**< PM_RTC_WE Mask */ 367 368 #define MXC_F_GCR_PM_USB_WE_POS 6 /**< PM_USB_WE Position */ 369 #define MXC_F_GCR_PM_USB_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_USB_WE_POS)) /**< PM_USB_WE Mask */ 370 371 #define MXC_F_GCR_PM_ERFO_PD_POS 12 /**< PM_ERFO_PD Position */ 372 #define MXC_F_GCR_PM_ERFO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_PD_POS)) /**< PM_ERFO_PD Mask */ 373 374 #define MXC_F_GCR_PM_ISO_PD_POS 15 /**< PM_ISO_PD Position */ 375 #define MXC_F_GCR_PM_ISO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_ISO_PD_POS)) /**< PM_ISO_PD Mask */ 376 377 #define MXC_F_GCR_PM_IPO_PD_POS 16 /**< PM_IPO_PD Position */ 378 #define MXC_F_GCR_PM_IPO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IPO_PD_POS)) /**< PM_IPO_PD Mask */ 379 380 #define MXC_F_GCR_PM_IBRO_PD_POS 17 /**< PM_IBRO_PD Position */ 381 #define MXC_F_GCR_PM_IBRO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IBRO_PD_POS)) /**< PM_IBRO_PD Mask */ 382 383 #define MXC_F_GCR_PM_ERFO_BP_POS 20 /**< PM_ERFO_BP Position */ 384 #define MXC_F_GCR_PM_ERFO_BP ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_BP_POS)) /**< PM_ERFO_BP Mask */ 385 386 /**@} end of group GCR_PM_Register */ 387 388 /** 389 * @ingroup gcr_registers 390 * @defgroup GCR_PCLKDIV GCR_PCLKDIV 391 * @brief Peripheral Clock Divider. 392 * @{ 393 */ 394 #define MXC_F_GCR_PCLKDIV_SKBDFRQ_POS 0 /**< PCLKDIV_SKBDFRQ Position */ 395 #define MXC_F_GCR_PCLKDIV_SKBDFRQ ((uint32_t)(0x7UL << MXC_F_GCR_PCLKDIV_SKBDFRQ_POS)) /**< PCLKDIV_SKBDFRQ Mask */ 396 397 #define MXC_F_GCR_PCLKDIV_ADCFRQ_POS 10 /**< PCLKDIV_ADCFRQ Position */ 398 #define MXC_F_GCR_PCLKDIV_ADCFRQ ((uint32_t)(0xFUL << MXC_F_GCR_PCLKDIV_ADCFRQ_POS)) /**< PCLKDIV_ADCFRQ Mask */ 399 400 #define MXC_F_GCR_PCLKDIV_AONCLKDIV_POS 14 /**< PCLKDIV_AONCLKDIV Position */ 401 #define MXC_F_GCR_PCLKDIV_AONCLKDIV ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS)) /**< PCLKDIV_AONCLKDIV Mask */ 402 #define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV4 ((uint32_t)0x0UL) /**< PCLKDIV_AONCLKDIV_DIV4 Value */ 403 #define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV4 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV4 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV4 Setting */ 404 #define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV8 ((uint32_t)0x1UL) /**< PCLKDIV_AONCLKDIV_DIV8 Value */ 405 #define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV8 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV8 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV8 Setting */ 406 #define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV16 ((uint32_t)0x2UL) /**< PCLKDIV_AONCLKDIV_DIV16 Value */ 407 #define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV16 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV16 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV16 Setting */ 408 #define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV32 ((uint32_t)0x3UL) /**< PCLKDIV_AONCLKDIV_DIV32 Value */ 409 #define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV32 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV32 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV32 Setting */ 410 411 /**@} end of group GCR_PCLKDIV_Register */ 412 413 /** 414 * @ingroup gcr_registers 415 * @defgroup GCR_PCLKDIS0 GCR_PCLKDIS0 416 * @brief Peripheral Clock Disable. 417 * @{ 418 */ 419 #define MXC_F_GCR_PCLKDIS0_GPIO0_POS 0 /**< PCLKDIS0_GPIO0 Position */ 420 #define MXC_F_GCR_PCLKDIS0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO0_POS)) /**< PCLKDIS0_GPIO0 Mask */ 421 422 #define MXC_F_GCR_PCLKDIS0_GPIO1_POS 1 /**< PCLKDIS0_GPIO1 Position */ 423 #define MXC_F_GCR_PCLKDIS0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO1_POS)) /**< PCLKDIS0_GPIO1 Mask */ 424 425 #define MXC_F_GCR_PCLKDIS0_USB_POS 3 /**< PCLKDIS0_USB Position */ 426 #define MXC_F_GCR_PCLKDIS0_USB ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_USB_POS)) /**< PCLKDIS0_USB Mask */ 427 428 #define MXC_F_GCR_PCLKDIS0_DMA_POS 5 /**< PCLKDIS0_DMA Position */ 429 #define MXC_F_GCR_PCLKDIS0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_DMA_POS)) /**< PCLKDIS0_DMA Mask */ 430 431 #define MXC_F_GCR_PCLKDIS0_SPI0_POS 6 /**< PCLKDIS0_SPI0 Position */ 432 #define MXC_F_GCR_PCLKDIS0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI0_POS)) /**< PCLKDIS0_SPI0 Mask */ 433 434 #define MXC_F_GCR_PCLKDIS0_SPI1_POS 7 /**< PCLKDIS0_SPI1 Position */ 435 #define MXC_F_GCR_PCLKDIS0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI1_POS)) /**< PCLKDIS0_SPI1 Mask */ 436 437 #define MXC_F_GCR_PCLKDIS0_UART0_POS 9 /**< PCLKDIS0_UART0 Position */ 438 #define MXC_F_GCR_PCLKDIS0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART0_POS)) /**< PCLKDIS0_UART0 Mask */ 439 440 #define MXC_F_GCR_PCLKDIS0_UART1_POS 10 /**< PCLKDIS0_UART1 Position */ 441 #define MXC_F_GCR_PCLKDIS0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART1_POS)) /**< PCLKDIS0_UART1 Mask */ 442 443 #define MXC_F_GCR_PCLKDIS0_I2C0_POS 13 /**< PCLKDIS0_I2C0 Position */ 444 #define MXC_F_GCR_PCLKDIS0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C0_POS)) /**< PCLKDIS0_I2C0 Mask */ 445 446 #define MXC_F_GCR_PCLKDIS0_CRYPTO_POS 14 /**< PCLKDIS0_CRYPTO Position */ 447 #define MXC_F_GCR_PCLKDIS0_CRYPTO ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_CRYPTO_POS)) /**< PCLKDIS0_CRYPTO Mask */ 448 449 #define MXC_F_GCR_PCLKDIS0_TMR0_POS 15 /**< PCLKDIS0_TMR0 Position */ 450 #define MXC_F_GCR_PCLKDIS0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR0_POS)) /**< PCLKDIS0_TMR0 Mask */ 451 452 #define MXC_F_GCR_PCLKDIS0_TMR1_POS 16 /**< PCLKDIS0_TMR1 Position */ 453 #define MXC_F_GCR_PCLKDIS0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR1_POS)) /**< PCLKDIS0_TMR1 Mask */ 454 455 #define MXC_F_GCR_PCLKDIS0_TMR2_POS 17 /**< PCLKDIS0_TMR2 Position */ 456 #define MXC_F_GCR_PCLKDIS0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR2_POS)) /**< PCLKDIS0_TMR2 Mask */ 457 458 #define MXC_F_GCR_PCLKDIS0_TMR3_POS 18 /**< PCLKDIS0_TMR3 Position */ 459 #define MXC_F_GCR_PCLKDIS0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR3_POS)) /**< PCLKDIS0_TMR3 Mask */ 460 461 #define MXC_F_GCR_PCLKDIS0_TMR4_POS 19 /**< PCLKDIS0_TMR4 Position */ 462 #define MXC_F_GCR_PCLKDIS0_TMR4 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR4_POS)) /**< PCLKDIS0_TMR4 Mask */ 463 464 #define MXC_F_GCR_PCLKDIS0_TMR5_POS 20 /**< PCLKDIS0_TMR5 Position */ 465 #define MXC_F_GCR_PCLKDIS0_TMR5 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR5_POS)) /**< PCLKDIS0_TMR5 Mask */ 466 467 #define MXC_F_GCR_PCLKDIS0_SKBD_POS 22 /**< PCLKDIS0_SKBD Position */ 468 #define MXC_F_GCR_PCLKDIS0_SKBD ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SKBD_POS)) /**< PCLKDIS0_SKBD Mask */ 469 470 #define MXC_F_GCR_PCLKDIS0_ADC_POS 23 /**< PCLKDIS0_ADC Position */ 471 #define MXC_F_GCR_PCLKDIS0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_ADC_POS)) /**< PCLKDIS0_ADC Mask */ 472 473 #define MXC_F_GCR_PCLKDIS0_HTMR0_POS 26 /**< PCLKDIS0_HTMR0 Position */ 474 #define MXC_F_GCR_PCLKDIS0_HTMR0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_HTMR0_POS)) /**< PCLKDIS0_HTMR0 Mask */ 475 476 #define MXC_F_GCR_PCLKDIS0_HTMR1_POS 27 /**< PCLKDIS0_HTMR1 Position */ 477 #define MXC_F_GCR_PCLKDIS0_HTMR1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_HTMR1_POS)) /**< PCLKDIS0_HTMR1 Mask */ 478 479 #define MXC_F_GCR_PCLKDIS0_I2C1_POS 28 /**< PCLKDIS0_I2C1 Position */ 480 #define MXC_F_GCR_PCLKDIS0_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C1_POS)) /**< PCLKDIS0_I2C1 Mask */ 481 482 #define MXC_F_GCR_PCLKDIS0_PT_POS 29 /**< PCLKDIS0_PT Position */ 483 #define MXC_F_GCR_PCLKDIS0_PT ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_PT_POS)) /**< PCLKDIS0_PT Mask */ 484 485 #define MXC_F_GCR_PCLKDIS0_SPIXIP_POS 30 /**< PCLKDIS0_SPIXIP Position */ 486 #define MXC_F_GCR_PCLKDIS0_SPIXIP ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPIXIP_POS)) /**< PCLKDIS0_SPIXIP Mask */ 487 488 #define MXC_F_GCR_PCLKDIS0_SPIXIPC_POS 31 /**< PCLKDIS0_SPIXIPC Position */ 489 #define MXC_F_GCR_PCLKDIS0_SPIXIPC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPIXIPC_POS)) /**< PCLKDIS0_SPIXIPC Mask */ 490 491 /**@} end of group GCR_PCLKDIS0_Register */ 492 493 /** 494 * @ingroup gcr_registers 495 * @defgroup GCR_MEMCTRL GCR_MEMCTRL 496 * @brief Memory Clock Control Register. 497 * @{ 498 */ 499 #define MXC_F_GCR_MEMCTRL_FWS_POS 0 /**< MEMCTRL_FWS Position */ 500 #define MXC_F_GCR_MEMCTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCTRL_FWS_POS)) /**< MEMCTRL_FWS Mask */ 501 502 #define MXC_F_GCR_MEMCTRL_RAM4_WS_POS 4 /**< MEMCTRL_RAM4_WS Position */ 503 #define MXC_F_GCR_MEMCTRL_RAM4_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM4_WS_POS)) /**< MEMCTRL_RAM4_WS Mask */ 504 505 #define MXC_F_GCR_MEMCTRL_RAM5_WS_POS 5 /**< MEMCTRL_RAM5_WS Position */ 506 #define MXC_F_GCR_MEMCTRL_RAM5_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM5_WS_POS)) /**< MEMCTRL_RAM5_WS Mask */ 507 508 #define MXC_F_GCR_MEMCTRL_RAM6_WS_POS 6 /**< MEMCTRL_RAM6_WS Position */ 509 #define MXC_F_GCR_MEMCTRL_RAM6_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM6_WS_POS)) /**< MEMCTRL_RAM6_WS Mask */ 510 511 #define MXC_F_GCR_MEMCTRL_ROM1_WS_POS 7 /**< MEMCTRL_ROM1_WS Position */ 512 #define MXC_F_GCR_MEMCTRL_ROM1_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROM1_WS_POS)) /**< MEMCTRL_ROM1_WS Mask */ 513 514 #define MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS 16 /**< MEMCTRL_RAM0LS_EN Position */ 515 #define MXC_F_GCR_MEMCTRL_RAM0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS)) /**< MEMCTRL_RAM0LS_EN Mask */ 516 517 #define MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS 17 /**< MEMCTRL_RAM1LS_EN Position */ 518 #define MXC_F_GCR_MEMCTRL_RAM1LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS)) /**< MEMCTRL_RAM1LS_EN Mask */ 519 520 #define MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS 18 /**< MEMCTRL_RAM2LS_EN Position */ 521 #define MXC_F_GCR_MEMCTRL_RAM2LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS)) /**< MEMCTRL_RAM2LS_EN Mask */ 522 523 #define MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS 19 /**< MEMCTRL_RAM3LS_EN Position */ 524 #define MXC_F_GCR_MEMCTRL_RAM3LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS)) /**< MEMCTRL_RAM3LS_EN Mask */ 525 526 #define MXC_F_GCR_MEMCTRL_RAM4LS_EN_POS 20 /**< MEMCTRL_RAM4LS_EN Position */ 527 #define MXC_F_GCR_MEMCTRL_RAM4LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM4LS_EN_POS)) /**< MEMCTRL_RAM4LS_EN Mask */ 528 529 #define MXC_F_GCR_MEMCTRL_RAM5LS_EN_POS 21 /**< MEMCTRL_RAM5LS_EN Position */ 530 #define MXC_F_GCR_MEMCTRL_RAM5LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM5LS_EN_POS)) /**< MEMCTRL_RAM5LS_EN Mask */ 531 532 #define MXC_F_GCR_MEMCTRL_RAM6LS_EN_POS 22 /**< MEMCTRL_RAM6LS_EN Position */ 533 #define MXC_F_GCR_MEMCTRL_RAM6LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM6LS_EN_POS)) /**< MEMCTRL_RAM6LS_EN Mask */ 534 535 #define MXC_F_GCR_MEMCTRL_ICCXIPLS_EN_POS 25 /**< MEMCTRL_ICCXIPLS_EN Position */ 536 #define MXC_F_GCR_MEMCTRL_ICCXIPLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ICCXIPLS_EN_POS)) /**< MEMCTRL_ICCXIPLS_EN Mask */ 537 538 #define MXC_F_GCR_MEMCTRL_CRYPTOLS_EN_POS 27 /**< MEMCTRL_CRYPTOLS_EN Position */ 539 #define MXC_F_GCR_MEMCTRL_CRYPTOLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_CRYPTOLS_EN_POS)) /**< MEMCTRL_CRYPTOLS_EN Mask */ 540 541 #define MXC_F_GCR_MEMCTRL_USBLS_EN_POS 28 /**< MEMCTRL_USBLS_EN Position */ 542 #define MXC_F_GCR_MEMCTRL_USBLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_USBLS_EN_POS)) /**< MEMCTRL_USBLS_EN Mask */ 543 544 #define MXC_F_GCR_MEMCTRL_ROM0LS_EN_POS 29 /**< MEMCTRL_ROM0LS_EN Position */ 545 #define MXC_F_GCR_MEMCTRL_ROM0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROM0LS_EN_POS)) /**< MEMCTRL_ROM0LS_EN Mask */ 546 547 #define MXC_F_GCR_MEMCTRL_ROM1LS_EN_POS 30 /**< MEMCTRL_ROM1LS_EN Position */ 548 #define MXC_F_GCR_MEMCTRL_ROM1LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROM1LS_EN_POS)) /**< MEMCTRL_ROM1LS_EN Mask */ 549 550 #define MXC_F_GCR_MEMCTRL_MAALS_EN_POS 31 /**< MEMCTRL_MAALS_EN Position */ 551 #define MXC_F_GCR_MEMCTRL_MAALS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_MAALS_EN_POS)) /**< MEMCTRL_MAALS_EN Mask */ 552 553 /**@} end of group GCR_MEMCTRL_Register */ 554 555 /** 556 * @ingroup gcr_registers 557 * @defgroup GCR_MEMZ GCR_MEMZ 558 * @brief Memory Zeroize Control. 559 * @{ 560 */ 561 #define MXC_F_GCR_MEMZ_RAM0_POS 0 /**< MEMZ_RAM0 Position */ 562 #define MXC_F_GCR_MEMZ_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM0_POS)) /**< MEMZ_RAM0 Mask */ 563 564 #define MXC_F_GCR_MEMZ_RAM1_POS 1 /**< MEMZ_RAM1 Position */ 565 #define MXC_F_GCR_MEMZ_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM1_POS)) /**< MEMZ_RAM1 Mask */ 566 567 #define MXC_F_GCR_MEMZ_RAM2_POS 2 /**< MEMZ_RAM2 Position */ 568 #define MXC_F_GCR_MEMZ_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM2_POS)) /**< MEMZ_RAM2 Mask */ 569 570 #define MXC_F_GCR_MEMZ_RAM3_POS 3 /**< MEMZ_RAM3 Position */ 571 #define MXC_F_GCR_MEMZ_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM3_POS)) /**< MEMZ_RAM3 Mask */ 572 573 #define MXC_F_GCR_MEMZ_RAM4_POS 4 /**< MEMZ_RAM4 Position */ 574 #define MXC_F_GCR_MEMZ_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM4_POS)) /**< MEMZ_RAM4 Mask */ 575 576 #define MXC_F_GCR_MEMZ_RAM5_POS 5 /**< MEMZ_RAM5 Position */ 577 #define MXC_F_GCR_MEMZ_RAM5 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM5_POS)) /**< MEMZ_RAM5 Mask */ 578 579 #define MXC_F_GCR_MEMZ_RAM6_POS 6 /**< MEMZ_RAM6 Position */ 580 #define MXC_F_GCR_MEMZ_RAM6 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM6_POS)) /**< MEMZ_RAM6 Mask */ 581 582 #define MXC_F_GCR_MEMZ_ICCXIP_POS 9 /**< MEMZ_ICCXIP Position */ 583 #define MXC_F_GCR_MEMZ_ICCXIP ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICCXIP_POS)) /**< MEMZ_ICCXIP Mask */ 584 585 #define MXC_F_GCR_MEMZ_CRYPTO_POS 12 /**< MEMZ_CRYPTO Position */ 586 #define MXC_F_GCR_MEMZ_CRYPTO ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_CRYPTO_POS)) /**< MEMZ_CRYPTO Mask */ 587 588 #define MXC_F_GCR_MEMZ_USBFIFO_POS 13 /**< MEMZ_USBFIFO Position */ 589 #define MXC_F_GCR_MEMZ_USBFIFO ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_USBFIFO_POS)) /**< MEMZ_USBFIFO Mask */ 590 591 /**@} end of group GCR_MEMZ_Register */ 592 593 /** 594 * @ingroup gcr_registers 595 * @defgroup GCR_SCCLKCTRL GCR_SCCLKCTRL 596 * @brief Smart Card Clock Control. 597 * @{ 598 */ 599 #define MXC_F_GCR_SCCLKCTRL_SC0CLK_DIV_POS 0 /**< SCCLKCTRL_SC0CLK_DIV Position */ 600 #define MXC_F_GCR_SCCLKCTRL_SC0CLK_DIV ((uint32_t)(0x3FUL << MXC_F_GCR_SCCLKCTRL_SC0CLK_DIV_POS)) /**< SCCLKCTRL_SC0CLK_DIV Mask */ 601 602 #define MXC_F_GCR_SCCLKCTRL_SC1CLK_DIV_POS 8 /**< SCCLKCTRL_SC1CLK_DIV Position */ 603 #define MXC_F_GCR_SCCLKCTRL_SC1CLK_DIV ((uint32_t)(0x3FUL << MXC_F_GCR_SCCLKCTRL_SC1CLK_DIV_POS)) /**< SCCLKCTRL_SC1CLK_DIV Mask */ 604 605 /**@} end of group GCR_SCCLKCTRL_Register */ 606 607 /** 608 * @ingroup gcr_registers 609 * @defgroup GCR_SYSST GCR_SYSST 610 * @brief System Status Register. 611 * @{ 612 */ 613 #define MXC_F_GCR_SYSST_ICELOCK_POS 0 /**< SYSST_ICELOCK Position */ 614 #define MXC_F_GCR_SYSST_ICELOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICELOCK_POS)) /**< SYSST_ICELOCK Mask */ 615 616 #define MXC_F_GCR_SYSST_CODEINTERR_POS 1 /**< SYSST_CODEINTERR Position */ 617 #define MXC_F_GCR_SYSST_CODEINTERR ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_CODEINTERR_POS)) /**< SYSST_CODEINTERR Mask */ 618 619 #define MXC_F_GCR_SYSST_SCMEMF_POS 5 /**< SYSST_SCMEMF Position */ 620 #define MXC_F_GCR_SYSST_SCMEMF ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_SCMEMF_POS)) /**< SYSST_SCMEMF Mask */ 621 622 /**@} end of group GCR_SYSST_Register */ 623 624 /** 625 * @ingroup gcr_registers 626 * @defgroup GCR_RST1 GCR_RST1 627 * @brief Reset 1. 628 * @{ 629 */ 630 #define MXC_F_GCR_RST1_I2C1_POS 0 /**< RST1_I2C1 Position */ 631 #define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) /**< RST1_I2C1 Mask */ 632 633 #define MXC_F_GCR_RST1_PT_POS 1 /**< RST1_PT Position */ 634 #define MXC_F_GCR_RST1_PT ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PT_POS)) /**< RST1_PT Mask */ 635 636 #define MXC_F_GCR_RST1_SPIXIP_POS 3 /**< RST1_SPIXIP Position */ 637 #define MXC_F_GCR_RST1_SPIXIP ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPIXIP_POS)) /**< RST1_SPIXIP Mask */ 638 639 #define MXC_F_GCR_RST1_SPIXIPM_POS 4 /**< RST1_SPIXIPM Position */ 640 #define MXC_F_GCR_RST1_SPIXIPM ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPIXIPM_POS)) /**< RST1_SPIXIPM Mask */ 641 642 #define MXC_F_GCR_RST1_WDT1_POS 8 /**< RST1_WDT1 Position */ 643 #define MXC_F_GCR_RST1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS)) /**< RST1_WDT1 Mask */ 644 645 #define MXC_F_GCR_RST1_SPI3_POS 9 /**< RST1_SPI3 Position */ 646 #define MXC_F_GCR_RST1_SPI3 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPI3_POS)) /**< RST1_SPI3 Mask */ 647 648 #define MXC_F_GCR_RST1_AC_POS 14 /**< RST1_AC Position */ 649 #define MXC_F_GCR_RST1_AC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AC_POS)) /**< RST1_AC Mask */ 650 651 #define MXC_F_GCR_RST1_SEMA_POS 16 /**< RST1_SEMA Position */ 652 #define MXC_F_GCR_RST1_SEMA ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SEMA_POS)) /**< RST1_SEMA Mask */ 653 654 #define MXC_F_GCR_RST1_UART3_POS 18 /**< RST1_UART3 Position */ 655 #define MXC_F_GCR_RST1_UART3 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_UART3_POS)) /**< RST1_UART3 Mask */ 656 657 #define MXC_F_GCR_RST1_SKBD_POS 21 /**< RST1_SKBD Position */ 658 #define MXC_F_GCR_RST1_SKBD ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SKBD_POS)) /**< RST1_SKBD Mask */ 659 660 #define MXC_F_GCR_RST1_MSRADC_POS 22 /**< RST1_MSRADC Position */ 661 #define MXC_F_GCR_RST1_MSRADC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_MSRADC_POS)) /**< RST1_MSRADC Mask */ 662 663 #define MXC_F_GCR_RST1_SC0_POS 23 /**< RST1_SC0 Position */ 664 #define MXC_F_GCR_RST1_SC0 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SC0_POS)) /**< RST1_SC0 Mask */ 665 666 #define MXC_F_GCR_RST1_SC1_POS 24 /**< RST1_SC1 Position */ 667 #define MXC_F_GCR_RST1_SC1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SC1_POS)) /**< RST1_SC1 Mask */ 668 669 #define MXC_F_GCR_RST1_HTMR0_POS 28 /**< RST1_HTMR0 Position */ 670 #define MXC_F_GCR_RST1_HTMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_HTMR0_POS)) /**< RST1_HTMR0 Mask */ 671 672 #define MXC_F_GCR_RST1_HTMR1_POS 29 /**< RST1_HTMR1 Position */ 673 #define MXC_F_GCR_RST1_HTMR1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_HTMR1_POS)) /**< RST1_HTMR1 Mask */ 674 675 #define MXC_F_GCR_RST1_CPU1_POS 31 /**< RST1_CPU1 Position */ 676 #define MXC_F_GCR_RST1_CPU1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CPU1_POS)) /**< RST1_CPU1 Mask */ 677 678 /**@} end of group GCR_RST1_Register */ 679 680 /** 681 * @ingroup gcr_registers 682 * @defgroup GCR_PCLKDIS1 GCR_PCLKDIS1 683 * @brief Peripheral Clock Disable. 684 * @{ 685 */ 686 #define MXC_F_GCR_PCLKDIS1_UART2_POS 1 /**< PCLKDIS1_UART2 Position */ 687 #define MXC_F_GCR_PCLKDIS1_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART2_POS)) /**< PCLKDIS1_UART2 Mask */ 688 689 #define MXC_F_GCR_PCLKDIS1_TRNG_POS 2 /**< PCLKDIS1_TRNG Position */ 690 #define MXC_F_GCR_PCLKDIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_TRNG_POS)) /**< PCLKDIS1_TRNG Mask */ 691 692 #define MXC_F_GCR_PCLKDIS1_OTP_POS 3 /**< PCLKDIS1_OTP Position */ 693 #define MXC_F_GCR_PCLKDIS1_OTP ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_OTP_POS)) /**< PCLKDIS1_OTP Mask */ 694 695 #define MXC_F_GCR_PCLKDIS1_WDT0_POS 4 /**< PCLKDIS1_WDT0 Position */ 696 #define MXC_F_GCR_PCLKDIS1_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WDT0_POS)) /**< PCLKDIS1_WDT0 Mask */ 697 698 #define MXC_F_GCR_PCLKDIS1_WDT1_POS 5 /**< PCLKDIS1_WDT1 Position */ 699 #define MXC_F_GCR_PCLKDIS1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WDT1_POS)) /**< PCLKDIS1_WDT1 Mask */ 700 701 #define MXC_F_GCR_PCLKDIS1_SEMA_POS 9 /**< PCLKDIS1_SEMA Position */ 702 #define MXC_F_GCR_PCLKDIS1_SEMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SEMA_POS)) /**< PCLKDIS1_SEMA Mask */ 703 704 #define MXC_F_GCR_PCLKDIS1_SPI3_POS 14 /**< PCLKDIS1_SPI3 Position */ 705 #define MXC_F_GCR_PCLKDIS1_SPI3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SPI3_POS)) /**< PCLKDIS1_SPI3 Mask */ 706 707 #define MXC_F_GCR_PCLKDIS1_UART3_POS 22 /**< PCLKDIS1_UART3 Position */ 708 #define MXC_F_GCR_PCLKDIS1_UART3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART3_POS)) /**< PCLKDIS1_UART3 Mask */ 709 710 #define MXC_F_GCR_PCLKDIS1_MSRADC_POS 25 /**< PCLKDIS1_MSRADC Position */ 711 #define MXC_F_GCR_PCLKDIS1_MSRADC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_MSRADC_POS)) /**< PCLKDIS1_MSRADC Mask */ 712 713 #define MXC_F_GCR_PCLKDIS1_SC0_POS 26 /**< PCLKDIS1_SC0 Position */ 714 #define MXC_F_GCR_PCLKDIS1_SC0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SC0_POS)) /**< PCLKDIS1_SC0 Mask */ 715 716 #define MXC_F_GCR_PCLKDIS1_SC1_POS 27 /**< PCLKDIS1_SC1 Position */ 717 #define MXC_F_GCR_PCLKDIS1_SC1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SC1_POS)) /**< PCLKDIS1_SC1 Mask */ 718 719 #define MXC_F_GCR_PCLKDIS1_CPU1_POS 31 /**< PCLKDIS1_CPU1 Position */ 720 #define MXC_F_GCR_PCLKDIS1_CPU1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CPU1_POS)) /**< PCLKDIS1_CPU1 Mask */ 721 722 /**@} end of group GCR_PCLKDIS1_Register */ 723 724 /** 725 * @ingroup gcr_registers 726 * @defgroup GCR_EVENTEN GCR_EVENTEN 727 * @brief Event Enable Register. 728 * @{ 729 */ 730 #define MXC_F_GCR_EVENTEN_DMA_POS 0 /**< EVENTEN_DMA Position */ 731 #define MXC_F_GCR_EVENTEN_DMA ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_DMA_POS)) /**< EVENTEN_DMA Mask */ 732 733 #define MXC_F_GCR_EVENTEN_RX_POS 1 /**< EVENTEN_RX Position */ 734 #define MXC_F_GCR_EVENTEN_RX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_RX_POS)) /**< EVENTEN_RX Mask */ 735 736 #define MXC_F_GCR_EVENTEN_TX_POS 2 /**< EVENTEN_TX Position */ 737 #define MXC_F_GCR_EVENTEN_TX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_TX_POS)) /**< EVENTEN_TX Mask */ 738 739 /**@} end of group GCR_EVENTEN_Register */ 740 741 /** 742 * @ingroup gcr_registers 743 * @defgroup GCR_REVISION GCR_REVISION 744 * @brief Revision Register. 745 * @{ 746 */ 747 #define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */ 748 #define MXC_F_GCR_REVISION_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */ 749 750 /**@} end of group GCR_REVISION_Register */ 751 752 /** 753 * @ingroup gcr_registers 754 * @defgroup GCR_SYSIE GCR_SYSIE 755 * @brief System Status Interrupt Enable Register. 756 * @{ 757 */ 758 #define MXC_F_GCR_SYSIE_ICEUNLOCK_POS 0 /**< SYSIE_ICEUNLOCK Position */ 759 #define MXC_F_GCR_SYSIE_ICEUNLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSIE_ICEUNLOCK_POS)) /**< SYSIE_ICEUNLOCK Mask */ 760 761 #define MXC_F_GCR_SYSIE_CIE_POS 1 /**< SYSIE_CIE Position */ 762 #define MXC_F_GCR_SYSIE_CIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSIE_CIE_POS)) /**< SYSIE_CIE Mask */ 763 764 #define MXC_F_GCR_SYSIE_SCMF_POS 5 /**< SYSIE_SCMF Position */ 765 #define MXC_F_GCR_SYSIE_SCMF ((uint32_t)(0x1UL << MXC_F_GCR_SYSIE_SCMF_POS)) /**< SYSIE_SCMF Mask */ 766 767 /**@} end of group GCR_SYSIE_Register */ 768 769 /** 770 * @ingroup gcr_registers 771 * @defgroup GCR_IPOCNT GCR_IPOCNT 772 * @brief IPO Warmup Count Register. 773 * @{ 774 */ 775 #define MXC_F_GCR_IPOCNT_WMUPCNT_POS 0 /**< IPOCNT_WMUPCNT Position */ 776 #define MXC_F_GCR_IPOCNT_WMUPCNT ((uint32_t)(0x3FFUL << MXC_F_GCR_IPOCNT_WMUPCNT_POS)) /**< IPOCNT_WMUPCNT Mask */ 777 778 /**@} end of group GCR_IPOCNT_Register */ 779 780 #ifdef __cplusplus 781 } 782 #endif 783 784 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_GCR_REGS_H_ 785
