1 /** 2 * @file fcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup fcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_FCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_FCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup fcr 67 * @defgroup fcr_registers FCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. 69 * @details Function Control Register. 70 */ 71 72 /** 73 * @ingroup fcr_registers 74 * Structure type to access the FCR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t fctrl0; /**< <tt>\b 0x00:</tt> FCR FCTRL0 Register */ 78 __IO uint32_t fctrl1; /**< <tt>\b 0x04:</tt> FCR FCTRL1 Register */ 79 __R uint32_t rsv_0x8; 80 __IO uint32_t fctrl3; /**< <tt>\b 0x0C:</tt> FCR FCTRL3 Register */ 81 __IO uint32_t urvbootaddr; /**< <tt>\b 0x10:</tt> FCR URVBOOTADDR Register */ 82 __IO uint32_t urvctrl; /**< <tt>\b 0x14:</tt> FCR URVCTRL Register */ 83 __R uint32_t rsv_0x18; 84 __IO uint32_t gp; /**< <tt>\b 0x1C:</tt> FCR GP Register */ 85 __IO uint32_t trimctrl; /**< <tt>\b 0x20:</tt> FCR TRIMCTRL Register */ 86 __IO uint32_t erfoks; /**< <tt>\b 0x24:</tt> FCR ERFOKS Register */ 87 } mxc_fcr_regs_t; 88 89 /* Register offsets for module FCR */ 90 /** 91 * @ingroup fcr_registers 92 * @defgroup FCR_Register_Offsets Register Offsets 93 * @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address. 94 * @{ 95 */ 96 #define MXC_R_FCR_FCTRL0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: <tt> 0x0000</tt> */ 97 #define MXC_R_FCR_FCTRL1 ((uint32_t)0x00000004UL) /**< Offset from FCR Base Address: <tt> 0x0004</tt> */ 98 #define MXC_R_FCR_FCTRL3 ((uint32_t)0x0000000CUL) /**< Offset from FCR Base Address: <tt> 0x000C</tt> */ 99 #define MXC_R_FCR_URVBOOTADDR ((uint32_t)0x00000010UL) /**< Offset from FCR Base Address: <tt> 0x0010</tt> */ 100 #define MXC_R_FCR_URVCTRL ((uint32_t)0x00000014UL) /**< Offset from FCR Base Address: <tt> 0x0014</tt> */ 101 #define MXC_R_FCR_GP ((uint32_t)0x0000001CUL) /**< Offset from FCR Base Address: <tt> 0x001C</tt> */ 102 #define MXC_R_FCR_TRIMCTRL ((uint32_t)0x00000020UL) /**< Offset from FCR Base Address: <tt> 0x0020</tt> */ 103 #define MXC_R_FCR_ERFOKS ((uint32_t)0x00000024UL) /**< Offset from FCR Base Address: <tt> 0x0024</tt> */ 104 /**@} end of group fcr_registers */ 105 106 /** 107 * @ingroup fcr_registers 108 * @defgroup FCR_FCTRL0 FCR_FCTRL0 109 * @brief Register 0. 110 * @{ 111 */ 112 #define MXC_F_FCR_FCTRL0_USBCLKSEL_POS 16 /**< FCTRL0_USBCLKSEL Position */ 113 #define MXC_F_FCR_FCTRL0_USBCLKSEL ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_USBCLKSEL_POS)) /**< FCTRL0_USBCLKSEL Mask */ 114 115 #define MXC_F_FCR_FCTRL0_I2C0DGEN0_POS 20 /**< FCTRL0_I2C0DGEN0 Position */ 116 #define MXC_F_FCR_FCTRL0_I2C0DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN0_POS)) /**< FCTRL0_I2C0DGEN0 Mask */ 117 118 #define MXC_F_FCR_FCTRL0_I2C0DGEN1_POS 21 /**< FCTRL0_I2C0DGEN1 Position */ 119 #define MXC_F_FCR_FCTRL0_I2C0DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN1_POS)) /**< FCTRL0_I2C0DGEN1 Mask */ 120 121 #define MXC_F_FCR_FCTRL0_I2C1DGEN0_POS 22 /**< FCTRL0_I2C1DGEN0 Position */ 122 #define MXC_F_FCR_FCTRL0_I2C1DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN0_POS)) /**< FCTRL0_I2C1DGEN0 Mask */ 123 124 #define MXC_F_FCR_FCTRL0_I2C1DGEN1_POS 23 /**< FCTRL0_I2C1DGEN1 Position */ 125 #define MXC_F_FCR_FCTRL0_I2C1DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN1_POS)) /**< FCTRL0_I2C1DGEN1 Mask */ 126 127 /**@} end of group FCR_FCTRL0_Register */ 128 129 /** 130 * @ingroup fcr_registers 131 * @defgroup FCR_FCTRL1 FCR_FCTRL1 132 * @brief Register 1. 133 * @{ 134 */ 135 #define MXC_F_FCR_FCTRL1_AC_EN_POS 0 /**< FCTRL1_AC_EN Position */ 136 #define MXC_F_FCR_FCTRL1_AC_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL1_AC_EN_POS)) /**< FCTRL1_AC_EN Mask */ 137 138 #define MXC_F_FCR_FCTRL1_AC_RUN_POS 1 /**< FCTRL1_AC_RUN Position */ 139 #define MXC_F_FCR_FCTRL1_AC_RUN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL1_AC_RUN_POS)) /**< FCTRL1_AC_RUN Mask */ 140 141 #define MXC_F_FCR_FCTRL1_LOAD_POS 2 /**< FCTRL1_LOAD Position */ 142 #define MXC_F_FCR_FCTRL1_LOAD ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL1_LOAD_POS)) /**< FCTRL1_LOAD Mask */ 143 144 #define MXC_F_FCR_FCTRL1_INV_GAIN_POS 3 /**< FCTRL1_INV_GAIN Position */ 145 #define MXC_F_FCR_FCTRL1_INV_GAIN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL1_INV_GAIN_POS)) /**< FCTRL1_INV_GAIN Mask */ 146 147 #define MXC_F_FCR_FCTRL1_ATOMIC_POS 4 /**< FCTRL1_ATOMIC Position */ 148 #define MXC_F_FCR_FCTRL1_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL1_ATOMIC_POS)) /**< FCTRL1_ATOMIC Mask */ 149 150 #define MXC_F_FCR_FCTRL1_MU_POS 8 /**< FCTRL1_MU Position */ 151 #define MXC_F_FCR_FCTRL1_MU ((uint32_t)(0xFFFUL << MXC_F_FCR_FCTRL1_MU_POS)) /**< FCTRL1_MU Mask */ 152 153 #define MXC_F_FCR_FCTRL1_AC_TRIM_POS 23 /**< FCTRL1_AC_TRIM Position */ 154 #define MXC_F_FCR_FCTRL1_AC_TRIM ((uint32_t)(0x1FFUL << MXC_F_FCR_FCTRL1_AC_TRIM_POS)) /**< FCTRL1_AC_TRIM Mask */ 155 156 /**@} end of group FCR_FCTRL1_Register */ 157 158 /** 159 * @ingroup fcr_registers 160 * @defgroup FCR_FCTRL3 FCR_FCTRL3 161 * @brief Register 3. 162 * @{ 163 */ 164 #define MXC_F_FCR_FCTRL3_DONECNT_POS 0 /**< FCTRL3_DONECNT Position */ 165 #define MXC_F_FCR_FCTRL3_DONECNT ((uint32_t)(0xFFUL << MXC_F_FCR_FCTRL3_DONECNT_POS)) /**< FCTRL3_DONECNT Mask */ 166 167 /**@} end of group FCR_FCTRL3_Register */ 168 169 /** 170 * @ingroup fcr_registers 171 * @defgroup FCR_URVBOOTADDR FCR_URVBOOTADDR 172 * @brief Register 4. 173 * @{ 174 */ 175 #define MXC_F_FCR_URVBOOTADDR_BOOTADDR_POS 0 /**< URVBOOTADDR_BOOTADDR Position */ 176 #define MXC_F_FCR_URVBOOTADDR_BOOTADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FCR_URVBOOTADDR_BOOTADDR_POS)) /**< URVBOOTADDR_BOOTADDR Mask */ 177 178 /**@} end of group FCR_URVBOOTADDR_Register */ 179 180 /** 181 * @ingroup fcr_registers 182 * @defgroup FCR_URVCTRL FCR_URVCTRL 183 * @brief Register 5. 184 * @{ 185 */ 186 #define MXC_F_FCR_URVCTRL_SLEEP_REQ_POS 0 /**< URVCTRL_SLEEP_REQ Position */ 187 #define MXC_F_FCR_URVCTRL_SLEEP_REQ ((uint32_t)(0x1UL << MXC_F_FCR_URVCTRL_SLEEP_REQ_POS)) /**< URVCTRL_SLEEP_REQ Mask */ 188 189 #define MXC_F_FCR_URVCTRL_SLEEP_ACK_POS 1 /**< URVCTRL_SLEEP_ACK Position */ 190 #define MXC_F_FCR_URVCTRL_SLEEP_ACK ((uint32_t)(0x1UL << MXC_F_FCR_URVCTRL_SLEEP_ACK_POS)) /**< URVCTRL_SLEEP_ACK Mask */ 191 192 /**@} end of group FCR_URVCTRL_Register */ 193 194 /** 195 * @ingroup fcr_registers 196 * @defgroup FCR_GP FCR_GP 197 * @brief General Purpose Register. 198 * @{ 199 */ 200 #define MXC_F_FCR_GP_GP_POS 0 /**< GP_GP Position */ 201 #define MXC_F_FCR_GP_GP ((uint32_t)(0xFFFFFFFFUL << MXC_F_FCR_GP_GP_POS)) /**< GP_GP Mask */ 202 203 /**@} end of group FCR_GP_Register */ 204 205 /** 206 * @ingroup fcr_registers 207 * @defgroup FCR_TRIMCTRL FCR_TRIMCTRL 208 * @brief MSR ADC Trim Register. 209 * @{ 210 */ 211 #define MXC_F_FCR_TRIMCTRL_MSR_R1_POS 0 /**< TRIMCTRL_MSR_R1 Position */ 212 #define MXC_F_FCR_TRIMCTRL_MSR_R1 ((uint32_t)(0x3UL << MXC_F_FCR_TRIMCTRL_MSR_R1_POS)) /**< TRIMCTRL_MSR_R1 Mask */ 213 #define MXC_V_FCR_TRIMCTRL_MSR_R1_0K ((uint32_t)0x0UL) /**< TRIMCTRL_MSR_R1_0K Value */ 214 #define MXC_S_FCR_TRIMCTRL_MSR_R1_0K (MXC_V_FCR_TRIMCTRL_MSR_R1_0K << MXC_F_FCR_TRIMCTRL_MSR_R1_POS) /**< TRIMCTRL_MSR_R1_0K Setting */ 215 #define MXC_V_FCR_TRIMCTRL_MSR_R1_1P2K ((uint32_t)0x1UL) /**< TRIMCTRL_MSR_R1_1P2K Value */ 216 #define MXC_S_FCR_TRIMCTRL_MSR_R1_1P2K (MXC_V_FCR_TRIMCTRL_MSR_R1_1P2K << MXC_F_FCR_TRIMCTRL_MSR_R1_POS) /**< TRIMCTRL_MSR_R1_1P2K Setting */ 217 #define MXC_V_FCR_TRIMCTRL_MSR_R1_2P4K ((uint32_t)0x2UL) /**< TRIMCTRL_MSR_R1_2P4K Value */ 218 #define MXC_S_FCR_TRIMCTRL_MSR_R1_2P4K (MXC_V_FCR_TRIMCTRL_MSR_R1_2P4K << MXC_F_FCR_TRIMCTRL_MSR_R1_POS) /**< TRIMCTRL_MSR_R1_2P4K Setting */ 219 #define MXC_V_FCR_TRIMCTRL_MSR_R1_4P8K ((uint32_t)0x3UL) /**< TRIMCTRL_MSR_R1_4P8K Value */ 220 #define MXC_S_FCR_TRIMCTRL_MSR_R1_4P8K (MXC_V_FCR_TRIMCTRL_MSR_R1_4P8K << MXC_F_FCR_TRIMCTRL_MSR_R1_POS) /**< TRIMCTRL_MSR_R1_4P8K Setting */ 221 222 #define MXC_F_FCR_TRIMCTRL_MSR_R2_POS 2 /**< TRIMCTRL_MSR_R2 Position */ 223 #define MXC_F_FCR_TRIMCTRL_MSR_R2 ((uint32_t)(0x7UL << MXC_F_FCR_TRIMCTRL_MSR_R2_POS)) /**< TRIMCTRL_MSR_R2 Mask */ 224 #define MXC_V_FCR_TRIMCTRL_MSR_R2_OPEN ((uint32_t)0x0UL) /**< TRIMCTRL_MSR_R2_OPEN Value */ 225 #define MXC_S_FCR_TRIMCTRL_MSR_R2_OPEN (MXC_V_FCR_TRIMCTRL_MSR_R2_OPEN << MXC_F_FCR_TRIMCTRL_MSR_R2_POS) /**< TRIMCTRL_MSR_R2_OPEN Setting */ 226 #define MXC_V_FCR_TRIMCTRL_MSR_R2_3K ((uint32_t)0x4UL) /**< TRIMCTRL_MSR_R2_3K Value */ 227 #define MXC_S_FCR_TRIMCTRL_MSR_R2_3K (MXC_V_FCR_TRIMCTRL_MSR_R2_3K << MXC_F_FCR_TRIMCTRL_MSR_R2_POS) /**< TRIMCTRL_MSR_R2_3K Setting */ 228 #define MXC_V_FCR_TRIMCTRL_MSR_R2_6K ((uint32_t)0x5UL) /**< TRIMCTRL_MSR_R2_6K Value */ 229 #define MXC_S_FCR_TRIMCTRL_MSR_R2_6K (MXC_V_FCR_TRIMCTRL_MSR_R2_6K << MXC_F_FCR_TRIMCTRL_MSR_R2_POS) /**< TRIMCTRL_MSR_R2_6K Setting */ 230 #define MXC_V_FCR_TRIMCTRL_MSR_R2_12K ((uint32_t)0x6UL) /**< TRIMCTRL_MSR_R2_12K Value */ 231 #define MXC_S_FCR_TRIMCTRL_MSR_R2_12K (MXC_V_FCR_TRIMCTRL_MSR_R2_12K << MXC_F_FCR_TRIMCTRL_MSR_R2_POS) /**< TRIMCTRL_MSR_R2_12K Setting */ 232 #define MXC_V_FCR_TRIMCTRL_MSR_R2_24K ((uint32_t)0x7UL) /**< TRIMCTRL_MSR_R2_24K Value */ 233 #define MXC_S_FCR_TRIMCTRL_MSR_R2_24K (MXC_V_FCR_TRIMCTRL_MSR_R2_24K << MXC_F_FCR_TRIMCTRL_MSR_R2_POS) /**< TRIMCTRL_MSR_R2_24K Setting */ 234 235 /**@} end of group FCR_TRIMCTRL_Register */ 236 237 /** 238 * @ingroup fcr_registers 239 * @defgroup FCR_ERFOKS FCR_ERFOKS 240 * @brief ERFO Kick Start Register. 241 * @{ 242 */ 243 #define MXC_F_FCR_ERFOKS_CTRL_POS 0 /**< ERFOKS_CTRL Position */ 244 #define MXC_F_FCR_ERFOKS_CTRL ((uint32_t)(0xFFFFUL << MXC_F_FCR_ERFOKS_CTRL_POS)) /**< ERFOKS_CTRL Mask */ 245 246 /**@} end of group FCR_ERFOKS_Register */ 247 248 #ifdef __cplusplus 249 } 250 #endif 251 252 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_FCR_REGS_H_ 253
