1 /** 2 * @file srcc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SRCC Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SRCC_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SRCC_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup srcc 66 * @defgroup srcc_registers SRCC_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the SRCC Peripheral Module. 68 * @details SPIX Cache Controller Registers. 69 */ 70 71 /** 72 * @ingroup srcc_registers 73 * Structure type to access the SRCC Registers. 74 */ 75 typedef struct { 76 __I uint32_t cache_id; /**< <tt>\b 0x0000:</tt> SRCC CACHE_ID Register */ 77 __I uint32_t memcfg; /**< <tt>\b 0x0004:</tt> SRCC MEMCFG Register */ 78 __R uint32_t rsv_0x8_0xff[62]; 79 __IO uint32_t cache_ctrl; /**< <tt>\b 0x0100:</tt> SRCC CACHE_CTRL Register */ 80 __R uint32_t rsv_0x104_0x6ff[383]; 81 __IO uint32_t invalidate; /**< <tt>\b 0x0700:</tt> SRCC INVALIDATE Register */ 82 } mxc_srcc_regs_t; 83 84 /* Register offsets for module SRCC */ 85 /** 86 * @ingroup srcc_registers 87 * @defgroup SRCC_Register_Offsets Register Offsets 88 * @brief SRCC Peripheral Register Offsets from the SRCC Base Peripheral Address. 89 * @{ 90 */ 91 #define MXC_R_SRCC_CACHE_ID ((uint32_t)0x00000000UL) /**< Offset from SRCC Base Address: <tt> 0x0000</tt> */ 92 #define MXC_R_SRCC_MEMCFG ((uint32_t)0x00000004UL) /**< Offset from SRCC Base Address: <tt> 0x0004</tt> */ 93 #define MXC_R_SRCC_CACHE_CTRL ((uint32_t)0x00000100UL) /**< Offset from SRCC Base Address: <tt> 0x0100</tt> */ 94 #define MXC_R_SRCC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from SRCC Base Address: <tt> 0x0700</tt> */ 95 /**@} end of group srcc_registers */ 96 97 /** 98 * @ingroup srcc_registers 99 * @defgroup SRCC_CACHE_ID SRCC_CACHE_ID 100 * @brief Cache ID Register. 101 * @{ 102 */ 103 #define MXC_F_SRCC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */ 104 #define MXC_F_SRCC_CACHE_ID_RELNUM ((uint32_t)(0x3FUL << MXC_F_SRCC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM Mask */ 105 106 #define MXC_F_SRCC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */ 107 #define MXC_F_SRCC_CACHE_ID_PARTNUM ((uint32_t)(0xFUL << MXC_F_SRCC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM Mask */ 108 109 #define MXC_F_SRCC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */ 110 #define MXC_F_SRCC_CACHE_ID_CCHID ((uint32_t)(0x3FUL << MXC_F_SRCC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */ 111 112 /**@} end of group SRCC_CACHE_ID_Register */ 113 114 /** 115 * @ingroup srcc_registers 116 * @defgroup SRCC_MEMCFG SRCC_MEMCFG 117 * @brief Memory Configuration Register. 118 * @{ 119 */ 120 #define MXC_F_SRCC_MEMCFG_CCHSZ_POS 0 /**< MEMCFG_CCHSZ Position */ 121 #define MXC_F_SRCC_MEMCFG_CCHSZ ((uint32_t)(0xFFFFUL << MXC_F_SRCC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ Mask */ 122 123 #define MXC_F_SRCC_MEMCFG_MEMSZ_POS 16 /**< MEMCFG_MEMSZ Position */ 124 #define MXC_F_SRCC_MEMCFG_MEMSZ ((uint32_t)(0xFFFFUL << MXC_F_SRCC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ Mask */ 125 126 /**@} end of group SRCC_MEMCFG_Register */ 127 128 /** 129 * @ingroup srcc_registers 130 * @defgroup SRCC_CACHE_CTRL SRCC_CACHE_CTRL 131 * @brief Cache Control and Status Register. 132 * @{ 133 */ 134 #define MXC_F_SRCC_CACHE_CTRL_CACHE_EN_POS 0 /**< CACHE_CTRL_CACHE_EN Position */ 135 #define MXC_F_SRCC_CACHE_CTRL_CACHE_EN ((uint32_t)(0x1UL << MXC_F_SRCC_CACHE_CTRL_CACHE_EN_POS)) /**< CACHE_CTRL_CACHE_EN Mask */ 136 137 #define MXC_F_SRCC_CACHE_CTRL_WRITE_ALLOC_EN_POS 1 /**< CACHE_CTRL_WRITE_ALLOC_EN Position */ 138 #define MXC_F_SRCC_CACHE_CTRL_WRITE_ALLOC_EN ((uint32_t)(0x1UL << MXC_F_SRCC_CACHE_CTRL_WRITE_ALLOC_EN_POS)) /**< CACHE_CTRL_WRITE_ALLOC_EN Mask */ 139 140 #define MXC_F_SRCC_CACHE_CTRL_CWFST_DIS_POS 2 /**< CACHE_CTRL_CWFST_DIS Position */ 141 #define MXC_F_SRCC_CACHE_CTRL_CWFST_DIS ((uint32_t)(0x1UL << MXC_F_SRCC_CACHE_CTRL_CWFST_DIS_POS)) /**< CACHE_CTRL_CWFST_DIS Mask */ 142 143 #define MXC_F_SRCC_CACHE_CTRL_CACHE_RDY_POS 16 /**< CACHE_CTRL_CACHE_RDY Position */ 144 #define MXC_F_SRCC_CACHE_CTRL_CACHE_RDY ((uint32_t)(0x1UL << MXC_F_SRCC_CACHE_CTRL_CACHE_RDY_POS)) /**< CACHE_CTRL_CACHE_RDY Mask */ 145 146 /**@} end of group SRCC_CACHE_CTRL_Register */ 147 148 /** 149 * @ingroup srcc_registers 150 * @defgroup SRCC_INVALIDATE SRCC_INVALIDATE 151 * @brief Invalidate All Cache Contents. Any time this register location is written 152 * (regardless of the data value), the cache controller immediately begins 153 * invalidating the entire contents of the cache memory. The cache will be in 154 * bypass mode until the invalidate operation is complete. System software can 155 * examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the 156 * invalidate operation is complete. Note that it is not necessary to disable the 157 * cache controller prior to beginning this operation. Reads from this register 158 * always return 0. 159 * @{ 160 */ 161 #define MXC_F_SRCC_INVALIDATE_IA_POS 0 /**< INVALIDATE_IA Position */ 162 #define MXC_F_SRCC_INVALIDATE_IA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SRCC_INVALIDATE_IA_POS)) /**< INVALIDATE_IA Mask */ 163 164 /**@} end of group SRCC_INVALIDATE_Register */ 165 166 #ifdef __cplusplus 167 } 168 #endif 169 170 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SRCC_REGS_H_ 171
