1 /** 2 * @file spixr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPIXR Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SPIXR_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SPIXR_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup spixr 66 * @defgroup spixr_registers SPIXR_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the SPIXR Peripheral Module. 68 * @details SPIXR peripheral. 69 */ 70 71 /** 72 * @ingroup spixr_registers 73 * Structure type to access the SPIXR Registers. 74 */ 75 typedef struct { 76 union { 77 __IO uint32_t data32; /**< <tt>\b 0x00:</tt> SPIXR DATA32 Register */ 78 __IO uint16_t data16[2]; /**< <tt>\b 0x00:</tt> SPIXR DATA16 Register */ 79 __IO uint8_t data8[4]; /**< <tt>\b 0x00:</tt> SPIXR DATA8 Register */ 80 }; 81 __IO uint32_t ctrl1; /**< <tt>\b 0x04:</tt> SPIXR CTRL1 Register */ 82 __IO uint32_t ctrl2; /**< <tt>\b 0x08:</tt> SPIXR CTRL2 Register */ 83 __IO uint32_t ctrl3; /**< <tt>\b 0x0C:</tt> SPIXR CTRL3 Register */ 84 __IO uint32_t ss_time; /**< <tt>\b 0x10:</tt> SPIXR SS_TIME Register */ 85 __IO uint32_t brg_ctrl; /**< <tt>\b 0x14:</tt> SPIXR BRG_CTRL Register */ 86 __R uint32_t rsv_0x18; 87 __IO uint32_t dma; /**< <tt>\b 0x1C:</tt> SPIXR DMA Register */ 88 __IO uint32_t int_fl; /**< <tt>\b 0x20:</tt> SPIXR INT_FL Register */ 89 __IO uint32_t int_en; /**< <tt>\b 0x24:</tt> SPIXR INT_EN Register */ 90 __IO uint32_t wake_fl; /**< <tt>\b 0x28:</tt> SPIXR WAKE_FL Register */ 91 __IO uint32_t wake_en; /**< <tt>\b 0x2C:</tt> SPIXR WAKE_EN Register */ 92 __I uint32_t stat; /**< <tt>\b 0x30:</tt> SPIXR STAT Register */ 93 __IO uint32_t xmem_ctrl; /**< <tt>\b 0x34:</tt> SPIXR XMEM_CTRL Register */ 94 } mxc_spixr_regs_t; 95 96 /* Register offsets for module SPIXR */ 97 /** 98 * @ingroup spixr_registers 99 * @defgroup SPIXR_Register_Offsets Register Offsets 100 * @brief SPIXR Peripheral Register Offsets from the SPIXR Base Peripheral Address. 101 * @{ 102 */ 103 #define MXC_R_SPIXR_DATA32 ((uint32_t)0x00000000UL) /**< Offset from SPIXR Base Address: <tt> 0x0000</tt> */ 104 #define MXC_R_SPIXR_DATA16 ((uint32_t)0x00000000UL) /**< Offset from SPIXR Base Address: <tt> 0x0000</tt> */ 105 #define MXC_R_SPIXR_DATA8 ((uint32_t)0x00000000UL) /**< Offset from SPIXR Base Address: <tt> 0x0000</tt> */ 106 #define MXC_R_SPIXR_CTRL1 ((uint32_t)0x00000004UL) /**< Offset from SPIXR Base Address: <tt> 0x0004</tt> */ 107 #define MXC_R_SPIXR_CTRL2 ((uint32_t)0x00000008UL) /**< Offset from SPIXR Base Address: <tt> 0x0008</tt> */ 108 #define MXC_R_SPIXR_CTRL3 ((uint32_t)0x0000000CUL) /**< Offset from SPIXR Base Address: <tt> 0x000C</tt> */ 109 #define MXC_R_SPIXR_SS_TIME ((uint32_t)0x00000010UL) /**< Offset from SPIXR Base Address: <tt> 0x0010</tt> */ 110 #define MXC_R_SPIXR_BRG_CTRL ((uint32_t)0x00000014UL) /**< Offset from SPIXR Base Address: <tt> 0x0014</tt> */ 111 #define MXC_R_SPIXR_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPIXR Base Address: <tt> 0x001C</tt> */ 112 #define MXC_R_SPIXR_INT_FL ((uint32_t)0x00000020UL) /**< Offset from SPIXR Base Address: <tt> 0x0020</tt> */ 113 #define MXC_R_SPIXR_INT_EN ((uint32_t)0x00000024UL) /**< Offset from SPIXR Base Address: <tt> 0x0024</tt> */ 114 #define MXC_R_SPIXR_WAKE_FL ((uint32_t)0x00000028UL) /**< Offset from SPIXR Base Address: <tt> 0x0028</tt> */ 115 #define MXC_R_SPIXR_WAKE_EN ((uint32_t)0x0000002CUL) /**< Offset from SPIXR Base Address: <tt> 0x002C</tt> */ 116 #define MXC_R_SPIXR_STAT ((uint32_t)0x00000030UL) /**< Offset from SPIXR Base Address: <tt> 0x0030</tt> */ 117 #define MXC_R_SPIXR_XMEM_CTRL ((uint32_t)0x00000034UL) /**< Offset from SPIXR Base Address: <tt> 0x0034</tt> */ 118 /**@} end of group spixr_registers */ 119 120 /** 121 * @ingroup spixr_registers 122 * @defgroup SPIXR_DATA32 SPIXR_DATA32 123 * @brief Register for reading and writing the FIFO. 124 * @{ 125 */ 126 #define MXC_F_SPIXR_DATA32_DATA_POS 0 /**< DATA32_DATA Position */ 127 #define MXC_F_SPIXR_DATA32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPIXR_DATA32_DATA_POS)) /**< DATA32_DATA Mask */ 128 129 /**@} end of group SPIXR_DATA32_Register */ 130 131 /** 132 * @ingroup spixr_registers 133 * @defgroup SPIXR_DATA16 SPIXR_DATA16 134 * @brief Register for reading and writing the FIFO. 135 * @{ 136 */ 137 #define MXC_F_SPIXR_DATA16_DATA_POS 0 /**< DATA16_DATA Position */ 138 #define MXC_F_SPIXR_DATA16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPIXR_DATA16_DATA_POS)) /**< DATA16_DATA Mask */ 139 140 /**@} end of group SPIXR_DATA16_Register */ 141 142 /** 143 * @ingroup spixr_registers 144 * @defgroup SPIXR_DATA8 SPIXR_DATA8 145 * @brief Register for reading and writing the FIFO. 146 * @{ 147 */ 148 #define MXC_F_SPIXR_DATA8_DATA_POS 0 /**< DATA8_DATA Position */ 149 #define MXC_F_SPIXR_DATA8_DATA ((uint8_t)(0xFFUL << MXC_F_SPIXR_DATA8_DATA_POS)) /**< DATA8_DATA Mask */ 150 151 /**@} end of group SPIXR_DATA8_Register */ 152 153 /** 154 * @ingroup spixr_registers 155 * @defgroup SPIXR_CTRL1 SPIXR_CTRL1 156 * @brief Register for controlling SPI peripheral. 157 * @{ 158 */ 159 #define MXC_F_SPIXR_CTRL1_SPIEN_POS 0 /**< CTRL1_SPIEN Position */ 160 #define MXC_F_SPIXR_CTRL1_SPIEN ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_SPIEN_POS)) /**< CTRL1_SPIEN Mask */ 161 162 #define MXC_F_SPIXR_CTRL1_MMEN_POS 1 /**< CTRL1_MMEN Position */ 163 #define MXC_F_SPIXR_CTRL1_MMEN ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_MMEN_POS)) /**< CTRL1_MMEN Mask */ 164 165 #define MXC_F_SPIXR_CTRL1_SSIO_POS 4 /**< CTRL1_SSIO Position */ 166 #define MXC_F_SPIXR_CTRL1_SSIO ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_SSIO_POS)) /**< CTRL1_SSIO Mask */ 167 168 #define MXC_F_SPIXR_CTRL1_TX_START_POS 5 /**< CTRL1_TX_START Position */ 169 #define MXC_F_SPIXR_CTRL1_TX_START ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_TX_START_POS)) /**< CTRL1_TX_START Mask */ 170 171 #define MXC_F_SPIXR_CTRL1_SS_CTRL_POS 8 /**< CTRL1_SS_CTRL Position */ 172 #define MXC_F_SPIXR_CTRL1_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_SS_CTRL_POS)) /**< CTRL1_SS_CTRL Mask */ 173 174 #define MXC_F_SPIXR_CTRL1_SS_POS 16 /**< CTRL1_SS Position */ 175 #define MXC_F_SPIXR_CTRL1_SS ((uint32_t)(0xFFUL << MXC_F_SPIXR_CTRL1_SS_POS)) /**< CTRL1_SS Mask */ 176 #define MXC_V_SPIXR_CTRL1_SS_SS0 ((uint32_t)0x1UL) /**< CTRL1_SS_SS0 Value */ 177 #define MXC_S_SPIXR_CTRL1_SS_SS0 (MXC_V_SPIXR_CTRL1_SS_SS0 << MXC_F_SPIXR_CTRL1_SS_POS) /**< CTRL1_SS_SS0 Setting */ 178 #define MXC_V_SPIXR_CTRL1_SS_SS1 ((uint32_t)0x2UL) /**< CTRL1_SS_SS1 Value */ 179 #define MXC_S_SPIXR_CTRL1_SS_SS1 (MXC_V_SPIXR_CTRL1_SS_SS1 << MXC_F_SPIXR_CTRL1_SS_POS) /**< CTRL1_SS_SS1 Setting */ 180 #define MXC_V_SPIXR_CTRL1_SS_SS2 ((uint32_t)0x4UL) /**< CTRL1_SS_SS2 Value */ 181 #define MXC_S_SPIXR_CTRL1_SS_SS2 (MXC_V_SPIXR_CTRL1_SS_SS2 << MXC_F_SPIXR_CTRL1_SS_POS) /**< CTRL1_SS_SS2 Setting */ 182 #define MXC_V_SPIXR_CTRL1_SS_SS3 ((uint32_t)0x8UL) /**< CTRL1_SS_SS3 Value */ 183 #define MXC_S_SPIXR_CTRL1_SS_SS3 (MXC_V_SPIXR_CTRL1_SS_SS3 << MXC_F_SPIXR_CTRL1_SS_POS) /**< CTRL1_SS_SS3 Setting */ 184 #define MXC_V_SPIXR_CTRL1_SS_SS4 ((uint32_t)0x10UL) /**< CTRL1_SS_SS4 Value */ 185 #define MXC_S_SPIXR_CTRL1_SS_SS4 (MXC_V_SPIXR_CTRL1_SS_SS4 << MXC_F_SPIXR_CTRL1_SS_POS) /**< CTRL1_SS_SS4 Setting */ 186 #define MXC_V_SPIXR_CTRL1_SS_SS5 ((uint32_t)0x20UL) /**< CTRL1_SS_SS5 Value */ 187 #define MXC_S_SPIXR_CTRL1_SS_SS5 (MXC_V_SPIXR_CTRL1_SS_SS5 << MXC_F_SPIXR_CTRL1_SS_POS) /**< CTRL1_SS_SS5 Setting */ 188 #define MXC_V_SPIXR_CTRL1_SS_SS6 ((uint32_t)0x40UL) /**< CTRL1_SS_SS6 Value */ 189 #define MXC_S_SPIXR_CTRL1_SS_SS6 (MXC_V_SPIXR_CTRL1_SS_SS6 << MXC_F_SPIXR_CTRL1_SS_POS) /**< CTRL1_SS_SS6 Setting */ 190 #define MXC_V_SPIXR_CTRL1_SS_SS7 ((uint32_t)0x80UL) /**< CTRL1_SS_SS7 Value */ 191 #define MXC_S_SPIXR_CTRL1_SS_SS7 (MXC_V_SPIXR_CTRL1_SS_SS7 << MXC_F_SPIXR_CTRL1_SS_POS) /**< CTRL1_SS_SS7 Setting */ 192 193 /**@} end of group SPIXR_CTRL1_Register */ 194 195 /** 196 * @ingroup spixr_registers 197 * @defgroup SPIXR_CTRL2 SPIXR_CTRL2 198 * @brief Register for controlling SPI peripheral. 199 * @{ 200 */ 201 #define MXC_F_SPIXR_CTRL2_TX_NUM_CHAR_POS 0 /**< CTRL2_TX_NUM_CHAR Position */ 202 #define MXC_F_SPIXR_CTRL2_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPIXR_CTRL2_TX_NUM_CHAR_POS)) /**< CTRL2_TX_NUM_CHAR Mask */ 203 204 #define MXC_F_SPIXR_CTRL2_RX_NUM_CHAR_POS 16 /**< CTRL2_RX_NUM_CHAR Position */ 205 #define MXC_F_SPIXR_CTRL2_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPIXR_CTRL2_RX_NUM_CHAR_POS)) /**< CTRL2_RX_NUM_CHAR Mask */ 206 207 /**@} end of group SPIXR_CTRL2_Register */ 208 209 /** 210 * @ingroup spixr_registers 211 * @defgroup SPIXR_CTRL3 SPIXR_CTRL3 212 * @brief Register for controlling SPI peripheral. 213 * @{ 214 */ 215 #define MXC_F_SPIXR_CTRL3_CPHA_POS 0 /**< CTRL3_CPHA Position */ 216 #define MXC_F_SPIXR_CTRL3_CPHA ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL3_CPHA_POS)) /**< CTRL3_CPHA Mask */ 217 218 #define MXC_F_SPIXR_CTRL3_CPOL_POS 1 /**< CTRL3_CPOL Position */ 219 #define MXC_F_SPIXR_CTRL3_CPOL ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL3_CPOL_POS)) /**< CTRL3_CPOL Mask */ 220 221 #define MXC_F_SPIXR_CTRL3_SCLK_FB_INV_POS 4 /**< CTRL3_SCLK_FB_INV Position */ 222 #define MXC_F_SPIXR_CTRL3_SCLK_FB_INV ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL3_SCLK_FB_INV_POS)) /**< CTRL3_SCLK_FB_INV Mask */ 223 224 #define MXC_F_SPIXR_CTRL3_NUMBITS_POS 8 /**< CTRL3_NUMBITS Position */ 225 #define MXC_F_SPIXR_CTRL3_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPIXR_CTRL3_NUMBITS_POS)) /**< CTRL3_NUMBITS Mask */ 226 #define MXC_V_SPIXR_CTRL3_NUMBITS_0 ((uint32_t)0x0UL) /**< CTRL3_NUMBITS_0 Value */ 227 #define MXC_S_SPIXR_CTRL3_NUMBITS_0 (MXC_V_SPIXR_CTRL3_NUMBITS_0 << MXC_F_SPIXR_CTRL3_NUMBITS_POS) /**< CTRL3_NUMBITS_0 Setting */ 228 229 #define MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS 12 /**< CTRL3_DATA_WIDTH Position */ 230 #define MXC_F_SPIXR_CTRL3_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS)) /**< CTRL3_DATA_WIDTH Mask */ 231 #define MXC_V_SPIXR_CTRL3_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL3_DATA_WIDTH_MONO Value */ 232 #define MXC_S_SPIXR_CTRL3_DATA_WIDTH_MONO (MXC_V_SPIXR_CTRL3_DATA_WIDTH_MONO << MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS) /**< CTRL3_DATA_WIDTH_MONO Setting */ 233 #define MXC_V_SPIXR_CTRL3_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL3_DATA_WIDTH_DUAL Value */ 234 #define MXC_S_SPIXR_CTRL3_DATA_WIDTH_DUAL (MXC_V_SPIXR_CTRL3_DATA_WIDTH_DUAL << MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS) /**< CTRL3_DATA_WIDTH_DUAL Setting */ 235 #define MXC_V_SPIXR_CTRL3_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL3_DATA_WIDTH_QUAD Value */ 236 #define MXC_S_SPIXR_CTRL3_DATA_WIDTH_QUAD (MXC_V_SPIXR_CTRL3_DATA_WIDTH_QUAD << MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS) /**< CTRL3_DATA_WIDTH_QUAD Setting */ 237 238 #define MXC_F_SPIXR_CTRL3_THREE_WIRE_POS 15 /**< CTRL3_THREE_WIRE Position */ 239 #define MXC_F_SPIXR_CTRL3_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL3_THREE_WIRE_POS)) /**< CTRL3_THREE_WIRE Mask */ 240 241 #define MXC_F_SPIXR_CTRL3_SSPOL_POS 16 /**< CTRL3_SSPOL Position */ 242 #define MXC_F_SPIXR_CTRL3_SSPOL ((uint32_t)(0xFFUL << MXC_F_SPIXR_CTRL3_SSPOL_POS)) /**< CTRL3_SSPOL Mask */ 243 #define MXC_V_SPIXR_CTRL3_SSPOL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL3_SSPOL_SS0_HIGH Value */ 244 #define MXC_S_SPIXR_CTRL3_SSPOL_SS0_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS0_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) /**< CTRL3_SSPOL_SS0_HIGH Setting */ 245 #define MXC_V_SPIXR_CTRL3_SSPOL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL3_SSPOL_SS1_HIGH Value */ 246 #define MXC_S_SPIXR_CTRL3_SSPOL_SS1_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS1_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) /**< CTRL3_SSPOL_SS1_HIGH Setting */ 247 #define MXC_V_SPIXR_CTRL3_SSPOL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL3_SSPOL_SS2_HIGH Value */ 248 #define MXC_S_SPIXR_CTRL3_SSPOL_SS2_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS2_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) /**< CTRL3_SSPOL_SS2_HIGH Setting */ 249 #define MXC_V_SPIXR_CTRL3_SSPOL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL3_SSPOL_SS3_HIGH Value */ 250 #define MXC_S_SPIXR_CTRL3_SSPOL_SS3_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS3_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) /**< CTRL3_SSPOL_SS3_HIGH Setting */ 251 #define MXC_V_SPIXR_CTRL3_SSPOL_SS4_HIGH ((uint32_t)0x10UL) /**< CTRL3_SSPOL_SS4_HIGH Value */ 252 #define MXC_S_SPIXR_CTRL3_SSPOL_SS4_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS4_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) /**< CTRL3_SSPOL_SS4_HIGH Setting */ 253 #define MXC_V_SPIXR_CTRL3_SSPOL_SS5_HIGH ((uint32_t)0x20UL) /**< CTRL3_SSPOL_SS5_HIGH Value */ 254 #define MXC_S_SPIXR_CTRL3_SSPOL_SS5_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS5_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) /**< CTRL3_SSPOL_SS5_HIGH Setting */ 255 #define MXC_V_SPIXR_CTRL3_SSPOL_SS6_HIGH ((uint32_t)0x40UL) /**< CTRL3_SSPOL_SS6_HIGH Value */ 256 #define MXC_S_SPIXR_CTRL3_SSPOL_SS6_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS6_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) /**< CTRL3_SSPOL_SS6_HIGH Setting */ 257 #define MXC_V_SPIXR_CTRL3_SSPOL_SS7_HIGH ((uint32_t)0x80UL) /**< CTRL3_SSPOL_SS7_HIGH Value */ 258 #define MXC_S_SPIXR_CTRL3_SSPOL_SS7_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS7_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) /**< CTRL3_SSPOL_SS7_HIGH Setting */ 259 260 /**@} end of group SPIXR_CTRL3_Register */ 261 262 /** 263 * @ingroup spixr_registers 264 * @defgroup SPIXR_SS_TIME SPIXR_SS_TIME 265 * @brief Register for controlling SPI peripheral. 266 * @{ 267 */ 268 #define MXC_F_SPIXR_SS_TIME_SSACT1_POS 0 /**< SS_TIME_SSACT1 Position */ 269 #define MXC_F_SPIXR_SS_TIME_SSACT1 ((uint32_t)(0xFFUL << MXC_F_SPIXR_SS_TIME_SSACT1_POS)) /**< SS_TIME_SSACT1 Mask */ 270 #define MXC_V_SPIXR_SS_TIME_SSACT1_256 ((uint32_t)0x0UL) /**< SS_TIME_SSACT1_256 Value */ 271 #define MXC_S_SPIXR_SS_TIME_SSACT1_256 (MXC_V_SPIXR_SS_TIME_SSACT1_256 << MXC_F_SPIXR_SS_TIME_SSACT1_POS) /**< SS_TIME_SSACT1_256 Setting */ 272 273 #define MXC_F_SPIXR_SS_TIME_SSACT2_POS 8 /**< SS_TIME_SSACT2 Position */ 274 #define MXC_F_SPIXR_SS_TIME_SSACT2 ((uint32_t)(0xFFUL << MXC_F_SPIXR_SS_TIME_SSACT2_POS)) /**< SS_TIME_SSACT2 Mask */ 275 #define MXC_V_SPIXR_SS_TIME_SSACT2_256 ((uint32_t)0x0UL) /**< SS_TIME_SSACT2_256 Value */ 276 #define MXC_S_SPIXR_SS_TIME_SSACT2_256 (MXC_V_SPIXR_SS_TIME_SSACT2_256 << MXC_F_SPIXR_SS_TIME_SSACT2_POS) /**< SS_TIME_SSACT2_256 Setting */ 277 278 #define MXC_F_SPIXR_SS_TIME_SSINACT_POS 16 /**< SS_TIME_SSINACT Position */ 279 #define MXC_F_SPIXR_SS_TIME_SSINACT ((uint32_t)(0xFFUL << MXC_F_SPIXR_SS_TIME_SSINACT_POS)) /**< SS_TIME_SSINACT Mask */ 280 #define MXC_V_SPIXR_SS_TIME_SSINACT_256 ((uint32_t)0x0UL) /**< SS_TIME_SSINACT_256 Value */ 281 #define MXC_S_SPIXR_SS_TIME_SSINACT_256 (MXC_V_SPIXR_SS_TIME_SSINACT_256 << MXC_F_SPIXR_SS_TIME_SSINACT_POS) /**< SS_TIME_SSINACT_256 Setting */ 282 283 /**@} end of group SPIXR_SS_TIME_Register */ 284 285 /** 286 * @ingroup spixr_registers 287 * @defgroup SPIXR_BRG_CTRL SPIXR_BRG_CTRL 288 * @brief Register for controlling SPI clock rate. 289 * @{ 290 */ 291 #define MXC_F_SPIXR_BRG_CTRL_LOW_POS 0 /**< BRG_CTRL_LOW Position */ 292 #define MXC_F_SPIXR_BRG_CTRL_LOW ((uint32_t)(0xFFUL << MXC_F_SPIXR_BRG_CTRL_LOW_POS)) /**< BRG_CTRL_LOW Mask */ 293 #define MXC_V_SPIXR_BRG_CTRL_LOW_DIS ((uint32_t)0x0UL) /**< BRG_CTRL_LOW_DIS Value */ 294 #define MXC_S_SPIXR_BRG_CTRL_LOW_DIS (MXC_V_SPIXR_BRG_CTRL_LOW_DIS << MXC_F_SPIXR_BRG_CTRL_LOW_POS) /**< BRG_CTRL_LOW_DIS Setting */ 295 296 #define MXC_F_SPIXR_BRG_CTRL_HI_POS 8 /**< BRG_CTRL_HI Position */ 297 #define MXC_F_SPIXR_BRG_CTRL_HI ((uint32_t)(0xFFUL << MXC_F_SPIXR_BRG_CTRL_HI_POS)) /**< BRG_CTRL_HI Mask */ 298 #define MXC_V_SPIXR_BRG_CTRL_HI_DIS ((uint32_t)0x0UL) /**< BRG_CTRL_HI_DIS Value */ 299 #define MXC_S_SPIXR_BRG_CTRL_HI_DIS (MXC_V_SPIXR_BRG_CTRL_HI_DIS << MXC_F_SPIXR_BRG_CTRL_HI_POS) /**< BRG_CTRL_HI_DIS Setting */ 300 301 #define MXC_F_SPIXR_BRG_CTRL_SCALE_POS 16 /**< BRG_CTRL_SCALE Position */ 302 #define MXC_F_SPIXR_BRG_CTRL_SCALE ((uint32_t)(0xFUL << MXC_F_SPIXR_BRG_CTRL_SCALE_POS)) /**< BRG_CTRL_SCALE Mask */ 303 304 /**@} end of group SPIXR_BRG_CTRL_Register */ 305 306 /** 307 * @ingroup spixr_registers 308 * @defgroup SPIXR_DMA SPIXR_DMA 309 * @brief Register for controlling DMA. 310 * @{ 311 */ 312 #define MXC_F_SPIXR_DMA_TX_FIFO_LEVEL_POS 0 /**< DMA_TX_FIFO_LEVEL Position */ 313 #define MXC_F_SPIXR_DMA_TX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPIXR_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */ 314 315 #define MXC_F_SPIXR_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */ 316 #define MXC_F_SPIXR_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */ 317 318 #define MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS 7 /**< DMA_TX_FIFO_CLEAR Position */ 319 #define MXC_F_SPIXR_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */ 320 321 #define MXC_F_SPIXR_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */ 322 #define MXC_F_SPIXR_DMA_TX_FIFO_CNT ((uint32_t)(0x1FUL << MXC_F_SPIXR_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */ 323 324 #define MXC_F_SPIXR_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */ 325 #define MXC_F_SPIXR_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */ 326 327 #define MXC_F_SPIXR_DMA_RX_FIFO_LEVEL_POS 16 /**< DMA_RX_FIFO_LEVEL Position */ 328 #define MXC_F_SPIXR_DMA_RX_FIFO_LEVEL ((uint32_t)(0x3FUL << MXC_F_SPIXR_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */ 329 330 #define MXC_F_SPIXR_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */ 331 #define MXC_F_SPIXR_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */ 332 333 #define MXC_F_SPIXR_DMA_RX_FIFO_CLEAR_POS 23 /**< DMA_RX_FIFO_CLEAR Position */ 334 #define MXC_F_SPIXR_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */ 335 336 #define MXC_F_SPIXR_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */ 337 #define MXC_F_SPIXR_DMA_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPIXR_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */ 338 339 #define MXC_F_SPIXR_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */ 340 #define MXC_F_SPIXR_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */ 341 342 /**@} end of group SPIXR_DMA_Register */ 343 344 /** 345 * @ingroup spixr_registers 346 * @defgroup SPIXR_INT_FL SPIXR_INT_FL 347 * @brief Register for reading and clearing interrupt flags. All bits are write 1 to 348 * clear. 349 * @{ 350 */ 351 #define MXC_F_SPIXR_INT_FL_TX_THRESH_POS 0 /**< INT_FL_TX_THRESH Position */ 352 #define MXC_F_SPIXR_INT_FL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_TX_THRESH_POS)) /**< INT_FL_TX_THRESH Mask */ 353 354 #define MXC_F_SPIXR_INT_FL_TX_EMPTY_POS 1 /**< INT_FL_TX_EMPTY Position */ 355 #define MXC_F_SPIXR_INT_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_TX_EMPTY_POS)) /**< INT_FL_TX_EMPTY Mask */ 356 357 #define MXC_F_SPIXR_INT_FL_RX_THRESH_POS 2 /**< INT_FL_RX_THRESH Position */ 358 #define MXC_F_SPIXR_INT_FL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_RX_THRESH_POS)) /**< INT_FL_RX_THRESH Mask */ 359 360 #define MXC_F_SPIXR_INT_FL_RX_FULL_POS 3 /**< INT_FL_RX_FULL Position */ 361 #define MXC_F_SPIXR_INT_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_RX_FULL_POS)) /**< INT_FL_RX_FULL Mask */ 362 363 #define MXC_F_SPIXR_INT_FL_SSA_POS 4 /**< INT_FL_SSA Position */ 364 #define MXC_F_SPIXR_INT_FL_SSA ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_SSA_POS)) /**< INT_FL_SSA Mask */ 365 366 #define MXC_F_SPIXR_INT_FL_SSD_POS 5 /**< INT_FL_SSD Position */ 367 #define MXC_F_SPIXR_INT_FL_SSD ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_SSD_POS)) /**< INT_FL_SSD Mask */ 368 369 #define MXC_F_SPIXR_INT_FL_FAULT_POS 8 /**< INT_FL_FAULT Position */ 370 #define MXC_F_SPIXR_INT_FL_FAULT ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_FAULT_POS)) /**< INT_FL_FAULT Mask */ 371 372 #define MXC_F_SPIXR_INT_FL_ABORT_POS 9 /**< INT_FL_ABORT Position */ 373 #define MXC_F_SPIXR_INT_FL_ABORT ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_ABORT_POS)) /**< INT_FL_ABORT Mask */ 374 375 #define MXC_F_SPIXR_INT_FL_M_DONE_POS 11 /**< INT_FL_M_DONE Position */ 376 #define MXC_F_SPIXR_INT_FL_M_DONE ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_M_DONE_POS)) /**< INT_FL_M_DONE Mask */ 377 378 #define MXC_F_SPIXR_INT_FL_TX_OVR_POS 12 /**< INT_FL_TX_OVR Position */ 379 #define MXC_F_SPIXR_INT_FL_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_TX_OVR_POS)) /**< INT_FL_TX_OVR Mask */ 380 381 #define MXC_F_SPIXR_INT_FL_TX_UND_POS 13 /**< INT_FL_TX_UND Position */ 382 #define MXC_F_SPIXR_INT_FL_TX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_TX_UND_POS)) /**< INT_FL_TX_UND Mask */ 383 384 #define MXC_F_SPIXR_INT_FL_RX_OVR_POS 14 /**< INT_FL_RX_OVR Position */ 385 #define MXC_F_SPIXR_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */ 386 387 #define MXC_F_SPIXR_INT_FL_RX_UND_POS 15 /**< INT_FL_RX_UND Position */ 388 #define MXC_F_SPIXR_INT_FL_RX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_RX_UND_POS)) /**< INT_FL_RX_UND Mask */ 389 390 /**@} end of group SPIXR_INT_FL_Register */ 391 392 /** 393 * @ingroup spixr_registers 394 * @defgroup SPIXR_INT_EN SPIXR_INT_EN 395 * @brief Register for enabling interrupts. 396 * @{ 397 */ 398 #define MXC_F_SPIXR_INT_EN_TX_THRESH_POS 0 /**< INT_EN_TX_THRESH Position */ 399 #define MXC_F_SPIXR_INT_EN_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_TX_THRESH_POS)) /**< INT_EN_TX_THRESH Mask */ 400 401 #define MXC_F_SPIXR_INT_EN_TX_EMPTY_POS 1 /**< INT_EN_TX_EMPTY Position */ 402 #define MXC_F_SPIXR_INT_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_TX_EMPTY_POS)) /**< INT_EN_TX_EMPTY Mask */ 403 404 #define MXC_F_SPIXR_INT_EN_RX_THRESH_POS 2 /**< INT_EN_RX_THRESH Position */ 405 #define MXC_F_SPIXR_INT_EN_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_RX_THRESH_POS)) /**< INT_EN_RX_THRESH Mask */ 406 407 #define MXC_F_SPIXR_INT_EN_RX_FULL_POS 3 /**< INT_EN_RX_FULL Position */ 408 #define MXC_F_SPIXR_INT_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_RX_FULL_POS)) /**< INT_EN_RX_FULL Mask */ 409 410 #define MXC_F_SPIXR_INT_EN_SSA_POS 4 /**< INT_EN_SSA Position */ 411 #define MXC_F_SPIXR_INT_EN_SSA ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_SSA_POS)) /**< INT_EN_SSA Mask */ 412 413 #define MXC_F_SPIXR_INT_EN_SSD_POS 5 /**< INT_EN_SSD Position */ 414 #define MXC_F_SPIXR_INT_EN_SSD ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_SSD_POS)) /**< INT_EN_SSD Mask */ 415 416 #define MXC_F_SPIXR_INT_EN_FAULT_POS 8 /**< INT_EN_FAULT Position */ 417 #define MXC_F_SPIXR_INT_EN_FAULT ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_FAULT_POS)) /**< INT_EN_FAULT Mask */ 418 419 #define MXC_F_SPIXR_INT_EN_ABORT_POS 9 /**< INT_EN_ABORT Position */ 420 #define MXC_F_SPIXR_INT_EN_ABORT ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_ABORT_POS)) /**< INT_EN_ABORT Mask */ 421 422 #define MXC_F_SPIXR_INT_EN_M_DONE_POS 11 /**< INT_EN_M_DONE Position */ 423 #define MXC_F_SPIXR_INT_EN_M_DONE ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_M_DONE_POS)) /**< INT_EN_M_DONE Mask */ 424 425 #define MXC_F_SPIXR_INT_EN_TX_OVR_POS 12 /**< INT_EN_TX_OVR Position */ 426 #define MXC_F_SPIXR_INT_EN_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_TX_OVR_POS)) /**< INT_EN_TX_OVR Mask */ 427 428 #define MXC_F_SPIXR_INT_EN_TX_UND_POS 13 /**< INT_EN_TX_UND Position */ 429 #define MXC_F_SPIXR_INT_EN_TX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_TX_UND_POS)) /**< INT_EN_TX_UND Mask */ 430 431 #define MXC_F_SPIXR_INT_EN_RX_OVR_POS 14 /**< INT_EN_RX_OVR Position */ 432 #define MXC_F_SPIXR_INT_EN_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_RX_OVR_POS)) /**< INT_EN_RX_OVR Mask */ 433 434 #define MXC_F_SPIXR_INT_EN_RX_UND_POS 15 /**< INT_EN_RX_UND Position */ 435 #define MXC_F_SPIXR_INT_EN_RX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_RX_UND_POS)) /**< INT_EN_RX_UND Mask */ 436 437 /**@} end of group SPIXR_INT_EN_Register */ 438 439 /** 440 * @ingroup spixr_registers 441 * @defgroup SPIXR_WAKE_FL SPIXR_WAKE_FL 442 * @brief Register for wake up flags. All bits in this register are write 1 to clear. 443 * @{ 444 */ 445 #define MXC_F_SPIXR_WAKE_FL_TX_THRESH_POS 0 /**< WAKE_FL_TX_THRESH Position */ 446 #define MXC_F_SPIXR_WAKE_FL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_FL_TX_THRESH_POS)) /**< WAKE_FL_TX_THRESH Mask */ 447 448 #define MXC_F_SPIXR_WAKE_FL_TX_EMPTY_POS 1 /**< WAKE_FL_TX_EMPTY Position */ 449 #define MXC_F_SPIXR_WAKE_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_FL_TX_EMPTY_POS)) /**< WAKE_FL_TX_EMPTY Mask */ 450 451 #define MXC_F_SPIXR_WAKE_FL_RX_THRESH_POS 2 /**< WAKE_FL_RX_THRESH Position */ 452 #define MXC_F_SPIXR_WAKE_FL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_FL_RX_THRESH_POS)) /**< WAKE_FL_RX_THRESH Mask */ 453 454 #define MXC_F_SPIXR_WAKE_FL_RX_FULL_POS 3 /**< WAKE_FL_RX_FULL Position */ 455 #define MXC_F_SPIXR_WAKE_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_FL_RX_FULL_POS)) /**< WAKE_FL_RX_FULL Mask */ 456 457 /**@} end of group SPIXR_WAKE_FL_Register */ 458 459 /** 460 * @ingroup spixr_registers 461 * @defgroup SPIXR_WAKE_EN SPIXR_WAKE_EN 462 * @brief Register for wake up enable. 463 * @{ 464 */ 465 #define MXC_F_SPIXR_WAKE_EN_TX_THRESH_POS 0 /**< WAKE_EN_TX_THRESH Position */ 466 #define MXC_F_SPIXR_WAKE_EN_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_EN_TX_THRESH_POS)) /**< WAKE_EN_TX_THRESH Mask */ 467 468 #define MXC_F_SPIXR_WAKE_EN_TX_EMPTY_POS 1 /**< WAKE_EN_TX_EMPTY Position */ 469 #define MXC_F_SPIXR_WAKE_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_EN_TX_EMPTY_POS)) /**< WAKE_EN_TX_EMPTY Mask */ 470 471 #define MXC_F_SPIXR_WAKE_EN_RX_THRESH_POS 2 /**< WAKE_EN_RX_THRESH Position */ 472 #define MXC_F_SPIXR_WAKE_EN_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_EN_RX_THRESH_POS)) /**< WAKE_EN_RX_THRESH Mask */ 473 474 #define MXC_F_SPIXR_WAKE_EN_RX_FULL_POS 3 /**< WAKE_EN_RX_FULL Position */ 475 #define MXC_F_SPIXR_WAKE_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_EN_RX_FULL_POS)) /**< WAKE_EN_RX_FULL Mask */ 476 477 /**@} end of group SPIXR_WAKE_EN_Register */ 478 479 /** 480 * @ingroup spixr_registers 481 * @defgroup SPIXR_STAT SPIXR_STAT 482 * @brief SPI Status register. 483 * @{ 484 */ 485 #define MXC_F_SPIXR_STAT_BUSY_POS 0 /**< STAT_BUSY Position */ 486 #define MXC_F_SPIXR_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPIXR_STAT_BUSY_POS)) /**< STAT_BUSY Mask */ 487 488 /**@} end of group SPIXR_STAT_Register */ 489 490 /** 491 * @ingroup spixr_registers 492 * @defgroup SPIXR_XMEM_CTRL SPIXR_XMEM_CTRL 493 * @brief Register to control external memory. 494 * @{ 495 */ 496 #define MXC_F_SPIXR_XMEM_CTRL_RD_CMD_POS 0 /**< XMEM_CTRL_RD_CMD Position */ 497 #define MXC_F_SPIXR_XMEM_CTRL_RD_CMD ((uint32_t)(0xFFUL << MXC_F_SPIXR_XMEM_CTRL_RD_CMD_POS)) /**< XMEM_CTRL_RD_CMD Mask */ 498 499 #define MXC_F_SPIXR_XMEM_CTRL_WR_CMD_POS 8 /**< XMEM_CTRL_WR_CMD Position */ 500 #define MXC_F_SPIXR_XMEM_CTRL_WR_CMD ((uint32_t)(0xFFUL << MXC_F_SPIXR_XMEM_CTRL_WR_CMD_POS)) /**< XMEM_CTRL_WR_CMD Mask */ 501 502 #define MXC_F_SPIXR_XMEM_CTRL_DUMMY_CLK_POS 16 /**< XMEM_CTRL_DUMMY_CLK Position */ 503 #define MXC_F_SPIXR_XMEM_CTRL_DUMMY_CLK ((uint32_t)(0xFFUL << MXC_F_SPIXR_XMEM_CTRL_DUMMY_CLK_POS)) /**< XMEM_CTRL_DUMMY_CLK Mask */ 504 505 #define MXC_F_SPIXR_XMEM_CTRL_XMEM_EN_POS 31 /**< XMEM_CTRL_XMEM_EN Position */ 506 #define MXC_F_SPIXR_XMEM_CTRL_XMEM_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_XMEM_CTRL_XMEM_EN_POS)) /**< XMEM_CTRL_XMEM_EN Mask */ 507 508 /**@} end of group SPIXR_XMEM_CTRL_Register */ 509 510 #ifdef __cplusplus 511 } 512 #endif 513 514 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SPIXR_REGS_H_ 515
