1 /** 2 * @file spixfm_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPIXFM Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SPIXFM_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SPIXFM_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup spixfm 66 * @defgroup spixfm_registers SPIXFM_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the SPIXFM Peripheral Module. 68 * @details SPIXF Master 69 */ 70 71 /** 72 * @ingroup spixfm_registers 73 * Structure type to access the SPIXFM Registers. 74 */ 75 typedef struct { 76 __IO uint32_t cfg; /**< <tt>\b 0x00:</tt> SPIXFM CFG Register */ 77 __IO uint32_t fetch_ctrl; /**< <tt>\b 0x04:</tt> SPIXFM FETCH_CTRL Register */ 78 __IO uint32_t mode_ctrl; /**< <tt>\b 0x08:</tt> SPIXFM MODE_CTRL Register */ 79 __IO uint32_t mode_data; /**< <tt>\b 0x0C:</tt> SPIXFM MODE_DATA Register */ 80 __IO uint32_t fb_ctrl; /**< <tt>\b 0x10:</tt> SPIXFM FB_CTRL Register */ 81 __R uint32_t rsv_0x14_0x1b[2]; 82 __IO uint32_t io_ctrl; /**< <tt>\b 0x1C:</tt> SPIXFM IO_CTRL Register */ 83 __IO uint32_t sec_ctrl; /**< <tt>\b 0x20:</tt> SPIXFM SEC_CTRL Register */ 84 __IO uint32_t bus_idle; /**< <tt>\b 0x24:</tt> SPIXFM BUS_IDLE Register */ 85 __IO uint32_t authoffset; /**< <tt>\b 0x28:</tt> SPIXFM AUTHOFFSET Register */ 86 } mxc_spixfm_regs_t; 87 88 /* Register offsets for module SPIXFM */ 89 /** 90 * @ingroup spixfm_registers 91 * @defgroup SPIXFM_Register_Offsets Register Offsets 92 * @brief SPIXFM Peripheral Register Offsets from the SPIXFM Base Peripheral Address. 93 * @{ 94 */ 95 #define MXC_R_SPIXFM_CFG ((uint32_t)0x00000000UL) /**< Offset from SPIXFM Base Address: <tt> 0x0000</tt> */ 96 #define MXC_R_SPIXFM_FETCH_CTRL ((uint32_t)0x00000004UL) /**< Offset from SPIXFM Base Address: <tt> 0x0004</tt> */ 97 #define MXC_R_SPIXFM_MODE_CTRL ((uint32_t)0x00000008UL) /**< Offset from SPIXFM Base Address: <tt> 0x0008</tt> */ 98 #define MXC_R_SPIXFM_MODE_DATA ((uint32_t)0x0000000CUL) /**< Offset from SPIXFM Base Address: <tt> 0x000C</tt> */ 99 #define MXC_R_SPIXFM_FB_CTRL ((uint32_t)0x00000010UL) /**< Offset from SPIXFM Base Address: <tt> 0x0010</tt> */ 100 #define MXC_R_SPIXFM_IO_CTRL ((uint32_t)0x0000001CUL) /**< Offset from SPIXFM Base Address: <tt> 0x001C</tt> */ 101 #define MXC_R_SPIXFM_SEC_CTRL ((uint32_t)0x00000020UL) /**< Offset from SPIXFM Base Address: <tt> 0x0020</tt> */ 102 #define MXC_R_SPIXFM_BUS_IDLE ((uint32_t)0x00000024UL) /**< Offset from SPIXFM Base Address: <tt> 0x0024</tt> */ 103 #define MXC_R_SPIXFM_AUTHOFFSET ((uint32_t)0x00000028UL) /**< Offset from SPIXFM Base Address: <tt> 0x0028</tt> */ 104 /**@} end of group spixfm_registers */ 105 106 /** 107 * @ingroup spixfm_registers 108 * @defgroup SPIXFM_CFG SPIXFM_CFG 109 * @brief SPIX Configuration Register. 110 * @{ 111 */ 112 #define MXC_F_SPIXFM_CFG_MODE_POS 0 /**< CFG_MODE Position */ 113 #define MXC_F_SPIXFM_CFG_MODE ((uint32_t)(0x3UL << MXC_F_SPIXFM_CFG_MODE_POS)) /**< CFG_MODE Mask */ 114 #define MXC_V_SPIXFM_CFG_MODE_SCLK_HI_SAMPLE_RISING ((uint32_t)0x0UL) /**< CFG_MODE_SCLK_HI_SAMPLE_RISING Value */ 115 #define MXC_S_SPIXFM_CFG_MODE_SCLK_HI_SAMPLE_RISING (MXC_V_SPIXFM_CFG_MODE_SCLK_HI_SAMPLE_RISING << MXC_F_SPIXFM_CFG_MODE_POS) /**< CFG_MODE_SCLK_HI_SAMPLE_RISING Setting */ 116 #define MXC_V_SPIXFM_CFG_MODE_SCLK_LO_SAMPLE_FAILLING ((uint32_t)0x3UL) /**< CFG_MODE_SCLK_LO_SAMPLE_FAILLING Value */ 117 #define MXC_S_SPIXFM_CFG_MODE_SCLK_LO_SAMPLE_FAILLING (MXC_V_SPIXFM_CFG_MODE_SCLK_LO_SAMPLE_FAILLING << MXC_F_SPIXFM_CFG_MODE_POS) /**< CFG_MODE_SCLK_LO_SAMPLE_FAILLING Setting */ 118 119 #define MXC_F_SPIXFM_CFG_SSPOL_POS 2 /**< CFG_SSPOL Position */ 120 #define MXC_F_SPIXFM_CFG_SSPOL ((uint32_t)(0x1UL << MXC_F_SPIXFM_CFG_SSPOL_POS)) /**< CFG_SSPOL Mask */ 121 122 #define MXC_F_SPIXFM_CFG_SSEL_POS 4 /**< CFG_SSEL Position */ 123 #define MXC_F_SPIXFM_CFG_SSEL ((uint32_t)(0x7UL << MXC_F_SPIXFM_CFG_SSEL_POS)) /**< CFG_SSEL Mask */ 124 125 #define MXC_F_SPIXFM_CFG_LO_CLK_POS 8 /**< CFG_LO_CLK Position */ 126 #define MXC_F_SPIXFM_CFG_LO_CLK ((uint32_t)(0xFUL << MXC_F_SPIXFM_CFG_LO_CLK_POS)) /**< CFG_LO_CLK Mask */ 127 128 #define MXC_F_SPIXFM_CFG_HI_CLK_POS 12 /**< CFG_HI_CLK Position */ 129 #define MXC_F_SPIXFM_CFG_HI_CLK ((uint32_t)(0xFUL << MXC_F_SPIXFM_CFG_HI_CLK_POS)) /**< CFG_HI_CLK Mask */ 130 131 #define MXC_F_SPIXFM_CFG_SSACT_POS 16 /**< CFG_SSACT Position */ 132 #define MXC_F_SPIXFM_CFG_SSACT ((uint32_t)(0x3UL << MXC_F_SPIXFM_CFG_SSACT_POS)) /**< CFG_SSACT Mask */ 133 #define MXC_V_SPIXFM_CFG_SSACT_OFF ((uint32_t)0x0UL) /**< CFG_SSACT_OFF Value */ 134 #define MXC_S_SPIXFM_CFG_SSACT_OFF (MXC_V_SPIXFM_CFG_SSACT_OFF << MXC_F_SPIXFM_CFG_SSACT_POS) /**< CFG_SSACT_OFF Setting */ 135 #define MXC_V_SPIXFM_CFG_SSACT_FOR_2_MOD_CLK ((uint32_t)0x1UL) /**< CFG_SSACT_FOR_2_MOD_CLK Value */ 136 #define MXC_S_SPIXFM_CFG_SSACT_FOR_2_MOD_CLK (MXC_V_SPIXFM_CFG_SSACT_FOR_2_MOD_CLK << MXC_F_SPIXFM_CFG_SSACT_POS) /**< CFG_SSACT_FOR_2_MOD_CLK Setting */ 137 #define MXC_V_SPIXFM_CFG_SSACT_FOR_4_MOD_CLK ((uint32_t)0x2UL) /**< CFG_SSACT_FOR_4_MOD_CLK Value */ 138 #define MXC_S_SPIXFM_CFG_SSACT_FOR_4_MOD_CLK (MXC_V_SPIXFM_CFG_SSACT_FOR_4_MOD_CLK << MXC_F_SPIXFM_CFG_SSACT_POS) /**< CFG_SSACT_FOR_4_MOD_CLK Setting */ 139 #define MXC_V_SPIXFM_CFG_SSACT_FOR_8_MOD_CLK ((uint32_t)0x3UL) /**< CFG_SSACT_FOR_8_MOD_CLK Value */ 140 #define MXC_S_SPIXFM_CFG_SSACT_FOR_8_MOD_CLK (MXC_V_SPIXFM_CFG_SSACT_FOR_8_MOD_CLK << MXC_F_SPIXFM_CFG_SSACT_POS) /**< CFG_SSACT_FOR_8_MOD_CLK Setting */ 141 142 #define MXC_F_SPIXFM_CFG_SSIACT_POS 18 /**< CFG_SSIACT Position */ 143 #define MXC_F_SPIXFM_CFG_SSIACT ((uint32_t)(0x3UL << MXC_F_SPIXFM_CFG_SSIACT_POS)) /**< CFG_SSIACT Mask */ 144 #define MXC_V_SPIXFM_CFG_SSIACT_FOR_1_MOD_CLK ((uint32_t)0x0UL) /**< CFG_SSIACT_FOR_1_MOD_CLK Value */ 145 #define MXC_S_SPIXFM_CFG_SSIACT_FOR_1_MOD_CLK (MXC_V_SPIXFM_CFG_SSIACT_FOR_1_MOD_CLK << MXC_F_SPIXFM_CFG_SSIACT_POS) /**< CFG_SSIACT_FOR_1_MOD_CLK Setting */ 146 #define MXC_V_SPIXFM_CFG_SSIACT_FOR_3_MOD_CLK ((uint32_t)0x1UL) /**< CFG_SSIACT_FOR_3_MOD_CLK Value */ 147 #define MXC_S_SPIXFM_CFG_SSIACT_FOR_3_MOD_CLK (MXC_V_SPIXFM_CFG_SSIACT_FOR_3_MOD_CLK << MXC_F_SPIXFM_CFG_SSIACT_POS) /**< CFG_SSIACT_FOR_3_MOD_CLK Setting */ 148 #define MXC_V_SPIXFM_CFG_SSIACT_FOR_5_MOD_CLK ((uint32_t)0x2UL) /**< CFG_SSIACT_FOR_5_MOD_CLK Value */ 149 #define MXC_S_SPIXFM_CFG_SSIACT_FOR_5_MOD_CLK (MXC_V_SPIXFM_CFG_SSIACT_FOR_5_MOD_CLK << MXC_F_SPIXFM_CFG_SSIACT_POS) /**< CFG_SSIACT_FOR_5_MOD_CLK Setting */ 150 #define MXC_V_SPIXFM_CFG_SSIACT_FOR_9_MOD_CLK ((uint32_t)0x3UL) /**< CFG_SSIACT_FOR_9_MOD_CLK Value */ 151 #define MXC_S_SPIXFM_CFG_SSIACT_FOR_9_MOD_CLK (MXC_V_SPIXFM_CFG_SSIACT_FOR_9_MOD_CLK << MXC_F_SPIXFM_CFG_SSIACT_POS) /**< CFG_SSIACT_FOR_9_MOD_CLK Setting */ 152 153 /**@} end of group SPIXFM_CFG_Register */ 154 155 /** 156 * @ingroup spixfm_registers 157 * @defgroup SPIXFM_FETCH_CTRL SPIXFM_FETCH_CTRL 158 * @brief SPIX Fetch Control Register. 159 * @{ 160 */ 161 #define MXC_F_SPIXFM_FETCH_CTRL_CMDVAL_POS 0 /**< FETCH_CTRL_CMDVAL Position */ 162 #define MXC_F_SPIXFM_FETCH_CTRL_CMDVAL ((uint32_t)(0xFFUL << MXC_F_SPIXFM_FETCH_CTRL_CMDVAL_POS)) /**< FETCH_CTRL_CMDVAL Mask */ 163 164 #define MXC_F_SPIXFM_FETCH_CTRL_CMD_WIDTH_POS 8 /**< FETCH_CTRL_CMD_WIDTH Position */ 165 #define MXC_F_SPIXFM_FETCH_CTRL_CMD_WIDTH ((uint32_t)(0x3UL << MXC_F_SPIXFM_FETCH_CTRL_CMD_WIDTH_POS)) /**< FETCH_CTRL_CMD_WIDTH Mask */ 166 #define MXC_V_SPIXFM_FETCH_CTRL_CMD_WIDTH_SINGLE ((uint32_t)0x0UL) /**< FETCH_CTRL_CMD_WIDTH_SINGLE Value */ 167 #define MXC_S_SPIXFM_FETCH_CTRL_CMD_WIDTH_SINGLE (MXC_V_SPIXFM_FETCH_CTRL_CMD_WIDTH_SINGLE << MXC_F_SPIXFM_FETCH_CTRL_CMD_WIDTH_POS) /**< FETCH_CTRL_CMD_WIDTH_SINGLE Setting */ 168 #define MXC_V_SPIXFM_FETCH_CTRL_CMD_WIDTH_DUAL_IO ((uint32_t)0x1UL) /**< FETCH_CTRL_CMD_WIDTH_DUAL_IO Value */ 169 #define MXC_S_SPIXFM_FETCH_CTRL_CMD_WIDTH_DUAL_IO (MXC_V_SPIXFM_FETCH_CTRL_CMD_WIDTH_DUAL_IO << MXC_F_SPIXFM_FETCH_CTRL_CMD_WIDTH_POS) /**< FETCH_CTRL_CMD_WIDTH_DUAL_IO Setting */ 170 #define MXC_V_SPIXFM_FETCH_CTRL_CMD_WIDTH_QUAD_IO ((uint32_t)0x2UL) /**< FETCH_CTRL_CMD_WIDTH_QUAD_IO Value */ 171 #define MXC_S_SPIXFM_FETCH_CTRL_CMD_WIDTH_QUAD_IO (MXC_V_SPIXFM_FETCH_CTRL_CMD_WIDTH_QUAD_IO << MXC_F_SPIXFM_FETCH_CTRL_CMD_WIDTH_POS) /**< FETCH_CTRL_CMD_WIDTH_QUAD_IO Setting */ 172 #define MXC_V_SPIXFM_FETCH_CTRL_CMD_WIDTH_INVALID ((uint32_t)0x3UL) /**< FETCH_CTRL_CMD_WIDTH_INVALID Value */ 173 #define MXC_S_SPIXFM_FETCH_CTRL_CMD_WIDTH_INVALID (MXC_V_SPIXFM_FETCH_CTRL_CMD_WIDTH_INVALID << MXC_F_SPIXFM_FETCH_CTRL_CMD_WIDTH_POS) /**< FETCH_CTRL_CMD_WIDTH_INVALID Setting */ 174 175 #define MXC_F_SPIXFM_FETCH_CTRL_ADDR_WIDTH_POS 10 /**< FETCH_CTRL_ADDR_WIDTH Position */ 176 #define MXC_F_SPIXFM_FETCH_CTRL_ADDR_WIDTH ((uint32_t)(0x3UL << MXC_F_SPIXFM_FETCH_CTRL_ADDR_WIDTH_POS)) /**< FETCH_CTRL_ADDR_WIDTH Mask */ 177 #define MXC_V_SPIXFM_FETCH_CTRL_ADDR_WIDTH_SINGLE ((uint32_t)0x0UL) /**< FETCH_CTRL_ADDR_WIDTH_SINGLE Value */ 178 #define MXC_S_SPIXFM_FETCH_CTRL_ADDR_WIDTH_SINGLE (MXC_V_SPIXFM_FETCH_CTRL_ADDR_WIDTH_SINGLE << MXC_F_SPIXFM_FETCH_CTRL_ADDR_WIDTH_POS) /**< FETCH_CTRL_ADDR_WIDTH_SINGLE Setting */ 179 #define MXC_V_SPIXFM_FETCH_CTRL_ADDR_WIDTH_DUAL_IO ((uint32_t)0x1UL) /**< FETCH_CTRL_ADDR_WIDTH_DUAL_IO Value */ 180 #define MXC_S_SPIXFM_FETCH_CTRL_ADDR_WIDTH_DUAL_IO (MXC_V_SPIXFM_FETCH_CTRL_ADDR_WIDTH_DUAL_IO << MXC_F_SPIXFM_FETCH_CTRL_ADDR_WIDTH_POS) /**< FETCH_CTRL_ADDR_WIDTH_DUAL_IO Setting */ 181 #define MXC_V_SPIXFM_FETCH_CTRL_ADDR_WIDTH_QUAD_IO ((uint32_t)0x2UL) /**< FETCH_CTRL_ADDR_WIDTH_QUAD_IO Value */ 182 #define MXC_S_SPIXFM_FETCH_CTRL_ADDR_WIDTH_QUAD_IO (MXC_V_SPIXFM_FETCH_CTRL_ADDR_WIDTH_QUAD_IO << MXC_F_SPIXFM_FETCH_CTRL_ADDR_WIDTH_POS) /**< FETCH_CTRL_ADDR_WIDTH_QUAD_IO Setting */ 183 #define MXC_V_SPIXFM_FETCH_CTRL_ADDR_WIDTH_INVALID ((uint32_t)0x3UL) /**< FETCH_CTRL_ADDR_WIDTH_INVALID Value */ 184 #define MXC_S_SPIXFM_FETCH_CTRL_ADDR_WIDTH_INVALID (MXC_V_SPIXFM_FETCH_CTRL_ADDR_WIDTH_INVALID << MXC_F_SPIXFM_FETCH_CTRL_ADDR_WIDTH_POS) /**< FETCH_CTRL_ADDR_WIDTH_INVALID Setting */ 185 186 #define MXC_F_SPIXFM_FETCH_CTRL_DATA_WIDTH_POS 12 /**< FETCH_CTRL_DATA_WIDTH Position */ 187 #define MXC_F_SPIXFM_FETCH_CTRL_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPIXFM_FETCH_CTRL_DATA_WIDTH_POS)) /**< FETCH_CTRL_DATA_WIDTH Mask */ 188 #define MXC_V_SPIXFM_FETCH_CTRL_DATA_WIDTH_SINGLE ((uint32_t)0x0UL) /**< FETCH_CTRL_DATA_WIDTH_SINGLE Value */ 189 #define MXC_S_SPIXFM_FETCH_CTRL_DATA_WIDTH_SINGLE (MXC_V_SPIXFM_FETCH_CTRL_DATA_WIDTH_SINGLE << MXC_F_SPIXFM_FETCH_CTRL_DATA_WIDTH_POS) /**< FETCH_CTRL_DATA_WIDTH_SINGLE Setting */ 190 #define MXC_V_SPIXFM_FETCH_CTRL_DATA_WIDTH_DUAL_IO ((uint32_t)0x1UL) /**< FETCH_CTRL_DATA_WIDTH_DUAL_IO Value */ 191 #define MXC_S_SPIXFM_FETCH_CTRL_DATA_WIDTH_DUAL_IO (MXC_V_SPIXFM_FETCH_CTRL_DATA_WIDTH_DUAL_IO << MXC_F_SPIXFM_FETCH_CTRL_DATA_WIDTH_POS) /**< FETCH_CTRL_DATA_WIDTH_DUAL_IO Setting */ 192 #define MXC_V_SPIXFM_FETCH_CTRL_DATA_WIDTH_QUAD_IO ((uint32_t)0x2UL) /**< FETCH_CTRL_DATA_WIDTH_QUAD_IO Value */ 193 #define MXC_S_SPIXFM_FETCH_CTRL_DATA_WIDTH_QUAD_IO (MXC_V_SPIXFM_FETCH_CTRL_DATA_WIDTH_QUAD_IO << MXC_F_SPIXFM_FETCH_CTRL_DATA_WIDTH_POS) /**< FETCH_CTRL_DATA_WIDTH_QUAD_IO Setting */ 194 #define MXC_V_SPIXFM_FETCH_CTRL_DATA_WIDTH_INVALID ((uint32_t)0x3UL) /**< FETCH_CTRL_DATA_WIDTH_INVALID Value */ 195 #define MXC_S_SPIXFM_FETCH_CTRL_DATA_WIDTH_INVALID (MXC_V_SPIXFM_FETCH_CTRL_DATA_WIDTH_INVALID << MXC_F_SPIXFM_FETCH_CTRL_DATA_WIDTH_POS) /**< FETCH_CTRL_DATA_WIDTH_INVALID Setting */ 196 197 #define MXC_F_SPIXFM_FETCH_CTRL_FOUR_BYTE_ADDR_POS 16 /**< FETCH_CTRL_FOUR_BYTE_ADDR Position */ 198 #define MXC_F_SPIXFM_FETCH_CTRL_FOUR_BYTE_ADDR ((uint32_t)(0x1UL << MXC_F_SPIXFM_FETCH_CTRL_FOUR_BYTE_ADDR_POS)) /**< FETCH_CTRL_FOUR_BYTE_ADDR Mask */ 199 200 /**@} end of group SPIXFM_FETCH_CTRL_Register */ 201 202 /** 203 * @ingroup spixfm_registers 204 * @defgroup SPIXFM_MODE_CTRL SPIXFM_MODE_CTRL 205 * @brief SPIX Mode Control Register. 206 * @{ 207 */ 208 #define MXC_F_SPIXFM_MODE_CTRL_MDCLK_POS 0 /**< MODE_CTRL_MDCLK Position */ 209 #define MXC_F_SPIXFM_MODE_CTRL_MDCLK ((uint32_t)(0xFUL << MXC_F_SPIXFM_MODE_CTRL_MDCLK_POS)) /**< MODE_CTRL_MDCLK Mask */ 210 211 #define MXC_F_SPIXFM_MODE_CTRL_NO_CMD_POS 8 /**< MODE_CTRL_NO_CMD Position */ 212 #define MXC_F_SPIXFM_MODE_CTRL_NO_CMD ((uint32_t)(0x1UL << MXC_F_SPIXFM_MODE_CTRL_NO_CMD_POS)) /**< MODE_CTRL_NO_CMD Mask */ 213 214 #define MXC_F_SPIXFM_MODE_CTRL_MODE_SEND_POS 9 /**< MODE_CTRL_MODE_SEND Position */ 215 #define MXC_F_SPIXFM_MODE_CTRL_MODE_SEND ((uint32_t)(0x1UL << MXC_F_SPIXFM_MODE_CTRL_MODE_SEND_POS)) /**< MODE_CTRL_MODE_SEND Mask */ 216 217 /**@} end of group SPIXFM_MODE_CTRL_Register */ 218 219 /** 220 * @ingroup spixfm_registers 221 * @defgroup SPIXFM_MODE_DATA SPIXFM_MODE_DATA 222 * @brief SPIX Mode Data Register. 223 * @{ 224 */ 225 #define MXC_F_SPIXFM_MODE_DATA_DATA_POS 0 /**< MODE_DATA_DATA Position */ 226 #define MXC_F_SPIXFM_MODE_DATA_DATA ((uint32_t)(0xFFFFUL << MXC_F_SPIXFM_MODE_DATA_DATA_POS)) /**< MODE_DATA_DATA Mask */ 227 228 #define MXC_F_SPIXFM_MODE_DATA_OUT_EN_POS 16 /**< MODE_DATA_OUT_EN Position */ 229 #define MXC_F_SPIXFM_MODE_DATA_OUT_EN ((uint32_t)(0xFFFFUL << MXC_F_SPIXFM_MODE_DATA_OUT_EN_POS)) /**< MODE_DATA_OUT_EN Mask */ 230 231 /**@} end of group SPIXFM_MODE_DATA_Register */ 232 233 /** 234 * @ingroup spixfm_registers 235 * @defgroup SPIXFM_FB_CTRL SPIXFM_FB_CTRL 236 * @brief SPIX Feedback Control Register. 237 * @{ 238 */ 239 #define MXC_F_SPIXFM_FB_CTRL_FB_EN_POS 0 /**< FB_CTRL_FB_EN Position */ 240 #define MXC_F_SPIXFM_FB_CTRL_FB_EN ((uint32_t)(0x1UL << MXC_F_SPIXFM_FB_CTRL_FB_EN_POS)) /**< FB_CTRL_FB_EN Mask */ 241 242 #define MXC_F_SPIXFM_FB_CTRL_INVERT_EN_POS 1 /**< FB_CTRL_INVERT_EN Position */ 243 #define MXC_F_SPIXFM_FB_CTRL_INVERT_EN ((uint32_t)(0x1UL << MXC_F_SPIXFM_FB_CTRL_INVERT_EN_POS)) /**< FB_CTRL_INVERT_EN Mask */ 244 245 /**@} end of group SPIXFM_FB_CTRL_Register */ 246 247 /** 248 * @ingroup spixfm_registers 249 * @defgroup SPIXFM_IO_CTRL SPIXFM_IO_CTRL 250 * @brief SPIX IO Control Register. 251 * @{ 252 */ 253 #define MXC_F_SPIXFM_IO_CTRL_SCLK_DS_POS 0 /**< IO_CTRL_SCLK_DS Position */ 254 #define MXC_F_SPIXFM_IO_CTRL_SCLK_DS ((uint32_t)(0x1UL << MXC_F_SPIXFM_IO_CTRL_SCLK_DS_POS)) /**< IO_CTRL_SCLK_DS Mask */ 255 256 #define MXC_F_SPIXFM_IO_CTRL_SS_DS_POS 1 /**< IO_CTRL_SS_DS Position */ 257 #define MXC_F_SPIXFM_IO_CTRL_SS_DS ((uint32_t)(0x1UL << MXC_F_SPIXFM_IO_CTRL_SS_DS_POS)) /**< IO_CTRL_SS_DS Mask */ 258 259 #define MXC_F_SPIXFM_IO_CTRL_SDIO_DS_POS 2 /**< IO_CTRL_SDIO_DS Position */ 260 #define MXC_F_SPIXFM_IO_CTRL_SDIO_DS ((uint32_t)(0x1UL << MXC_F_SPIXFM_IO_CTRL_SDIO_DS_POS)) /**< IO_CTRL_SDIO_DS Mask */ 261 262 #define MXC_F_SPIXFM_IO_CTRL_PU_PD_CTRL_POS 3 /**< IO_CTRL_PU_PD_CTRL Position */ 263 #define MXC_F_SPIXFM_IO_CTRL_PU_PD_CTRL ((uint32_t)(0x3UL << MXC_F_SPIXFM_IO_CTRL_PU_PD_CTRL_POS)) /**< IO_CTRL_PU_PD_CTRL Mask */ 264 #define MXC_V_SPIXFM_IO_CTRL_PU_PD_CTRL_TRI_STATE ((uint32_t)0x0UL) /**< IO_CTRL_PU_PD_CTRL_TRI_STATE Value */ 265 #define MXC_S_SPIXFM_IO_CTRL_PU_PD_CTRL_TRI_STATE (MXC_V_SPIXFM_IO_CTRL_PU_PD_CTRL_TRI_STATE << MXC_F_SPIXFM_IO_CTRL_PU_PD_CTRL_POS) /**< IO_CTRL_PU_PD_CTRL_TRI_STATE Setting */ 266 #define MXC_V_SPIXFM_IO_CTRL_PU_PD_CTRL_PULL_UP ((uint32_t)0x1UL) /**< IO_CTRL_PU_PD_CTRL_PULL_UP Value */ 267 #define MXC_S_SPIXFM_IO_CTRL_PU_PD_CTRL_PULL_UP (MXC_V_SPIXFM_IO_CTRL_PU_PD_CTRL_PULL_UP << MXC_F_SPIXFM_IO_CTRL_PU_PD_CTRL_POS) /**< IO_CTRL_PU_PD_CTRL_PULL_UP Setting */ 268 #define MXC_V_SPIXFM_IO_CTRL_PU_PD_CTRL_PULL_DOWN ((uint32_t)0x2UL) /**< IO_CTRL_PU_PD_CTRL_PULL_DOWN Value */ 269 #define MXC_S_SPIXFM_IO_CTRL_PU_PD_CTRL_PULL_DOWN (MXC_V_SPIXFM_IO_CTRL_PU_PD_CTRL_PULL_DOWN << MXC_F_SPIXFM_IO_CTRL_PU_PD_CTRL_POS) /**< IO_CTRL_PU_PD_CTRL_PULL_DOWN Setting */ 270 271 /**@} end of group SPIXFM_IO_CTRL_Register */ 272 273 /** 274 * @ingroup spixfm_registers 275 * @defgroup SPIXFM_SEC_CTRL SPIXFM_SEC_CTRL 276 * @brief SPIX Memory Security Control Register. 277 * @{ 278 */ 279 #define MXC_F_SPIXFM_SEC_CTRL_DEC_EN_POS 0 /**< SEC_CTRL_DEC_EN Position */ 280 #define MXC_F_SPIXFM_SEC_CTRL_DEC_EN ((uint32_t)(0x1UL << MXC_F_SPIXFM_SEC_CTRL_DEC_EN_POS)) /**< SEC_CTRL_DEC_EN Mask */ 281 282 #define MXC_F_SPIXFM_SEC_CTRL_AUTH_DISABLE_POS 1 /**< SEC_CTRL_AUTH_DISABLE Position */ 283 #define MXC_F_SPIXFM_SEC_CTRL_AUTH_DISABLE ((uint32_t)(0x1UL << MXC_F_SPIXFM_SEC_CTRL_AUTH_DISABLE_POS)) /**< SEC_CTRL_AUTH_DISABLE Mask */ 284 285 /**@} end of group SPIXFM_SEC_CTRL_Register */ 286 287 /** 288 * @ingroup spixfm_registers 289 * @defgroup SPIXFM_BUS_IDLE SPIXFM_BUS_IDLE 290 * @brief Bus Idle 291 * @{ 292 */ 293 #define MXC_F_SPIXFM_BUS_IDLE_BUSIDLE_POS 0 /**< BUS_IDLE_BUSIDLE Position */ 294 #define MXC_F_SPIXFM_BUS_IDLE_BUSIDLE ((uint32_t)(0xFFFFUL << MXC_F_SPIXFM_BUS_IDLE_BUSIDLE_POS)) /**< BUS_IDLE_BUSIDLE Mask */ 295 296 /**@} end of group SPIXFM_BUS_IDLE_Register */ 297 298 #ifdef __cplusplus 299 } 300 #endif 301 302 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SPIXFM_REGS_H_ 303
