1 /** 2 * @file spixfc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPIXFC Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SPIXFC_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SPIXFC_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup spixfc 66 * @defgroup spixfc_registers SPIXFC_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the SPIXFC Peripheral Module. 68 * @details SPI XiP Flash Configuration Controller 69 */ 70 71 /** 72 * @ingroup spixfc_registers 73 * Structure type to access the SPIXFC Registers. 74 */ 75 typedef struct { 76 __IO uint32_t cfg; /**< <tt>\b 0x00:</tt> SPIXFC CFG Register */ 77 __IO uint32_t ss_pol; /**< <tt>\b 0x04:</tt> SPIXFC SS_POL Register */ 78 __IO uint32_t gen_ctrl; /**< <tt>\b 0x08:</tt> SPIXFC GEN_CTRL Register */ 79 __IO uint32_t fifo_ctrl; /**< <tt>\b 0x0C:</tt> SPIXFC FIFO_CTRL Register */ 80 __IO uint32_t sp_ctrl; /**< <tt>\b 0x10:</tt> SPIXFC SP_CTRL Register */ 81 __IO uint32_t int_fl; /**< <tt>\b 0x14:</tt> SPIXFC INT_FL Register */ 82 __IO uint32_t int_en; /**< <tt>\b 0x18:</tt> SPIXFC INT_EN Register */ 83 } mxc_spixfc_regs_t; 84 85 /* Register offsets for module SPIXFC */ 86 /** 87 * @ingroup spixfc_registers 88 * @defgroup SPIXFC_Register_Offsets Register Offsets 89 * @brief SPIXFC Peripheral Register Offsets from the SPIXFC Base Peripheral Address. 90 * @{ 91 */ 92 #define MXC_R_SPIXFC_CFG ((uint32_t)0x00000000UL) /**< Offset from SPIXFC Base Address: <tt> 0x0000</tt> */ 93 #define MXC_R_SPIXFC_SS_POL ((uint32_t)0x00000004UL) /**< Offset from SPIXFC Base Address: <tt> 0x0004</tt> */ 94 #define MXC_R_SPIXFC_GEN_CTRL ((uint32_t)0x00000008UL) /**< Offset from SPIXFC Base Address: <tt> 0x0008</tt> */ 95 #define MXC_R_SPIXFC_FIFO_CTRL ((uint32_t)0x0000000CUL) /**< Offset from SPIXFC Base Address: <tt> 0x000C</tt> */ 96 #define MXC_R_SPIXFC_SP_CTRL ((uint32_t)0x00000010UL) /**< Offset from SPIXFC Base Address: <tt> 0x0010</tt> */ 97 #define MXC_R_SPIXFC_INT_FL ((uint32_t)0x00000014UL) /**< Offset from SPIXFC Base Address: <tt> 0x0014</tt> */ 98 #define MXC_R_SPIXFC_INT_EN ((uint32_t)0x00000018UL) /**< Offset from SPIXFC Base Address: <tt> 0x0018</tt> */ 99 /**@} end of group spixfc_registers */ 100 101 /** 102 * @ingroup spixfc_registers 103 * @defgroup SPIXFC_CFG SPIXFC_CFG 104 * @brief Configuration Register. 105 * @{ 106 */ 107 #define MXC_F_SPIXFC_CFG_SSEL_POS 0 /**< CFG_SSEL Position */ 108 #define MXC_F_SPIXFC_CFG_SSEL ((uint32_t)(0x7UL << MXC_F_SPIXFC_CFG_SSEL_POS)) /**< CFG_SSEL Mask */ 109 #define MXC_V_SPIXFC_CFG_SSEL_SLAVE_0 ((uint32_t)0x0UL) /**< CFG_SSEL_SLAVE_0 Value */ 110 #define MXC_S_SPIXFC_CFG_SSEL_SLAVE_0 (MXC_V_SPIXFC_CFG_SSEL_SLAVE_0 << MXC_F_SPIXFC_CFG_SSEL_POS) /**< CFG_SSEL_SLAVE_0 Setting */ 111 #define MXC_V_SPIXFC_CFG_SSEL_SLAVE_1 ((uint32_t)0x1UL) /**< CFG_SSEL_SLAVE_1 Value */ 112 #define MXC_S_SPIXFC_CFG_SSEL_SLAVE_1 (MXC_V_SPIXFC_CFG_SSEL_SLAVE_1 << MXC_F_SPIXFC_CFG_SSEL_POS) /**< CFG_SSEL_SLAVE_1 Setting */ 113 114 #define MXC_F_SPIXFC_CFG_MODE_POS 4 /**< CFG_MODE Position */ 115 #define MXC_F_SPIXFC_CFG_MODE ((uint32_t)(0x3UL << MXC_F_SPIXFC_CFG_MODE_POS)) /**< CFG_MODE Mask */ 116 #define MXC_V_SPIXFC_CFG_MODE_SPIX_MODE_0 ((uint32_t)0x0UL) /**< CFG_MODE_SPIX_MODE_0 Value */ 117 #define MXC_S_SPIXFC_CFG_MODE_SPIX_MODE_0 (MXC_V_SPIXFC_CFG_MODE_SPIX_MODE_0 << MXC_F_SPIXFC_CFG_MODE_POS) /**< CFG_MODE_SPIX_MODE_0 Setting */ 118 #define MXC_V_SPIXFC_CFG_MODE_SPIX_MODE_3 ((uint32_t)0x3UL) /**< CFG_MODE_SPIX_MODE_3 Value */ 119 #define MXC_S_SPIXFC_CFG_MODE_SPIX_MODE_3 (MXC_V_SPIXFC_CFG_MODE_SPIX_MODE_3 << MXC_F_SPIXFC_CFG_MODE_POS) /**< CFG_MODE_SPIX_MODE_3 Setting */ 120 121 #define MXC_F_SPIXFC_CFG_PAGE_SIZE_POS 6 /**< CFG_PAGE_SIZE Position */ 122 #define MXC_F_SPIXFC_CFG_PAGE_SIZE ((uint32_t)(0x3UL << MXC_F_SPIXFC_CFG_PAGE_SIZE_POS)) /**< CFG_PAGE_SIZE Mask */ 123 #define MXC_V_SPIXFC_CFG_PAGE_SIZE_4_BYTES ((uint32_t)0x0UL) /**< CFG_PAGE_SIZE_4_BYTES Value */ 124 #define MXC_S_SPIXFC_CFG_PAGE_SIZE_4_BYTES (MXC_V_SPIXFC_CFG_PAGE_SIZE_4_BYTES << MXC_F_SPIXFC_CFG_PAGE_SIZE_POS) /**< CFG_PAGE_SIZE_4_BYTES Setting */ 125 #define MXC_V_SPIXFC_CFG_PAGE_SIZE_8_BYTES ((uint32_t)0x1UL) /**< CFG_PAGE_SIZE_8_BYTES Value */ 126 #define MXC_S_SPIXFC_CFG_PAGE_SIZE_8_BYTES (MXC_V_SPIXFC_CFG_PAGE_SIZE_8_BYTES << MXC_F_SPIXFC_CFG_PAGE_SIZE_POS) /**< CFG_PAGE_SIZE_8_BYTES Setting */ 127 #define MXC_V_SPIXFC_CFG_PAGE_SIZE_16_BYTES ((uint32_t)0x2UL) /**< CFG_PAGE_SIZE_16_BYTES Value */ 128 #define MXC_S_SPIXFC_CFG_PAGE_SIZE_16_BYTES (MXC_V_SPIXFC_CFG_PAGE_SIZE_16_BYTES << MXC_F_SPIXFC_CFG_PAGE_SIZE_POS) /**< CFG_PAGE_SIZE_16_BYTES Setting */ 129 #define MXC_V_SPIXFC_CFG_PAGE_SIZE_32_BYTES ((uint32_t)0x3UL) /**< CFG_PAGE_SIZE_32_BYTES Value */ 130 #define MXC_S_SPIXFC_CFG_PAGE_SIZE_32_BYTES (MXC_V_SPIXFC_CFG_PAGE_SIZE_32_BYTES << MXC_F_SPIXFC_CFG_PAGE_SIZE_POS) /**< CFG_PAGE_SIZE_32_BYTES Setting */ 131 132 #define MXC_F_SPIXFC_CFG_HI_CLK_POS 8 /**< CFG_HI_CLK Position */ 133 #define MXC_F_SPIXFC_CFG_HI_CLK ((uint32_t)(0xFUL << MXC_F_SPIXFC_CFG_HI_CLK_POS)) /**< CFG_HI_CLK Mask */ 134 #define MXC_V_SPIXFC_CFG_HI_CLK_16_SCLK ((uint32_t)0x0UL) /**< CFG_HI_CLK_16_SCLK Value */ 135 #define MXC_S_SPIXFC_CFG_HI_CLK_16_SCLK (MXC_V_SPIXFC_CFG_HI_CLK_16_SCLK << MXC_F_SPIXFC_CFG_HI_CLK_POS) /**< CFG_HI_CLK_16_SCLK Setting */ 136 137 #define MXC_F_SPIXFC_CFG_LO_CLK_POS 12 /**< CFG_LO_CLK Position */ 138 #define MXC_F_SPIXFC_CFG_LO_CLK ((uint32_t)(0xFUL << MXC_F_SPIXFC_CFG_LO_CLK_POS)) /**< CFG_LO_CLK Mask */ 139 #define MXC_V_SPIXFC_CFG_LO_CLK_16_SCLK ((uint32_t)0x0UL) /**< CFG_LO_CLK_16_SCLK Value */ 140 #define MXC_S_SPIXFC_CFG_LO_CLK_16_SCLK (MXC_V_SPIXFC_CFG_LO_CLK_16_SCLK << MXC_F_SPIXFC_CFG_LO_CLK_POS) /**< CFG_LO_CLK_16_SCLK Setting */ 141 142 #define MXC_F_SPIXFC_CFG_SSACT_POS 16 /**< CFG_SSACT Position */ 143 #define MXC_F_SPIXFC_CFG_SSACT ((uint32_t)(0x3UL << MXC_F_SPIXFC_CFG_SSACT_POS)) /**< CFG_SSACT Mask */ 144 #define MXC_V_SPIXFC_CFG_SSACT_0_CLKS ((uint32_t)0x0UL) /**< CFG_SSACT_0_CLKS Value */ 145 #define MXC_S_SPIXFC_CFG_SSACT_0_CLKS (MXC_V_SPIXFC_CFG_SSACT_0_CLKS << MXC_F_SPIXFC_CFG_SSACT_POS) /**< CFG_SSACT_0_CLKS Setting */ 146 #define MXC_V_SPIXFC_CFG_SSACT_2_CLKS ((uint32_t)0x1UL) /**< CFG_SSACT_2_CLKS Value */ 147 #define MXC_S_SPIXFC_CFG_SSACT_2_CLKS (MXC_V_SPIXFC_CFG_SSACT_2_CLKS << MXC_F_SPIXFC_CFG_SSACT_POS) /**< CFG_SSACT_2_CLKS Setting */ 148 #define MXC_V_SPIXFC_CFG_SSACT_4_CLKS ((uint32_t)0x2UL) /**< CFG_SSACT_4_CLKS Value */ 149 #define MXC_S_SPIXFC_CFG_SSACT_4_CLKS (MXC_V_SPIXFC_CFG_SSACT_4_CLKS << MXC_F_SPIXFC_CFG_SSACT_POS) /**< CFG_SSACT_4_CLKS Setting */ 150 #define MXC_V_SPIXFC_CFG_SSACT_8_CLKS ((uint32_t)0x3UL) /**< CFG_SSACT_8_CLKS Value */ 151 #define MXC_S_SPIXFC_CFG_SSACT_8_CLKS (MXC_V_SPIXFC_CFG_SSACT_8_CLKS << MXC_F_SPIXFC_CFG_SSACT_POS) /**< CFG_SSACT_8_CLKS Setting */ 152 153 #define MXC_F_SPIXFC_CFG_SSIACT_POS 18 /**< CFG_SSIACT Position */ 154 #define MXC_F_SPIXFC_CFG_SSIACT ((uint32_t)(0x3UL << MXC_F_SPIXFC_CFG_SSIACT_POS)) /**< CFG_SSIACT Mask */ 155 #define MXC_V_SPIXFC_CFG_SSIACT_4_CLKS ((uint32_t)0x0UL) /**< CFG_SSIACT_4_CLKS Value */ 156 #define MXC_S_SPIXFC_CFG_SSIACT_4_CLKS (MXC_V_SPIXFC_CFG_SSIACT_4_CLKS << MXC_F_SPIXFC_CFG_SSIACT_POS) /**< CFG_SSIACT_4_CLKS Setting */ 157 #define MXC_V_SPIXFC_CFG_SSIACT_6_CLKS ((uint32_t)0x1UL) /**< CFG_SSIACT_6_CLKS Value */ 158 #define MXC_S_SPIXFC_CFG_SSIACT_6_CLKS (MXC_V_SPIXFC_CFG_SSIACT_6_CLKS << MXC_F_SPIXFC_CFG_SSIACT_POS) /**< CFG_SSIACT_6_CLKS Setting */ 159 #define MXC_V_SPIXFC_CFG_SSIACT_8_CLKS ((uint32_t)0x2UL) /**< CFG_SSIACT_8_CLKS Value */ 160 #define MXC_S_SPIXFC_CFG_SSIACT_8_CLKS (MXC_V_SPIXFC_CFG_SSIACT_8_CLKS << MXC_F_SPIXFC_CFG_SSIACT_POS) /**< CFG_SSIACT_8_CLKS Setting */ 161 #define MXC_V_SPIXFC_CFG_SSIACT_12_CLKS ((uint32_t)0x3UL) /**< CFG_SSIACT_12_CLKS Value */ 162 #define MXC_S_SPIXFC_CFG_SSIACT_12_CLKS (MXC_V_SPIXFC_CFG_SSIACT_12_CLKS << MXC_F_SPIXFC_CFG_SSIACT_POS) /**< CFG_SSIACT_12_CLKS Setting */ 163 164 #define MXC_F_SPIXFC_CFG_IOSMPL_POS 20 /**< CFG_IOSMPL Position */ 165 #define MXC_F_SPIXFC_CFG_IOSMPL ((uint32_t)(0xFUL << MXC_F_SPIXFC_CFG_IOSMPL_POS)) /**< CFG_IOSMPL Mask */ 166 167 /**@} end of group SPIXFC_CFG_Register */ 168 169 /** 170 * @ingroup spixfc_registers 171 * @defgroup SPIXFC_SS_POL SPIXFC_SS_POL 172 * @brief SPIX Controller Slave Select Polarity Register. 173 * @{ 174 */ 175 #define MXC_F_SPIXFC_SS_POL_SSPOL_0_POS 0 /**< SS_POL_SSPOL_0 Position */ 176 #define MXC_F_SPIXFC_SS_POL_SSPOL_0 ((uint32_t)(0x1UL << MXC_F_SPIXFC_SS_POL_SSPOL_0_POS)) /**< SS_POL_SSPOL_0 Mask */ 177 178 /**@} end of group SPIXFC_SS_POL_Register */ 179 180 /** 181 * @ingroup spixfc_registers 182 * @defgroup SPIXFC_GEN_CTRL SPIXFC_GEN_CTRL 183 * @brief SPIX Controller General Controller Register. 184 * @{ 185 */ 186 #define MXC_F_SPIXFC_GEN_CTRL_ENABLE_POS 0 /**< GEN_CTRL_ENABLE Position */ 187 #define MXC_F_SPIXFC_GEN_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_ENABLE_POS)) /**< GEN_CTRL_ENABLE Mask */ 188 189 #define MXC_F_SPIXFC_GEN_CTRL_TX_FIFO_EN_POS 1 /**< GEN_CTRL_TX_FIFO_EN Position */ 190 #define MXC_F_SPIXFC_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_TX_FIFO_EN_POS)) /**< GEN_CTRL_TX_FIFO_EN Mask */ 191 192 #define MXC_F_SPIXFC_GEN_CTRL_RX_FIFO_EN_POS 2 /**< GEN_CTRL_RX_FIFO_EN Position */ 193 #define MXC_F_SPIXFC_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_RX_FIFO_EN_POS)) /**< GEN_CTRL_RX_FIFO_EN Mask */ 194 195 #define MXC_F_SPIXFC_GEN_CTRL_BBMODE_POS 3 /**< GEN_CTRL_BBMODE Position */ 196 #define MXC_F_SPIXFC_GEN_CTRL_BBMODE ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_BBMODE_POS)) /**< GEN_CTRL_BBMODE Mask */ 197 198 #define MXC_F_SPIXFC_GEN_CTRL_SSDR_POS 4 /**< GEN_CTRL_SSDR Position */ 199 #define MXC_F_SPIXFC_GEN_CTRL_SSDR ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SSDR_POS)) /**< GEN_CTRL_SSDR Mask */ 200 201 #define MXC_F_SPIXFC_GEN_CTRL_SCLK_DR_POS 6 /**< GEN_CTRL_SCLK_DR Position */ 202 #define MXC_F_SPIXFC_GEN_CTRL_SCLK_DR ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SCLK_DR_POS)) /**< GEN_CTRL_SCLK_DR Mask */ 203 204 #define MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS 8 /**< GEN_CTRL_SDIO_DATA_IN Position */ 205 #define MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN ((uint32_t)(0xFUL << MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS)) /**< GEN_CTRL_SDIO_DATA_IN Mask */ 206 #define MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO0 ((uint32_t)0x0UL) /**< GEN_CTRL_SDIO_DATA_IN_SDIO0 Value */ 207 #define MXC_S_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO0 (MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO0 << MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS) /**< GEN_CTRL_SDIO_DATA_IN_SDIO0 Setting */ 208 #define MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO1 ((uint32_t)0x1UL) /**< GEN_CTRL_SDIO_DATA_IN_SDIO1 Value */ 209 #define MXC_S_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO1 (MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO1 << MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS) /**< GEN_CTRL_SDIO_DATA_IN_SDIO1 Setting */ 210 #define MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO2 ((uint32_t)0x2UL) /**< GEN_CTRL_SDIO_DATA_IN_SDIO2 Value */ 211 #define MXC_S_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO2 (MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO2 << MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS) /**< GEN_CTRL_SDIO_DATA_IN_SDIO2 Setting */ 212 #define MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO3 ((uint32_t)0x3UL) /**< GEN_CTRL_SDIO_DATA_IN_SDIO3 Value */ 213 #define MXC_S_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO3 (MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO3 << MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS) /**< GEN_CTRL_SDIO_DATA_IN_SDIO3 Setting */ 214 215 #define MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS 12 /**< GEN_CTRL_BB_DATA Position */ 216 #define MXC_F_SPIXFC_GEN_CTRL_BB_DATA ((uint32_t)(0xFUL << MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS)) /**< GEN_CTRL_BB_DATA Mask */ 217 #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO0 ((uint32_t)0x0UL) /**< GEN_CTRL_BB_DATA_SDIO0 Value */ 218 #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_SDIO0 (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO0 << MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS) /**< GEN_CTRL_BB_DATA_SDIO0 Setting */ 219 #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO1 ((uint32_t)0x1UL) /**< GEN_CTRL_BB_DATA_SDIO1 Value */ 220 #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_SDIO1 (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO1 << MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS) /**< GEN_CTRL_BB_DATA_SDIO1 Setting */ 221 #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO2 ((uint32_t)0x2UL) /**< GEN_CTRL_BB_DATA_SDIO2 Value */ 222 #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_SDIO2 (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO2 << MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS) /**< GEN_CTRL_BB_DATA_SDIO2 Setting */ 223 #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO3 ((uint32_t)0x3UL) /**< GEN_CTRL_BB_DATA_SDIO3 Value */ 224 #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_SDIO3 (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO3 << MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS) /**< GEN_CTRL_BB_DATA_SDIO3 Setting */ 225 226 #define MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS 16 /**< GEN_CTRL_BB_DATA_OUT_EN Position */ 227 #define MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN ((uint32_t)(0xFUL << MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS)) /**< GEN_CTRL_BB_DATA_OUT_EN Mask */ 228 #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO0 ((uint32_t)0x0UL) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO0 Value */ 229 #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO0 (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO0 << MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO0 Setting */ 230 #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO1 ((uint32_t)0x1UL) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO1 Value */ 231 #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO1 (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO1 << MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO1 Setting */ 232 #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO2 ((uint32_t)0x2UL) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO2 Value */ 233 #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO2 (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO2 << MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO2 Setting */ 234 #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO3 ((uint32_t)0x3UL) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO3 Value */ 235 #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO3 (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO3 << MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO3 Setting */ 236 237 #define MXC_F_SPIXFC_GEN_CTRL_SIMPLE_POS 20 /**< GEN_CTRL_SIMPLE Position */ 238 #define MXC_F_SPIXFC_GEN_CTRL_SIMPLE ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SIMPLE_POS)) /**< GEN_CTRL_SIMPLE Mask */ 239 240 #define MXC_F_SPIXFC_GEN_CTRL_SIMPLE_RX_POS 21 /**< GEN_CTRL_SIMPLE_RX Position */ 241 #define MXC_F_SPIXFC_GEN_CTRL_SIMPLE_RX ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SIMPLE_RX_POS)) /**< GEN_CTRL_SIMPLE_RX Mask */ 242 243 #define MXC_F_SPIXFC_GEN_CTRL_SIMPLE_SS_POS 22 /**< GEN_CTRL_SIMPLE_SS Position */ 244 #define MXC_F_SPIXFC_GEN_CTRL_SIMPLE_SS ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SIMPLE_SS_POS)) /**< GEN_CTRL_SIMPLE_SS Mask */ 245 246 #define MXC_F_SPIXFC_GEN_CTRL_SCLK_FB_POS 24 /**< GEN_CTRL_SCLK_FB Position */ 247 #define MXC_F_SPIXFC_GEN_CTRL_SCLK_FB ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SCLK_FB_POS)) /**< GEN_CTRL_SCLK_FB Mask */ 248 249 #define MXC_F_SPIXFC_GEN_CTRL_SCLK_FB_INVERT_POS 25 /**< GEN_CTRL_SCLK_FB_INVERT Position */ 250 #define MXC_F_SPIXFC_GEN_CTRL_SCLK_FB_INVERT ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SCLK_FB_INVERT_POS)) /**< GEN_CTRL_SCLK_FB_INVERT Mask */ 251 252 /**@} end of group SPIXFC_GEN_CTRL_Register */ 253 254 /** 255 * @ingroup spixfc_registers 256 * @defgroup SPIXFC_FIFO_CTRL SPIXFC_FIFO_CTRL 257 * @brief SPIX Controller FIFO Control and Status Register. 258 * @{ 259 */ 260 #define MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0 /**< FIFO_CTRL_TX_FIFO_AE_LVL Position */ 261 #define MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0xFUL << MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_AE_LVL_POS)) /**< FIFO_CTRL_TX_FIFO_AE_LVL Mask */ 262 263 #define MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_CNT_POS 8 /**< FIFO_CTRL_TX_FIFO_CNT Position */ 264 #define MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_CNT ((uint32_t)(0x1FUL << MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_CNT_POS)) /**< FIFO_CTRL_TX_FIFO_CNT Mask */ 265 266 #define MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_AF_LVL_POS 16 /**< FIFO_CTRL_RX_FIFO_AF_LVL Position */ 267 #define MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x1FUL << MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_AF_LVL_POS)) /**< FIFO_CTRL_RX_FIFO_AF_LVL Mask */ 268 269 #define MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_CNT_POS 24 /**< FIFO_CTRL_RX_FIFO_CNT Position */ 270 #define MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_CNT_POS)) /**< FIFO_CTRL_RX_FIFO_CNT Mask */ 271 272 /**@} end of group SPIXFC_FIFO_CTRL_Register */ 273 274 /** 275 * @ingroup spixfc_registers 276 * @defgroup SPIXFC_SP_CTRL SPIXFC_SP_CTRL 277 * @brief SPIX Controller Special Control Register. 278 * @{ 279 */ 280 #define MXC_F_SPIXFC_SP_CTRL_SAMPL_POS 0 /**< SP_CTRL_SAMPL Position */ 281 #define MXC_F_SPIXFC_SP_CTRL_SAMPL ((uint32_t)(0x1UL << MXC_F_SPIXFC_SP_CTRL_SAMPL_POS)) /**< SP_CTRL_SAMPL Mask */ 282 283 #define MXC_F_SPIXFC_SP_CTRL_SDIO_OUT_POS 4 /**< SP_CTRL_SDIO_OUT Position */ 284 #define MXC_F_SPIXFC_SP_CTRL_SDIO_OUT ((uint32_t)(0xFUL << MXC_F_SPIXFC_SP_CTRL_SDIO_OUT_POS)) /**< SP_CTRL_SDIO_OUT Mask */ 285 286 #define MXC_F_SPIXFC_SP_CTRL_SDIO_OUT_EN_POS 8 /**< SP_CTRL_SDIO_OUT_EN Position */ 287 #define MXC_F_SPIXFC_SP_CTRL_SDIO_OUT_EN ((uint32_t)(0xFUL << MXC_F_SPIXFC_SP_CTRL_SDIO_OUT_EN_POS)) /**< SP_CTRL_SDIO_OUT_EN Mask */ 288 289 #define MXC_F_SPIXFC_SP_CTRL_SCLKINH3_POS 16 /**< SP_CTRL_SCLKINH3 Position */ 290 #define MXC_F_SPIXFC_SP_CTRL_SCLKINH3 ((uint32_t)(0x1UL << MXC_F_SPIXFC_SP_CTRL_SCLKINH3_POS)) /**< SP_CTRL_SCLKINH3 Mask */ 291 292 /**@} end of group SPIXFC_SP_CTRL_Register */ 293 294 /** 295 * @ingroup spixfc_registers 296 * @defgroup SPIXFC_INT_FL SPIXFC_INT_FL 297 * @brief SPIX Controller Interrupt Status Register. 298 * @{ 299 */ 300 #define MXC_F_SPIXFC_INT_FL_TX_STALLED_POS 0 /**< INT_FL_TX_STALLED Position */ 301 #define MXC_F_SPIXFC_INT_FL_TX_STALLED ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_FL_TX_STALLED_POS)) /**< INT_FL_TX_STALLED Mask */ 302 303 #define MXC_F_SPIXFC_INT_FL_RX_STALLED_POS 1 /**< INT_FL_RX_STALLED Position */ 304 #define MXC_F_SPIXFC_INT_FL_RX_STALLED ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_FL_RX_STALLED_POS)) /**< INT_FL_RX_STALLED Mask */ 305 306 #define MXC_F_SPIXFC_INT_FL_TX_READY_POS 2 /**< INT_FL_TX_READY Position */ 307 #define MXC_F_SPIXFC_INT_FL_TX_READY ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_FL_TX_READY_POS)) /**< INT_FL_TX_READY Mask */ 308 309 #define MXC_F_SPIXFC_INT_FL_RX_DONE_POS 3 /**< INT_FL_RX_DONE Position */ 310 #define MXC_F_SPIXFC_INT_FL_RX_DONE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_FL_RX_DONE_POS)) /**< INT_FL_RX_DONE Mask */ 311 312 #define MXC_F_SPIXFC_INT_FL_TX_FIFO_AE_POS 4 /**< INT_FL_TX_FIFO_AE Position */ 313 #define MXC_F_SPIXFC_INT_FL_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_FL_TX_FIFO_AE_POS)) /**< INT_FL_TX_FIFO_AE Mask */ 314 315 #define MXC_F_SPIXFC_INT_FL_RX_FIFO_AF_POS 5 /**< INT_FL_RX_FIFO_AF Position */ 316 #define MXC_F_SPIXFC_INT_FL_RX_FIFO_AF ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_FL_RX_FIFO_AF_POS)) /**< INT_FL_RX_FIFO_AF Mask */ 317 318 /**@} end of group SPIXFC_INT_FL_Register */ 319 320 /** 321 * @ingroup spixfc_registers 322 * @defgroup SPIXFC_INT_EN SPIXFC_INT_EN 323 * @brief SPIX Controller Interrupt Enable Register. 324 * @{ 325 */ 326 #define MXC_F_SPIXFC_INT_EN_TX_STALLED_POS 0 /**< INT_EN_TX_STALLED Position */ 327 #define MXC_F_SPIXFC_INT_EN_TX_STALLED ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_EN_TX_STALLED_POS)) /**< INT_EN_TX_STALLED Mask */ 328 329 #define MXC_F_SPIXFC_INT_EN_RX_STALLED_POS 1 /**< INT_EN_RX_STALLED Position */ 330 #define MXC_F_SPIXFC_INT_EN_RX_STALLED ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_EN_RX_STALLED_POS)) /**< INT_EN_RX_STALLED Mask */ 331 332 #define MXC_F_SPIXFC_INT_EN_TX_READY_POS 2 /**< INT_EN_TX_READY Position */ 333 #define MXC_F_SPIXFC_INT_EN_TX_READY ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_EN_TX_READY_POS)) /**< INT_EN_TX_READY Mask */ 334 335 #define MXC_F_SPIXFC_INT_EN_RX_DONE_POS 3 /**< INT_EN_RX_DONE Position */ 336 #define MXC_F_SPIXFC_INT_EN_RX_DONE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_EN_RX_DONE_POS)) /**< INT_EN_RX_DONE Mask */ 337 338 #define MXC_F_SPIXFC_INT_EN_TX_FIFO_AE_POS 4 /**< INT_EN_TX_FIFO_AE Position */ 339 #define MXC_F_SPIXFC_INT_EN_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_EN_TX_FIFO_AE_POS)) /**< INT_EN_TX_FIFO_AE Mask */ 340 341 #define MXC_F_SPIXFC_INT_EN_RX_FIFO_AF_POS 5 /**< INT_EN_RX_FIFO_AF Position */ 342 #define MXC_F_SPIXFC_INT_EN_RX_FIFO_AF ((uint32_t)(0x1UL << MXC_F_SPIXFC_INT_EN_RX_FIFO_AF_POS)) /**< INT_EN_RX_FIFO_AF Mask */ 343 344 /**@} end of group SPIXFC_INT_EN_Register */ 345 346 #ifdef __cplusplus 347 } 348 #endif 349 350 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SPIXFC_REGS_H_ 351
