1 /** 2 * @file spi_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SPI_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SPI_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup spi 66 * @defgroup spi_registers SPI_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. 68 * @details SPI peripheral. 69 */ 70 71 /** 72 * @ingroup spi_registers 73 * Structure type to access the SPI Registers. 74 */ 75 typedef struct { 76 union { 77 __IO uint32_t data32; /**< <tt>\b 0x00:</tt> SPI DATA32 Register */ 78 __IO uint16_t data16[2]; /**< <tt>\b 0x00:</tt> SPI DATA16 Register */ 79 __IO uint8_t data8[4]; /**< <tt>\b 0x00:</tt> SPI DATA8 Register */ 80 }; 81 __IO uint32_t ctrl0; /**< <tt>\b 0x04:</tt> SPI CTRL0 Register */ 82 __IO uint32_t ctrl1; /**< <tt>\b 0x08:</tt> SPI CTRL1 Register */ 83 __IO uint32_t ctrl2; /**< <tt>\b 0x0C:</tt> SPI CTRL2 Register */ 84 __IO uint32_t ss_time; /**< <tt>\b 0x10:</tt> SPI SS_TIME Register */ 85 __IO uint32_t clk_cfg; /**< <tt>\b 0x14:</tt> SPI CLK_CFG Register */ 86 __R uint32_t rsv_0x18; 87 __IO uint32_t dma; /**< <tt>\b 0x1C:</tt> SPI DMA Register */ 88 __IO uint32_t int_fl; /**< <tt>\b 0x20:</tt> SPI INT_FL Register */ 89 __IO uint32_t int_en; /**< <tt>\b 0x24:</tt> SPI INT_EN Register */ 90 __IO uint32_t wake_fl; /**< <tt>\b 0x28:</tt> SPI WAKE_FL Register */ 91 __IO uint32_t wake_en; /**< <tt>\b 0x2C:</tt> SPI WAKE_EN Register */ 92 __I uint32_t stat; /**< <tt>\b 0x30:</tt> SPI STAT Register */ 93 } mxc_spi_regs_t; 94 95 /* Register offsets for module SPI */ 96 /** 97 * @ingroup spi_registers 98 * @defgroup SPI_Register_Offsets Register Offsets 99 * @brief SPI Peripheral Register Offsets from the SPI Base Peripheral Address. 100 * @{ 101 */ 102 #define MXC_R_SPI_DATA32 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */ 103 #define MXC_R_SPI_DATA16 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */ 104 #define MXC_R_SPI_DATA8 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */ 105 #define MXC_R_SPI_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI Base Address: <tt> 0x0004</tt> */ 106 #define MXC_R_SPI_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI Base Address: <tt> 0x0008</tt> */ 107 #define MXC_R_SPI_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI Base Address: <tt> 0x000C</tt> */ 108 #define MXC_R_SPI_SS_TIME ((uint32_t)0x00000010UL) /**< Offset from SPI Base Address: <tt> 0x0010</tt> */ 109 #define MXC_R_SPI_CLK_CFG ((uint32_t)0x00000014UL) /**< Offset from SPI Base Address: <tt> 0x0014</tt> */ 110 #define MXC_R_SPI_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI Base Address: <tt> 0x001C</tt> */ 111 #define MXC_R_SPI_INT_FL ((uint32_t)0x00000020UL) /**< Offset from SPI Base Address: <tt> 0x0020</tt> */ 112 #define MXC_R_SPI_INT_EN ((uint32_t)0x00000024UL) /**< Offset from SPI Base Address: <tt> 0x0024</tt> */ 113 #define MXC_R_SPI_WAKE_FL ((uint32_t)0x00000028UL) /**< Offset from SPI Base Address: <tt> 0x0028</tt> */ 114 #define MXC_R_SPI_WAKE_EN ((uint32_t)0x0000002CUL) /**< Offset from SPI Base Address: <tt> 0x002C</tt> */ 115 #define MXC_R_SPI_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI Base Address: <tt> 0x0030</tt> */ 116 /**@} end of group spi_registers */ 117 118 /** 119 * @ingroup spi_registers 120 * @defgroup SPI_DATA32 SPI_DATA32 121 * @brief Register for reading and writing the FIFO. 122 * @{ 123 */ 124 #define MXC_F_SPI_DATA32_QSPIFIFO_POS 0 /**< DATA32_QSPIFIFO Position */ 125 #define MXC_F_SPI_DATA32_QSPIFIFO ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI_DATA32_QSPIFIFO_POS)) /**< DATA32_QSPIFIFO Mask */ 126 127 /**@} end of group SPI_DATA32_Register */ 128 129 /** 130 * @ingroup spi_registers 131 * @defgroup SPI_DATA16 SPI_DATA16 132 * @brief Register for reading and writing the FIFO. 133 * @{ 134 */ 135 #define MXC_F_SPI_DATA16_QSPIFIFO_POS 0 /**< DATA16_QSPIFIFO Position */ 136 #define MXC_F_SPI_DATA16_QSPIFIFO ((uint16_t)(0xFFFFUL << MXC_F_SPI_DATA16_QSPIFIFO_POS)) /**< DATA16_QSPIFIFO Mask */ 137 138 /**@} end of group SPI_DATA16_Register */ 139 140 /** 141 * @ingroup spi_registers 142 * @defgroup SPI_DATA8 SPI_DATA8 143 * @brief Register for reading and writing the FIFO. 144 * @{ 145 */ 146 #define MXC_F_SPI_DATA8_QSPIFIFO_POS 0 /**< DATA8_QSPIFIFO Position */ 147 #define MXC_F_SPI_DATA8_QSPIFIFO ((uint8_t)(0xFFUL << MXC_F_SPI_DATA8_QSPIFIFO_POS)) /**< DATA8_QSPIFIFO Mask */ 148 149 /**@} end of group SPI_DATA8_Register */ 150 151 /** 152 * @ingroup spi_registers 153 * @defgroup SPI_CTRL0 SPI_CTRL0 154 * @brief Register for controlling SPI peripheral. 155 * @{ 156 */ 157 #define MXC_F_SPI_CTRL0_EN_POS 0 /**< CTRL0_EN Position */ 158 #define MXC_F_SPI_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_EN_POS)) /**< CTRL0_EN Mask */ 159 160 #define MXC_F_SPI_CTRL0_MASTER_POS 1 /**< CTRL0_MASTER Position */ 161 #define MXC_F_SPI_CTRL0_MASTER ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MASTER_POS)) /**< CTRL0_MASTER Mask */ 162 163 #define MXC_F_SPI_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */ 164 #define MXC_F_SPI_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */ 165 166 #define MXC_F_SPI_CTRL0_START_POS 5 /**< CTRL0_START Position */ 167 #define MXC_F_SPI_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS)) /**< CTRL0_START Mask */ 168 169 #define MXC_F_SPI_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */ 170 #define MXC_F_SPI_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */ 171 172 #define MXC_F_SPI_CTRL0_SS_POS 16 /**< CTRL0_SS Position */ 173 #define MXC_F_SPI_CTRL0_SS ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_SS_POS)) /**< CTRL0_SS Mask */ 174 #define MXC_V_SPI_CTRL0_SS_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_SS0 Value */ 175 #define MXC_S_SPI_CTRL0_SS_SS0 (MXC_V_SPI_CTRL0_SS_SS0 << MXC_F_SPI_CTRL0_SS_POS) /**< CTRL0_SS_SS0 Setting */ 176 #define MXC_V_SPI_CTRL0_SS_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_SS1 Value */ 177 #define MXC_S_SPI_CTRL0_SS_SS1 (MXC_V_SPI_CTRL0_SS_SS1 << MXC_F_SPI_CTRL0_SS_POS) /**< CTRL0_SS_SS1 Setting */ 178 #define MXC_V_SPI_CTRL0_SS_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_SS2 Value */ 179 #define MXC_S_SPI_CTRL0_SS_SS2 (MXC_V_SPI_CTRL0_SS_SS2 << MXC_F_SPI_CTRL0_SS_POS) /**< CTRL0_SS_SS2 Setting */ 180 #define MXC_V_SPI_CTRL0_SS_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_SS3 Value */ 181 #define MXC_S_SPI_CTRL0_SS_SS3 (MXC_V_SPI_CTRL0_SS_SS3 << MXC_F_SPI_CTRL0_SS_POS) /**< CTRL0_SS_SS3 Setting */ 182 183 /**@} end of group SPI_CTRL0_Register */ 184 185 /** 186 * @ingroup spi_registers 187 * @defgroup SPI_CTRL1 SPI_CTRL1 188 * @brief Register for controlling SPI peripheral. 189 * @{ 190 */ 191 #define MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */ 192 #define MXC_F_SPI_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */ 193 194 #define MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */ 195 #define MXC_F_SPI_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */ 196 197 /**@} end of group SPI_CTRL1_Register */ 198 199 /** 200 * @ingroup spi_registers 201 * @defgroup SPI_CTRL2 SPI_CTRL2 202 * @brief Register for controlling SPI peripheral. 203 * @{ 204 */ 205 #define MXC_F_SPI_CTRL2_CPHA_POS 0 /**< CTRL2_CPHA Position */ 206 #define MXC_F_SPI_CTRL2_CPHA ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CPHA_POS)) /**< CTRL2_CPHA Mask */ 207 208 #define MXC_F_SPI_CTRL2_CPOL_POS 1 /**< CTRL2_CPOL Position */ 209 #define MXC_F_SPI_CTRL2_CPOL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CPOL_POS)) /**< CTRL2_CPOL Mask */ 210 211 #define MXC_F_SPI_CTRL2_NUMBITS_POS 8 /**< CTRL2_NUMBITS Position */ 212 #define MXC_F_SPI_CTRL2_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUMBITS_POS)) /**< CTRL2_NUMBITS Mask */ 213 #define MXC_V_SPI_CTRL2_NUMBITS_0 ((uint32_t)0x0UL) /**< CTRL2_NUMBITS_0 Value */ 214 #define MXC_S_SPI_CTRL2_NUMBITS_0 (MXC_V_SPI_CTRL2_NUMBITS_0 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_0 Setting */ 215 216 #define MXC_F_SPI_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */ 217 #define MXC_F_SPI_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */ 218 #define MXC_V_SPI_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */ 219 #define MXC_S_SPI_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */ 220 #define MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */ 221 #define MXC_S_SPI_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */ 222 #define MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */ 223 #define MXC_S_SPI_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */ 224 225 #define MXC_F_SPI_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */ 226 #define MXC_F_SPI_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */ 227 228 #define MXC_F_SPI_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */ 229 #define MXC_F_SPI_CTRL2_SS_POL ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */ 230 #define MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SS_POL_SS0_HIGH Value */ 231 #define MXC_S_SPI_CTRL2_SS_POL_SS0_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS0_HIGH Setting */ 232 #define MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SS_POL_SS1_HIGH Value */ 233 #define MXC_S_SPI_CTRL2_SS_POL_SS1_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS1_HIGH Setting */ 234 #define MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SS_POL_SS2_HIGH Value */ 235 #define MXC_S_SPI_CTRL2_SS_POL_SS2_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS2_HIGH Setting */ 236 #define MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SS_POL_SS3_HIGH Value */ 237 #define MXC_S_SPI_CTRL2_SS_POL_SS3_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS3_HIGH Setting */ 238 239 /**@} end of group SPI_CTRL2_Register */ 240 241 /** 242 * @ingroup spi_registers 243 * @defgroup SPI_SS_TIME SPI_SS_TIME 244 * @brief Register for controlling SPI peripheral/Slave Select Timing. 245 * @{ 246 */ 247 #define MXC_F_SPI_SS_TIME_PRE_POS 0 /**< SS_TIME_PRE Position */ 248 #define MXC_F_SPI_SS_TIME_PRE ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_PRE_POS)) /**< SS_TIME_PRE Mask */ 249 #define MXC_V_SPI_SS_TIME_PRE_256 ((uint32_t)0x0UL) /**< SS_TIME_PRE_256 Value */ 250 #define MXC_S_SPI_SS_TIME_PRE_256 (MXC_V_SPI_SS_TIME_PRE_256 << MXC_F_SPI_SS_TIME_PRE_POS) /**< SS_TIME_PRE_256 Setting */ 251 252 #define MXC_F_SPI_SS_TIME_POST_POS 8 /**< SS_TIME_POST Position */ 253 #define MXC_F_SPI_SS_TIME_POST ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_POST_POS)) /**< SS_TIME_POST Mask */ 254 #define MXC_V_SPI_SS_TIME_POST_256 ((uint32_t)0x0UL) /**< SS_TIME_POST_256 Value */ 255 #define MXC_S_SPI_SS_TIME_POST_256 (MXC_V_SPI_SS_TIME_POST_256 << MXC_F_SPI_SS_TIME_POST_POS) /**< SS_TIME_POST_256 Setting */ 256 257 #define MXC_F_SPI_SS_TIME_INACT_POS 16 /**< SS_TIME_INACT Position */ 258 #define MXC_F_SPI_SS_TIME_INACT ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_INACT_POS)) /**< SS_TIME_INACT Mask */ 259 #define MXC_V_SPI_SS_TIME_INACT_256 ((uint32_t)0x0UL) /**< SS_TIME_INACT_256 Value */ 260 #define MXC_S_SPI_SS_TIME_INACT_256 (MXC_V_SPI_SS_TIME_INACT_256 << MXC_F_SPI_SS_TIME_INACT_POS) /**< SS_TIME_INACT_256 Setting */ 261 262 /**@} end of group SPI_SS_TIME_Register */ 263 264 /** 265 * @ingroup spi_registers 266 * @defgroup SPI_CLK_CFG SPI_CLK_CFG 267 * @brief Register for controlling SPI clock rate. 268 * @{ 269 */ 270 #define MXC_F_SPI_CLK_CFG_LO_POS 0 /**< CLK_CFG_LO Position */ 271 #define MXC_F_SPI_CLK_CFG_LO ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_LO_POS)) /**< CLK_CFG_LO Mask */ 272 #define MXC_V_SPI_CLK_CFG_LO_DIS ((uint32_t)0x0UL) /**< CLK_CFG_LO_DIS Value */ 273 #define MXC_S_SPI_CLK_CFG_LO_DIS (MXC_V_SPI_CLK_CFG_LO_DIS << MXC_F_SPI_CLK_CFG_LO_POS) /**< CLK_CFG_LO_DIS Setting */ 274 275 #define MXC_F_SPI_CLK_CFG_HI_POS 8 /**< CLK_CFG_HI Position */ 276 #define MXC_F_SPI_CLK_CFG_HI ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_HI_POS)) /**< CLK_CFG_HI Mask */ 277 #define MXC_V_SPI_CLK_CFG_HI_DIS ((uint32_t)0x0UL) /**< CLK_CFG_HI_DIS Value */ 278 #define MXC_S_SPI_CLK_CFG_HI_DIS (MXC_V_SPI_CLK_CFG_HI_DIS << MXC_F_SPI_CLK_CFG_HI_POS) /**< CLK_CFG_HI_DIS Setting */ 279 280 #define MXC_F_SPI_CLK_CFG_SCALE_POS 16 /**< CLK_CFG_SCALE Position */ 281 #define MXC_F_SPI_CLK_CFG_SCALE ((uint32_t)(0xFUL << MXC_F_SPI_CLK_CFG_SCALE_POS)) /**< CLK_CFG_SCALE Mask */ 282 283 /**@} end of group SPI_CLK_CFG_Register */ 284 285 /** 286 * @ingroup spi_registers 287 * @defgroup SPI_DMA SPI_DMA 288 * @brief Register for controlling DMA. 289 * @{ 290 */ 291 #define MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS 0 /**< DMA_TX_FIFO_LEVEL Position */ 292 #define MXC_F_SPI_DMA_TX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */ 293 294 #define MXC_F_SPI_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */ 295 #define MXC_F_SPI_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */ 296 297 #define MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS 7 /**< DMA_TX_FIFO_CLEAR Position */ 298 #define MXC_F_SPI_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */ 299 300 #define MXC_F_SPI_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */ 301 #define MXC_F_SPI_DMA_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */ 302 303 #define MXC_F_SPI_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */ 304 #define MXC_F_SPI_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */ 305 306 #define MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS 16 /**< DMA_RX_FIFO_LEVEL Position */ 307 #define MXC_F_SPI_DMA_RX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */ 308 309 #define MXC_F_SPI_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */ 310 #define MXC_F_SPI_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */ 311 312 #define MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS 23 /**< DMA_RX_FIFO_CLEAR Position */ 313 #define MXC_F_SPI_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */ 314 315 #define MXC_F_SPI_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */ 316 #define MXC_F_SPI_DMA_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */ 317 318 #define MXC_F_SPI_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */ 319 #define MXC_F_SPI_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */ 320 321 /**@} end of group SPI_DMA_Register */ 322 323 /** 324 * @ingroup spi_registers 325 * @defgroup SPI_INT_FL SPI_INT_FL 326 * @brief Register for reading and clearing interrupt flags. All bits are write 1 to 327 * clear. 328 * @{ 329 */ 330 #define MXC_F_SPI_INT_FL_TX_THRESH_POS 0 /**< INT_FL_TX_THRESH Position */ 331 #define MXC_F_SPI_INT_FL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_THRESH_POS)) /**< INT_FL_TX_THRESH Mask */ 332 333 #define MXC_F_SPI_INT_FL_TX_EMPTY_POS 1 /**< INT_FL_TX_EMPTY Position */ 334 #define MXC_F_SPI_INT_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_EMPTY_POS)) /**< INT_FL_TX_EMPTY Mask */ 335 336 #define MXC_F_SPI_INT_FL_RX_THRESH_POS 2 /**< INT_FL_RX_THRESH Position */ 337 #define MXC_F_SPI_INT_FL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_THRESH_POS)) /**< INT_FL_RX_THRESH Mask */ 338 339 #define MXC_F_SPI_INT_FL_RX_FULL_POS 3 /**< INT_FL_RX_FULL Position */ 340 #define MXC_F_SPI_INT_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_FULL_POS)) /**< INT_FL_RX_FULL Mask */ 341 342 #define MXC_F_SPI_INT_FL_SSA_POS 4 /**< INT_FL_SSA Position */ 343 #define MXC_F_SPI_INT_FL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSA_POS)) /**< INT_FL_SSA Mask */ 344 345 #define MXC_F_SPI_INT_FL_SSD_POS 5 /**< INT_FL_SSD Position */ 346 #define MXC_F_SPI_INT_FL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSD_POS)) /**< INT_FL_SSD Mask */ 347 348 #define MXC_F_SPI_INT_FL_FAULT_POS 8 /**< INT_FL_FAULT Position */ 349 #define MXC_F_SPI_INT_FL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_FAULT_POS)) /**< INT_FL_FAULT Mask */ 350 351 #define MXC_F_SPI_INT_FL_ABORT_POS 9 /**< INT_FL_ABORT Position */ 352 #define MXC_F_SPI_INT_FL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_ABORT_POS)) /**< INT_FL_ABORT Mask */ 353 354 #define MXC_F_SPI_INT_FL_M_DONE_POS 11 /**< INT_FL_M_DONE Position */ 355 #define MXC_F_SPI_INT_FL_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_M_DONE_POS)) /**< INT_FL_M_DONE Mask */ 356 357 #define MXC_F_SPI_INT_FL_TX_OVR_POS 12 /**< INT_FL_TX_OVR Position */ 358 #define MXC_F_SPI_INT_FL_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_OVR_POS)) /**< INT_FL_TX_OVR Mask */ 359 360 #define MXC_F_SPI_INT_FL_TX_UND_POS 13 /**< INT_FL_TX_UND Position */ 361 #define MXC_F_SPI_INT_FL_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_UND_POS)) /**< INT_FL_TX_UND Mask */ 362 363 #define MXC_F_SPI_INT_FL_RX_OVR_POS 14 /**< INT_FL_RX_OVR Position */ 364 #define MXC_F_SPI_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */ 365 366 #define MXC_F_SPI_INT_FL_RX_UND_POS 15 /**< INT_FL_RX_UND Position */ 367 #define MXC_F_SPI_INT_FL_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_UND_POS)) /**< INT_FL_RX_UND Mask */ 368 369 /**@} end of group SPI_INT_FL_Register */ 370 371 /** 372 * @ingroup spi_registers 373 * @defgroup SPI_INT_EN SPI_INT_EN 374 * @brief Register for enabling interrupts. 375 * @{ 376 */ 377 #define MXC_F_SPI_INT_EN_TX_THRESH_POS 0 /**< INT_EN_TX_THRESH Position */ 378 #define MXC_F_SPI_INT_EN_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_THRESH_POS)) /**< INT_EN_TX_THRESH Mask */ 379 380 #define MXC_F_SPI_INT_EN_TX_EMPTY_POS 1 /**< INT_EN_TX_EMPTY Position */ 381 #define MXC_F_SPI_INT_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_EMPTY_POS)) /**< INT_EN_TX_EMPTY Mask */ 382 383 #define MXC_F_SPI_INT_EN_RX_THRESH_POS 2 /**< INT_EN_RX_THRESH Position */ 384 #define MXC_F_SPI_INT_EN_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_THRESH_POS)) /**< INT_EN_RX_THRESH Mask */ 385 386 #define MXC_F_SPI_INT_EN_RX_FULL_POS 3 /**< INT_EN_RX_FULL Position */ 387 #define MXC_F_SPI_INT_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_FULL_POS)) /**< INT_EN_RX_FULL Mask */ 388 389 #define MXC_F_SPI_INT_EN_SSA_POS 4 /**< INT_EN_SSA Position */ 390 #define MXC_F_SPI_INT_EN_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSA_POS)) /**< INT_EN_SSA Mask */ 391 392 #define MXC_F_SPI_INT_EN_SSD_POS 5 /**< INT_EN_SSD Position */ 393 #define MXC_F_SPI_INT_EN_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSD_POS)) /**< INT_EN_SSD Mask */ 394 395 #define MXC_F_SPI_INT_EN_FAULT_POS 8 /**< INT_EN_FAULT Position */ 396 #define MXC_F_SPI_INT_EN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_FAULT_POS)) /**< INT_EN_FAULT Mask */ 397 398 #define MXC_F_SPI_INT_EN_ABORT_POS 9 /**< INT_EN_ABORT Position */ 399 #define MXC_F_SPI_INT_EN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_ABORT_POS)) /**< INT_EN_ABORT Mask */ 400 401 #define MXC_F_SPI_INT_EN_M_DONE_POS 11 /**< INT_EN_M_DONE Position */ 402 #define MXC_F_SPI_INT_EN_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_M_DONE_POS)) /**< INT_EN_M_DONE Mask */ 403 404 #define MXC_F_SPI_INT_EN_TX_OVR_POS 12 /**< INT_EN_TX_OVR Position */ 405 #define MXC_F_SPI_INT_EN_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_OVR_POS)) /**< INT_EN_TX_OVR Mask */ 406 407 #define MXC_F_SPI_INT_EN_TX_UND_POS 13 /**< INT_EN_TX_UND Position */ 408 #define MXC_F_SPI_INT_EN_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_UND_POS)) /**< INT_EN_TX_UND Mask */ 409 410 #define MXC_F_SPI_INT_EN_RX_OVR_POS 14 /**< INT_EN_RX_OVR Position */ 411 #define MXC_F_SPI_INT_EN_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_OVR_POS)) /**< INT_EN_RX_OVR Mask */ 412 413 #define MXC_F_SPI_INT_EN_RX_UND_POS 15 /**< INT_EN_RX_UND Position */ 414 #define MXC_F_SPI_INT_EN_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_UND_POS)) /**< INT_EN_RX_UND Mask */ 415 416 /**@} end of group SPI_INT_EN_Register */ 417 418 /** 419 * @ingroup spi_registers 420 * @defgroup SPI_WAKE_FL SPI_WAKE_FL 421 * @brief Register for wake up flags. All bits in this register are write 1 to clear. 422 * @{ 423 */ 424 #define MXC_F_SPI_WAKE_FL_TX_THRESH_POS 0 /**< WAKE_FL_TX_THRESH Position */ 425 #define MXC_F_SPI_WAKE_FL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TX_THRESH_POS)) /**< WAKE_FL_TX_THRESH Mask */ 426 427 #define MXC_F_SPI_WAKE_FL_TX_EMPTY_POS 1 /**< WAKE_FL_TX_EMPTY Position */ 428 #define MXC_F_SPI_WAKE_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TX_EMPTY_POS)) /**< WAKE_FL_TX_EMPTY Mask */ 429 430 #define MXC_F_SPI_WAKE_FL_RX_THRESH_POS 2 /**< WAKE_FL_RX_THRESH Position */ 431 #define MXC_F_SPI_WAKE_FL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RX_THRESH_POS)) /**< WAKE_FL_RX_THRESH Mask */ 432 433 #define MXC_F_SPI_WAKE_FL_RX_FULL_POS 3 /**< WAKE_FL_RX_FULL Position */ 434 #define MXC_F_SPI_WAKE_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RX_FULL_POS)) /**< WAKE_FL_RX_FULL Mask */ 435 436 /**@} end of group SPI_WAKE_FL_Register */ 437 438 /** 439 * @ingroup spi_registers 440 * @defgroup SPI_WAKE_EN SPI_WAKE_EN 441 * @brief Register for wake up enable. 442 * @{ 443 */ 444 #define MXC_F_SPI_WAKE_EN_TX_THRESH_POS 0 /**< WAKE_EN_TX_THRESH Position */ 445 #define MXC_F_SPI_WAKE_EN_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TX_THRESH_POS)) /**< WAKE_EN_TX_THRESH Mask */ 446 447 #define MXC_F_SPI_WAKE_EN_TX_EMPTY_POS 1 /**< WAKE_EN_TX_EMPTY Position */ 448 #define MXC_F_SPI_WAKE_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TX_EMPTY_POS)) /**< WAKE_EN_TX_EMPTY Mask */ 449 450 #define MXC_F_SPI_WAKE_EN_RX_THRESH_POS 2 /**< WAKE_EN_RX_THRESH Position */ 451 #define MXC_F_SPI_WAKE_EN_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RX_THRESH_POS)) /**< WAKE_EN_RX_THRESH Mask */ 452 453 #define MXC_F_SPI_WAKE_EN_RX_FULL_POS 3 /**< WAKE_EN_RX_FULL Position */ 454 #define MXC_F_SPI_WAKE_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RX_FULL_POS)) /**< WAKE_EN_RX_FULL Mask */ 455 456 /**@} end of group SPI_WAKE_EN_Register */ 457 458 /** 459 * @ingroup spi_registers 460 * @defgroup SPI_STAT SPI_STAT 461 * @brief SPI Status register. 462 * @{ 463 */ 464 #define MXC_F_SPI_STAT_BUSY_POS 0 /**< STAT_BUSY Position */ 465 #define MXC_F_SPI_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_STAT_BUSY_POS)) /**< STAT_BUSY Mask */ 466 467 /**@} end of group SPI_STAT_Register */ 468 469 #ifdef __cplusplus 470 } 471 #endif 472 473 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SPI_REGS_H_ 474
