1 /** 2 * @file smon_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SMON Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SMON_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SMON_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup smon 66 * @defgroup smon_registers SMON_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the SMON Peripheral Module. 68 * @details The Security Monitor block used to monitor system threat conditions. 69 */ 70 71 /** 72 * @ingroup smon_registers 73 * Structure type to access the SMON Registers. 74 */ 75 typedef struct { 76 __IO uint32_t extscn; /**< <tt>\b 0x00:</tt> SMON EXTSCN Register */ 77 __IO uint32_t intscn; /**< <tt>\b 0x04:</tt> SMON INTSCN Register */ 78 __IO uint32_t secalm; /**< <tt>\b 0x08:</tt> SMON SECALM Register */ 79 __IO uint32_t secdiag; /**< <tt>\b 0x0C:</tt> SMON SECDIAG Register */ 80 __I uint32_t dlrtc; /**< <tt>\b 0x10:</tt> SMON DLRTC Register */ 81 __R uint32_t rsv_0x14_0x23[4]; 82 __IO uint32_t meucfg; /**< <tt>\b 0x24:</tt> SMON MEUCFG Register */ 83 __R uint32_t rsv_0x28_0x33[3]; 84 __I uint32_t secst; /**< <tt>\b 0x34:</tt> SMON SECST Register */ 85 __IO uint32_t sdbe; /**< <tt>\b 0x38:</tt> SMON SDBE Register */ 86 } mxc_smon_regs_t; 87 88 /* Register offsets for module SMON */ 89 /** 90 * @ingroup smon_registers 91 * @defgroup SMON_Register_Offsets Register Offsets 92 * @brief SMON Peripheral Register Offsets from the SMON Base Peripheral Address. 93 * @{ 94 */ 95 #define MXC_R_SMON_EXTSCN ((uint32_t)0x00000000UL) /**< Offset from SMON Base Address: <tt> 0x0000</tt> */ 96 #define MXC_R_SMON_INTSCN ((uint32_t)0x00000004UL) /**< Offset from SMON Base Address: <tt> 0x0004</tt> */ 97 #define MXC_R_SMON_SECALM ((uint32_t)0x00000008UL) /**< Offset from SMON Base Address: <tt> 0x0008</tt> */ 98 #define MXC_R_SMON_SECDIAG ((uint32_t)0x0000000CUL) /**< Offset from SMON Base Address: <tt> 0x000C</tt> */ 99 #define MXC_R_SMON_DLRTC ((uint32_t)0x00000010UL) /**< Offset from SMON Base Address: <tt> 0x0010</tt> */ 100 #define MXC_R_SMON_MEUCFG ((uint32_t)0x00000024UL) /**< Offset from SMON Base Address: <tt> 0x0024</tt> */ 101 #define MXC_R_SMON_SECST ((uint32_t)0x00000034UL) /**< Offset from SMON Base Address: <tt> 0x0034</tt> */ 102 #define MXC_R_SMON_SDBE ((uint32_t)0x00000038UL) /**< Offset from SMON Base Address: <tt> 0x0038</tt> */ 103 /**@} end of group smon_registers */ 104 105 /** 106 * @ingroup smon_registers 107 * @defgroup SMON_EXTSCN SMON_EXTSCN 108 * @brief External Sensor Control Register. 109 * @{ 110 */ 111 #define MXC_F_SMON_EXTSCN_EXTS_EN0_POS 0 /**< EXTSCN_EXTS_EN0 Position */ 112 #define MXC_F_SMON_EXTSCN_EXTS_EN0 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN0_POS)) /**< EXTSCN_EXTS_EN0 Mask */ 113 114 #define MXC_F_SMON_EXTSCN_EXTS_EN1_POS 1 /**< EXTSCN_EXTS_EN1 Position */ 115 #define MXC_F_SMON_EXTSCN_EXTS_EN1 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN1_POS)) /**< EXTSCN_EXTS_EN1 Mask */ 116 117 #define MXC_F_SMON_EXTSCN_EXTS_EN2_POS 2 /**< EXTSCN_EXTS_EN2 Position */ 118 #define MXC_F_SMON_EXTSCN_EXTS_EN2 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN2_POS)) /**< EXTSCN_EXTS_EN2 Mask */ 119 120 #define MXC_F_SMON_EXTSCN_EXTS_EN3_POS 3 /**< EXTSCN_EXTS_EN3 Position */ 121 #define MXC_F_SMON_EXTSCN_EXTS_EN3 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN3_POS)) /**< EXTSCN_EXTS_EN3 Mask */ 122 123 #define MXC_F_SMON_EXTSCN_EXTS_EN4_POS 4 /**< EXTSCN_EXTS_EN4 Position */ 124 #define MXC_F_SMON_EXTSCN_EXTS_EN4 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN4_POS)) /**< EXTSCN_EXTS_EN4 Mask */ 125 126 #define MXC_F_SMON_EXTSCN_EXTS_EN5_POS 5 /**< EXTSCN_EXTS_EN5 Position */ 127 #define MXC_F_SMON_EXTSCN_EXTS_EN5 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN5_POS)) /**< EXTSCN_EXTS_EN5 Mask */ 128 129 #define MXC_F_SMON_EXTSCN_EXTCNT_POS 16 /**< EXTSCN_EXTCNT Position */ 130 #define MXC_F_SMON_EXTSCN_EXTCNT ((uint32_t)(0x1FUL << MXC_F_SMON_EXTSCN_EXTCNT_POS)) /**< EXTSCN_EXTCNT Mask */ 131 132 #define MXC_F_SMON_EXTSCN_EXTFRQ_POS 21 /**< EXTSCN_EXTFRQ Position */ 133 #define MXC_F_SMON_EXTSCN_EXTFRQ ((uint32_t)(0x7UL << MXC_F_SMON_EXTSCN_EXTFRQ_POS)) /**< EXTSCN_EXTFRQ Mask */ 134 #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ2000HZ ((uint32_t)0x0UL) /**< EXTSCN_EXTFRQ_FREQ2000HZ Value */ 135 #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ2000HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ2000HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ2000HZ Setting */ 136 #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ1000HZ ((uint32_t)0x1UL) /**< EXTSCN_EXTFRQ_FREQ1000HZ Value */ 137 #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ1000HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ1000HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ1000HZ Setting */ 138 #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ500HZ ((uint32_t)0x2UL) /**< EXTSCN_EXTFRQ_FREQ500HZ Value */ 139 #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ500HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ500HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ500HZ Setting */ 140 #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ250HZ ((uint32_t)0x3UL) /**< EXTSCN_EXTFRQ_FREQ250HZ Value */ 141 #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ250HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ250HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ250HZ Setting */ 142 #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ125HZ ((uint32_t)0x4UL) /**< EXTSCN_EXTFRQ_FREQ125HZ Value */ 143 #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ125HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ125HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ125HZ Setting */ 144 #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ63HZ ((uint32_t)0x5UL) /**< EXTSCN_EXTFRQ_FREQ63HZ Value */ 145 #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ63HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ63HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ63HZ Setting */ 146 #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ31HZ ((uint32_t)0x6UL) /**< EXTSCN_EXTFRQ_FREQ31HZ Value */ 147 #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ31HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ31HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ31HZ Setting */ 148 #define MXC_V_SMON_EXTSCN_EXTFRQ_RFU ((uint32_t)0x7UL) /**< EXTSCN_EXTFRQ_RFU Value */ 149 #define MXC_S_SMON_EXTSCN_EXTFRQ_RFU (MXC_V_SMON_EXTSCN_EXTFRQ_RFU << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_RFU Setting */ 150 151 #define MXC_F_SMON_EXTSCN_DIVCLK_POS 24 /**< EXTSCN_DIVCLK Position */ 152 #define MXC_F_SMON_EXTSCN_DIVCLK ((uint32_t)(0x7UL << MXC_F_SMON_EXTSCN_DIVCLK_POS)) /**< EXTSCN_DIVCLK Mask */ 153 #define MXC_V_SMON_EXTSCN_DIVCLK_DIV1 ((uint32_t)0x0UL) /**< EXTSCN_DIVCLK_DIV1 Value */ 154 #define MXC_S_SMON_EXTSCN_DIVCLK_DIV1 (MXC_V_SMON_EXTSCN_DIVCLK_DIV1 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV1 Setting */ 155 #define MXC_V_SMON_EXTSCN_DIVCLK_DIV2 ((uint32_t)0x1UL) /**< EXTSCN_DIVCLK_DIV2 Value */ 156 #define MXC_S_SMON_EXTSCN_DIVCLK_DIV2 (MXC_V_SMON_EXTSCN_DIVCLK_DIV2 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV2 Setting */ 157 #define MXC_V_SMON_EXTSCN_DIVCLK_DIV4 ((uint32_t)0x2UL) /**< EXTSCN_DIVCLK_DIV4 Value */ 158 #define MXC_S_SMON_EXTSCN_DIVCLK_DIV4 (MXC_V_SMON_EXTSCN_DIVCLK_DIV4 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV4 Setting */ 159 #define MXC_V_SMON_EXTSCN_DIVCLK_DIV8 ((uint32_t)0x3UL) /**< EXTSCN_DIVCLK_DIV8 Value */ 160 #define MXC_S_SMON_EXTSCN_DIVCLK_DIV8 (MXC_V_SMON_EXTSCN_DIVCLK_DIV8 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV8 Setting */ 161 #define MXC_V_SMON_EXTSCN_DIVCLK_DIV16 ((uint32_t)0x4UL) /**< EXTSCN_DIVCLK_DIV16 Value */ 162 #define MXC_S_SMON_EXTSCN_DIVCLK_DIV16 (MXC_V_SMON_EXTSCN_DIVCLK_DIV16 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV16 Setting */ 163 #define MXC_V_SMON_EXTSCN_DIVCLK_DIV32 ((uint32_t)0x5UL) /**< EXTSCN_DIVCLK_DIV32 Value */ 164 #define MXC_S_SMON_EXTSCN_DIVCLK_DIV32 (MXC_V_SMON_EXTSCN_DIVCLK_DIV32 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV32 Setting */ 165 #define MXC_V_SMON_EXTSCN_DIVCLK_DIV64 ((uint32_t)0x6UL) /**< EXTSCN_DIVCLK_DIV64 Value */ 166 #define MXC_S_SMON_EXTSCN_DIVCLK_DIV64 (MXC_V_SMON_EXTSCN_DIVCLK_DIV64 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV64 Setting */ 167 168 #define MXC_F_SMON_EXTSCN_BUSY_POS 30 /**< EXTSCN_BUSY Position */ 169 #define MXC_F_SMON_EXTSCN_BUSY ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_BUSY_POS)) /**< EXTSCN_BUSY Mask */ 170 171 #define MXC_F_SMON_EXTSCN_LOCK_POS 31 /**< EXTSCN_LOCK Position */ 172 #define MXC_F_SMON_EXTSCN_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_LOCK_POS)) /**< EXTSCN_LOCK Mask */ 173 174 /**@} end of group SMON_EXTSCN_Register */ 175 176 /** 177 * @ingroup smon_registers 178 * @defgroup SMON_INTSCN SMON_INTSCN 179 * @brief Internal Sensor Control Register. 180 * @{ 181 */ 182 #define MXC_F_SMON_INTSCN_SHIELD_EN_POS 0 /**< INTSCN_SHIELD_EN Position */ 183 #define MXC_F_SMON_INTSCN_SHIELD_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_SHIELD_EN_POS)) /**< INTSCN_SHIELD_EN Mask */ 184 185 #define MXC_F_SMON_INTSCN_TEMP_EN_POS 1 /**< INTSCN_TEMP_EN Position */ 186 #define MXC_F_SMON_INTSCN_TEMP_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_TEMP_EN_POS)) /**< INTSCN_TEMP_EN Mask */ 187 188 #define MXC_F_SMON_INTSCN_VBAT_EN_POS 2 /**< INTSCN_VBAT_EN Position */ 189 #define MXC_F_SMON_INTSCN_VBAT_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VBAT_EN_POS)) /**< INTSCN_VBAT_EN Mask */ 190 191 #define MXC_F_SMON_INTSCN_DFD_EN_POS 3 /**< INTSCN_DFD_EN Position */ 192 #define MXC_F_SMON_INTSCN_DFD_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_DFD_EN_POS)) /**< INTSCN_DFD_EN Mask */ 193 194 #define MXC_F_SMON_INTSCN_DFD_NMI_POS 4 /**< INTSCN_DFD_NMI Position */ 195 #define MXC_F_SMON_INTSCN_DFD_NMI ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_DFD_NMI_POS)) /**< INTSCN_DFD_NMI Mask */ 196 197 #define MXC_F_SMON_INTSCN_DFD_STDBY_POS 8 /**< INTSCN_DFD_STDBY Position */ 198 #define MXC_F_SMON_INTSCN_DFD_STDBY ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_DFD_STDBY_POS)) /**< INTSCN_DFD_STDBY Mask */ 199 200 #define MXC_F_SMON_INTSCN_LOTEMP_SEL_POS 16 /**< INTSCN_LOTEMP_SEL Position */ 201 #define MXC_F_SMON_INTSCN_LOTEMP_SEL ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_LOTEMP_SEL_POS)) /**< INTSCN_LOTEMP_SEL Mask */ 202 203 #define MXC_F_SMON_INTSCN_VTM_LOTHSEL_POS 18 /**< INTSCN_VTM_LOTHSEL Position */ 204 #define MXC_F_SMON_INTSCN_VTM_LOTHSEL ((uint32_t)(0x3UL << MXC_F_SMON_INTSCN_VTM_LOTHSEL_POS)) /**< INTSCN_VTM_LOTHSEL Mask */ 205 #define MXC_V_SMON_INTSCN_VTM_LOTHSEL_1_6V ((uint32_t)0x0UL) /**< INTSCN_VTM_LOTHSEL_1_6V Value */ 206 #define MXC_S_SMON_INTSCN_VTM_LOTHSEL_1_6V (MXC_V_SMON_INTSCN_VTM_LOTHSEL_1_6V << MXC_F_SMON_INTSCN_VTM_LOTHSEL_POS) /**< INTSCN_VTM_LOTHSEL_1_6V Setting */ 207 #define MXC_V_SMON_INTSCN_VTM_LOTHSEL_2_2V ((uint32_t)0x1UL) /**< INTSCN_VTM_LOTHSEL_2_2V Value */ 208 #define MXC_S_SMON_INTSCN_VTM_LOTHSEL_2_2V (MXC_V_SMON_INTSCN_VTM_LOTHSEL_2_2V << MXC_F_SMON_INTSCN_VTM_LOTHSEL_POS) /**< INTSCN_VTM_LOTHSEL_2_2V Setting */ 209 #define MXC_V_SMON_INTSCN_VTM_LOTHSEL_2_8V ((uint32_t)0x2UL) /**< INTSCN_VTM_LOTHSEL_2_8V Value */ 210 #define MXC_S_SMON_INTSCN_VTM_LOTHSEL_2_8V (MXC_V_SMON_INTSCN_VTM_LOTHSEL_2_8V << MXC_F_SMON_INTSCN_VTM_LOTHSEL_POS) /**< INTSCN_VTM_LOTHSEL_2_8V Setting */ 211 212 #define MXC_F_SMON_INTSCN_LOCK_POS 31 /**< INTSCN_LOCK Position */ 213 #define MXC_F_SMON_INTSCN_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_LOCK_POS)) /**< INTSCN_LOCK Mask */ 214 215 /**@} end of group SMON_INTSCN_Register */ 216 217 /** 218 * @ingroup smon_registers 219 * @defgroup SMON_SECALM SMON_SECALM 220 * @brief Security Alarm Register. 221 * @{ 222 */ 223 #define MXC_F_SMON_SECALM_DRS_POS 0 /**< SECALM_DRS Position */ 224 #define MXC_F_SMON_SECALM_DRS ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_DRS_POS)) /**< SECALM_DRS Mask */ 225 226 #define MXC_F_SMON_SECALM_KEYWIPE_POS 1 /**< SECALM_KEYWIPE Position */ 227 #define MXC_F_SMON_SECALM_KEYWIPE ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_KEYWIPE_POS)) /**< SECALM_KEYWIPE Mask */ 228 229 #define MXC_F_SMON_SECALM_SHIELDF_POS 2 /**< SECALM_SHIELDF Position */ 230 #define MXC_F_SMON_SECALM_SHIELDF ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_SHIELDF_POS)) /**< SECALM_SHIELDF Mask */ 231 232 #define MXC_F_SMON_SECALM_LOTEMP_POS 3 /**< SECALM_LOTEMP Position */ 233 #define MXC_F_SMON_SECALM_LOTEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_LOTEMP_POS)) /**< SECALM_LOTEMP Mask */ 234 235 #define MXC_F_SMON_SECALM_HITEMP_POS 4 /**< SECALM_HITEMP Position */ 236 #define MXC_F_SMON_SECALM_HITEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_HITEMP_POS)) /**< SECALM_HITEMP Mask */ 237 238 #define MXC_F_SMON_SECALM_BATLO_POS 5 /**< SECALM_BATLO Position */ 239 #define MXC_F_SMON_SECALM_BATLO ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_BATLO_POS)) /**< SECALM_BATLO Mask */ 240 241 #define MXC_F_SMON_SECALM_BATHI_POS 6 /**< SECALM_BATHI Position */ 242 #define MXC_F_SMON_SECALM_BATHI ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_BATHI_POS)) /**< SECALM_BATHI Mask */ 243 244 #define MXC_F_SMON_SECALM_EXTF_POS 7 /**< SECALM_EXTF Position */ 245 #define MXC_F_SMON_SECALM_EXTF ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTF_POS)) /**< SECALM_EXTF Mask */ 246 247 #define MXC_F_SMON_SECALM_DFD_POS 8 /**< SECALM_DFD Position */ 248 #define MXC_F_SMON_SECALM_DFD ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_DFD_POS)) /**< SECALM_DFD Mask */ 249 250 #define MXC_F_SMON_SECALM_VMAINPF_POS 9 /**< SECALM_VMAINPF Position */ 251 #define MXC_F_SMON_SECALM_VMAINPF ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VMAINPF_POS)) /**< SECALM_VMAINPF Mask */ 252 253 #define MXC_F_SMON_SECALM_EXTSTAT0_POS 16 /**< SECALM_EXTSTAT0 Position */ 254 #define MXC_F_SMON_SECALM_EXTSTAT0 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT0_POS)) /**< SECALM_EXTSTAT0 Mask */ 255 256 #define MXC_F_SMON_SECALM_EXTSTAT1_POS 17 /**< SECALM_EXTSTAT1 Position */ 257 #define MXC_F_SMON_SECALM_EXTSTAT1 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT1_POS)) /**< SECALM_EXTSTAT1 Mask */ 258 259 #define MXC_F_SMON_SECALM_EXTSTAT2_POS 18 /**< SECALM_EXTSTAT2 Position */ 260 #define MXC_F_SMON_SECALM_EXTSTAT2 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT2_POS)) /**< SECALM_EXTSTAT2 Mask */ 261 262 #define MXC_F_SMON_SECALM_EXTSTAT3_POS 19 /**< SECALM_EXTSTAT3 Position */ 263 #define MXC_F_SMON_SECALM_EXTSTAT3 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT3_POS)) /**< SECALM_EXTSTAT3 Mask */ 264 265 #define MXC_F_SMON_SECALM_EXTSTAT4_POS 20 /**< SECALM_EXTSTAT4 Position */ 266 #define MXC_F_SMON_SECALM_EXTSTAT4 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT4_POS)) /**< SECALM_EXTSTAT4 Mask */ 267 268 #define MXC_F_SMON_SECALM_EXTSTAT5_POS 21 /**< SECALM_EXTSTAT5 Position */ 269 #define MXC_F_SMON_SECALM_EXTSTAT5 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT5_POS)) /**< SECALM_EXTSTAT5 Mask */ 270 271 #define MXC_F_SMON_SECALM_EXTSWARN0_POS 24 /**< SECALM_EXTSWARN0 Position */ 272 #define MXC_F_SMON_SECALM_EXTSWARN0 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN0_POS)) /**< SECALM_EXTSWARN0 Mask */ 273 274 #define MXC_F_SMON_SECALM_EXTSWARN1_POS 25 /**< SECALM_EXTSWARN1 Position */ 275 #define MXC_F_SMON_SECALM_EXTSWARN1 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN1_POS)) /**< SECALM_EXTSWARN1 Mask */ 276 277 #define MXC_F_SMON_SECALM_EXTSWARN2_POS 26 /**< SECALM_EXTSWARN2 Position */ 278 #define MXC_F_SMON_SECALM_EXTSWARN2 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN2_POS)) /**< SECALM_EXTSWARN2 Mask */ 279 280 #define MXC_F_SMON_SECALM_EXTSWARN3_POS 27 /**< SECALM_EXTSWARN3 Position */ 281 #define MXC_F_SMON_SECALM_EXTSWARN3 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN3_POS)) /**< SECALM_EXTSWARN3 Mask */ 282 283 #define MXC_F_SMON_SECALM_EXTSWARN4_POS 28 /**< SECALM_EXTSWARN4 Position */ 284 #define MXC_F_SMON_SECALM_EXTSWARN4 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN4_POS)) /**< SECALM_EXTSWARN4 Mask */ 285 286 #define MXC_F_SMON_SECALM_EXTSWARN5_POS 29 /**< SECALM_EXTSWARN5 Position */ 287 #define MXC_F_SMON_SECALM_EXTSWARN5 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN5_POS)) /**< SECALM_EXTSWARN5 Mask */ 288 289 /**@} end of group SMON_SECALM_Register */ 290 291 /** 292 * @ingroup smon_registers 293 * @defgroup SMON_SECDIAG SMON_SECDIAG 294 * @brief Security Diagnostic Register. 295 * @{ 296 */ 297 #define MXC_F_SMON_SECDIAG_PORF_POS 0 /**< SECDIAG_PORF Position */ 298 #define MXC_F_SMON_SECDIAG_PORF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_PORF_POS)) /**< SECDIAG_PORF Mask */ 299 300 #define MXC_F_SMON_SECDIAG_SHIELDF_POS 2 /**< SECDIAG_SHIELDF Position */ 301 #define MXC_F_SMON_SECDIAG_SHIELDF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_SHIELDF_POS)) /**< SECDIAG_SHIELDF Mask */ 302 303 #define MXC_F_SMON_SECDIAG_LOTEMP_POS 3 /**< SECDIAG_LOTEMP Position */ 304 #define MXC_F_SMON_SECDIAG_LOTEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_LOTEMP_POS)) /**< SECDIAG_LOTEMP Mask */ 305 306 #define MXC_F_SMON_SECDIAG_HITEMP_POS 4 /**< SECDIAG_HITEMP Position */ 307 #define MXC_F_SMON_SECDIAG_HITEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_HITEMP_POS)) /**< SECDIAG_HITEMP Mask */ 308 309 #define MXC_F_SMON_SECDIAG_BATLO_POS 5 /**< SECDIAG_BATLO Position */ 310 #define MXC_F_SMON_SECDIAG_BATLO ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BATLO_POS)) /**< SECDIAG_BATLO Mask */ 311 312 #define MXC_F_SMON_SECDIAG_BATHI_POS 6 /**< SECDIAG_BATHI Position */ 313 #define MXC_F_SMON_SECDIAG_BATHI ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BATHI_POS)) /**< SECDIAG_BATHI Mask */ 314 315 #define MXC_F_SMON_SECDIAG_DYNF_POS 7 /**< SECDIAG_DYNF Position */ 316 #define MXC_F_SMON_SECDIAG_DYNF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_DYNF_POS)) /**< SECDIAG_DYNF Mask */ 317 318 #define MXC_F_SMON_SECDIAG_AESK_MDU_POS 9 /**< SECDIAG_AESK_MDU Position */ 319 #define MXC_F_SMON_SECDIAG_AESK_MDU ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_AESK_MDU_POS)) /**< SECDIAG_AESK_MDU Mask */ 320 321 #define MXC_F_SMON_SECDIAG_AESK_NVSRAM_POS 10 /**< SECDIAG_AESK_NVSRAM Position */ 322 #define MXC_F_SMON_SECDIAG_AESK_NVSRAM ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_AESK_NVSRAM_POS)) /**< SECDIAG_AESK_NVSRAM Mask */ 323 324 #define MXC_F_SMON_SECDIAG_AESK_SPIXF_POS 11 /**< SECDIAG_AESK_SPIXF Position */ 325 #define MXC_F_SMON_SECDIAG_AESK_SPIXF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_AESK_SPIXF_POS)) /**< SECDIAG_AESK_SPIXF Mask */ 326 327 #define MXC_F_SMON_SECDIAG_AESK_SPIXR_POS 12 /**< SECDIAG_AESK_SPIXR Position */ 328 #define MXC_F_SMON_SECDIAG_AESK_SPIXR ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_AESK_SPIXR_POS)) /**< SECDIAG_AESK_SPIXR Mask */ 329 330 #define MXC_F_SMON_SECDIAG_EXTSTAT0_POS 16 /**< SECDIAG_EXTSTAT0 Position */ 331 #define MXC_F_SMON_SECDIAG_EXTSTAT0 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT0_POS)) /**< SECDIAG_EXTSTAT0 Mask */ 332 333 #define MXC_F_SMON_SECDIAG_EXTSTAT1_POS 17 /**< SECDIAG_EXTSTAT1 Position */ 334 #define MXC_F_SMON_SECDIAG_EXTSTAT1 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT1_POS)) /**< SECDIAG_EXTSTAT1 Mask */ 335 336 #define MXC_F_SMON_SECDIAG_EXTSTAT2_POS 18 /**< SECDIAG_EXTSTAT2 Position */ 337 #define MXC_F_SMON_SECDIAG_EXTSTAT2 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT2_POS)) /**< SECDIAG_EXTSTAT2 Mask */ 338 339 #define MXC_F_SMON_SECDIAG_EXTSTAT3_POS 19 /**< SECDIAG_EXTSTAT3 Position */ 340 #define MXC_F_SMON_SECDIAG_EXTSTAT3 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT3_POS)) /**< SECDIAG_EXTSTAT3 Mask */ 341 342 #define MXC_F_SMON_SECDIAG_EXTSTAT4_POS 20 /**< SECDIAG_EXTSTAT4 Position */ 343 #define MXC_F_SMON_SECDIAG_EXTSTAT4 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT4_POS)) /**< SECDIAG_EXTSTAT4 Mask */ 344 345 #define MXC_F_SMON_SECDIAG_EXTSTAT5_POS 21 /**< SECDIAG_EXTSTAT5 Position */ 346 #define MXC_F_SMON_SECDIAG_EXTSTAT5 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT5_POS)) /**< SECDIAG_EXTSTAT5 Mask */ 347 348 /**@} end of group SMON_SECDIAG_Register */ 349 350 /** 351 * @ingroup smon_registers 352 * @defgroup SMON_DLRTC SMON_DLRTC 353 * @brief DRS Log RTC Value. This register contains the 32 bit value in the RTC second 354 * register when the last DRS event occurred. 355 * @{ 356 */ 357 #define MXC_F_SMON_DLRTC_DLRTC_POS 0 /**< DLRTC_DLRTC Position */ 358 #define MXC_F_SMON_DLRTC_DLRTC ((uint32_t)(0xFFFFFFFFUL << MXC_F_SMON_DLRTC_DLRTC_POS)) /**< DLRTC_DLRTC Mask */ 359 360 /**@} end of group SMON_DLRTC_Register */ 361 362 /** 363 * @ingroup smon_registers 364 * @defgroup SMON_MEUCFG SMON_MEUCFG 365 * @brief MEU Configuration 366 * @{ 367 */ 368 #define MXC_F_SMON_MEUCFG_ENC_REG0_POS 0 /**< MEUCFG_ENC_REG0 Position */ 369 #define MXC_F_SMON_MEUCFG_ENC_REG0 ((uint32_t)(0x1UL << MXC_F_SMON_MEUCFG_ENC_REG0_POS)) /**< MEUCFG_ENC_REG0 Mask */ 370 371 #define MXC_F_SMON_MEUCFG_ENC_REG1_POS 1 /**< MEUCFG_ENC_REG1 Position */ 372 #define MXC_F_SMON_MEUCFG_ENC_REG1 ((uint32_t)(0x1UL << MXC_F_SMON_MEUCFG_ENC_REG1_POS)) /**< MEUCFG_ENC_REG1 Mask */ 373 374 #define MXC_F_SMON_MEUCFG_ENC_REG2_POS 2 /**< MEUCFG_ENC_REG2 Position */ 375 #define MXC_F_SMON_MEUCFG_ENC_REG2 ((uint32_t)(0x1UL << MXC_F_SMON_MEUCFG_ENC_REG2_POS)) /**< MEUCFG_ENC_REG2 Mask */ 376 377 #define MXC_F_SMON_MEUCFG_ENC_REG3_POS 3 /**< MEUCFG_ENC_REG3 Position */ 378 #define MXC_F_SMON_MEUCFG_ENC_REG3 ((uint32_t)(0x1UL << MXC_F_SMON_MEUCFG_ENC_REG3_POS)) /**< MEUCFG_ENC_REG3 Mask */ 379 380 #define MXC_F_SMON_MEUCFG_ENC_REG4_POS 4 /**< MEUCFG_ENC_REG4 Position */ 381 #define MXC_F_SMON_MEUCFG_ENC_REG4 ((uint32_t)(0x1UL << MXC_F_SMON_MEUCFG_ENC_REG4_POS)) /**< MEUCFG_ENC_REG4 Mask */ 382 383 #define MXC_F_SMON_MEUCFG_ENC_REG5_POS 5 /**< MEUCFG_ENC_REG5 Position */ 384 #define MXC_F_SMON_MEUCFG_ENC_REG5 ((uint32_t)(0x1UL << MXC_F_SMON_MEUCFG_ENC_REG5_POS)) /**< MEUCFG_ENC_REG5 Mask */ 385 386 #define MXC_F_SMON_MEUCFG_ENC_REG6_POS 6 /**< MEUCFG_ENC_REG6 Position */ 387 #define MXC_F_SMON_MEUCFG_ENC_REG6 ((uint32_t)(0x1UL << MXC_F_SMON_MEUCFG_ENC_REG6_POS)) /**< MEUCFG_ENC_REG6 Mask */ 388 389 #define MXC_F_SMON_MEUCFG_ENC_REG7_POS 7 /**< MEUCFG_ENC_REG7 Position */ 390 #define MXC_F_SMON_MEUCFG_ENC_REG7 ((uint32_t)(0x1UL << MXC_F_SMON_MEUCFG_ENC_REG7_POS)) /**< MEUCFG_ENC_REG7 Mask */ 391 392 #define MXC_F_SMON_MEUCFG_LOCK_POS 31 /**< MEUCFG_LOCK Position */ 393 #define MXC_F_SMON_MEUCFG_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_MEUCFG_LOCK_POS)) /**< MEUCFG_LOCK Mask */ 394 395 /**@} end of group SMON_MEUCFG_Register */ 396 397 /** 398 * @ingroup smon_registers 399 * @defgroup SMON_SECST SMON_SECST 400 * @brief Security Monitor Status Register. 401 * @{ 402 */ 403 #define MXC_F_SMON_SECST_EXTSRS_POS 0 /**< SECST_EXTSRS Position */ 404 #define MXC_F_SMON_SECST_EXTSRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_EXTSRS_POS)) /**< SECST_EXTSRS Mask */ 405 406 #define MXC_F_SMON_SECST_INTSRS_POS 1 /**< SECST_INTSRS Position */ 407 #define MXC_F_SMON_SECST_INTSRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_INTSRS_POS)) /**< SECST_INTSRS Mask */ 408 409 #define MXC_F_SMON_SECST_SECALRS_POS 2 /**< SECST_SECALRS Position */ 410 #define MXC_F_SMON_SECST_SECALRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_SECALRS_POS)) /**< SECST_SECALRS Mask */ 411 412 #define MXC_F_SMON_SECST_MEUCFG_POS 4 /**< SECST_MEUCFG Position */ 413 #define MXC_F_SMON_SECST_MEUCFG ((uint32_t)(0x1UL << MXC_F_SMON_SECST_MEUCFG_POS)) /**< SECST_MEUCFG Mask */ 414 415 /**@} end of group SMON_SECST_Register */ 416 417 /** 418 * @ingroup smon_registers 419 * @defgroup SMON_SDBE SMON_SDBE 420 * @brief Security Monitor Self Destruct Byte. 421 * @{ 422 */ 423 #define MXC_F_SMON_SDBE_DBYTE_POS 0 /**< SDBE_DBYTE Position */ 424 #define MXC_F_SMON_SDBE_DBYTE ((uint32_t)(0xFFUL << MXC_F_SMON_SDBE_DBYTE_POS)) /**< SDBE_DBYTE Mask */ 425 426 #define MXC_F_SMON_SDBE_SBDEN_POS 31 /**< SDBE_SBDEN Position */ 427 #define MXC_F_SMON_SDBE_SBDEN ((uint32_t)(0x1UL << MXC_F_SMON_SDBE_SBDEN_POS)) /**< SDBE_SBDEN Mask */ 428 429 /**@} end of group SMON_SDBE_Register */ 430 431 #ifdef __cplusplus 432 } 433 #endif 434 435 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SMON_REGS_H_ 436
