1 /** 2 * @file skbd_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SKBD Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SKBD_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SKBD_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup skbd 66 * @defgroup skbd_registers SKBD_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the SKBD Peripheral Module. 68 * @details Secure Keyboard 69 */ 70 71 /** 72 * @ingroup skbd_registers 73 * Structure type to access the SKBD Registers. 74 */ 75 typedef struct { 76 __IO uint32_t cr0; /**< <tt>\b 0x00:</tt> SKBD CR0 Register */ 77 __IO uint32_t cr1; /**< <tt>\b 0x04:</tt> SKBD CR1 Register */ 78 __I uint32_t sr; /**< <tt>\b 0x08:</tt> SKBD SR Register */ 79 __IO uint32_t ier; /**< <tt>\b 0x0C:</tt> SKBD IER Register */ 80 __IO uint32_t isr; /**< <tt>\b 0x10:</tt> SKBD ISR Register */ 81 __I uint32_t event[4]; /**< <tt>\b 0x14:</tt> SKBD EVENT Register */ 82 } mxc_skbd_regs_t; 83 84 /* Register offsets for module SKBD */ 85 /** 86 * @ingroup skbd_registers 87 * @defgroup SKBD_Register_Offsets Register Offsets 88 * @brief SKBD Peripheral Register Offsets from the SKBD Base Peripheral Address. 89 * @{ 90 */ 91 #define MXC_R_SKBD_CR0 ((uint32_t)0x00000000UL) /**< Offset from SKBD Base Address: <tt> 0x0000</tt> */ 92 #define MXC_R_SKBD_CR1 ((uint32_t)0x00000004UL) /**< Offset from SKBD Base Address: <tt> 0x0004</tt> */ 93 #define MXC_R_SKBD_SR ((uint32_t)0x00000008UL) /**< Offset from SKBD Base Address: <tt> 0x0008</tt> */ 94 #define MXC_R_SKBD_IER ((uint32_t)0x0000000CUL) /**< Offset from SKBD Base Address: <tt> 0x000C</tt> */ 95 #define MXC_R_SKBD_ISR ((uint32_t)0x00000010UL) /**< Offset from SKBD Base Address: <tt> 0x0010</tt> */ 96 #define MXC_R_SKBD_EVENT ((uint32_t)0x00000014UL) /**< Offset from SKBD Base Address: <tt> 0x0014</tt> */ 97 /**@} end of group skbd_registers */ 98 99 /** 100 * @ingroup skbd_registers 101 * @defgroup SKBD_CR0 SKBD_CR0 102 * @brief Input Output Select Bits. Each bit of IOSEL selects the pin direction for the 103 * corresponding KBDIO pin. If IOSEL[0] = 1, KBDIO0 is an output. 104 * @{ 105 */ 106 #define MXC_F_SKBD_CR0_KBDIO_0_POS 0 /**< CR0_KBDIO_0 Position */ 107 #define MXC_F_SKBD_CR0_KBDIO_0 ((uint32_t)(0x3FFUL << MXC_F_SKBD_CR0_KBDIO_0_POS)) /**< CR0_KBDIO_0 Mask */ 108 #define MXC_V_SKBD_CR0_KBDIO_0_INPUT ((uint32_t)0x0UL) /**< CR0_KBDIO_0_INPUT Value */ 109 #define MXC_S_SKBD_CR0_KBDIO_0_INPUT (MXC_V_SKBD_CR0_KBDIO_0_INPUT << MXC_F_SKBD_CR0_KBDIO_0_POS) /**< CR0_KBDIO_0_INPUT Setting */ 110 #define MXC_V_SKBD_CR0_KBDIO_0_OUTPUT ((uint32_t)0x1UL) /**< CR0_KBDIO_0_OUTPUT Value */ 111 #define MXC_S_SKBD_CR0_KBDIO_0_OUTPUT (MXC_V_SKBD_CR0_KBDIO_0_OUTPUT << MXC_F_SKBD_CR0_KBDIO_0_POS) /**< CR0_KBDIO_0_OUTPUT Setting */ 112 113 /**@} end of group SKBD_CR0_Register */ 114 115 /** 116 * @ingroup skbd_registers 117 * @defgroup SKBD_CR1 SKBD_CR1 118 * @brief Control Register 1 119 * @{ 120 */ 121 #define MXC_F_SKBD_CR1_AUTOEN_POS 0 /**< CR1_AUTOEN Position */ 122 #define MXC_F_SKBD_CR1_AUTOEN ((uint32_t)(0x1UL << MXC_F_SKBD_CR1_AUTOEN_POS)) /**< CR1_AUTOEN Mask */ 123 124 #define MXC_F_SKBD_CR1_CLEAR_POS 1 /**< CR1_CLEAR Position */ 125 #define MXC_F_SKBD_CR1_CLEAR ((uint32_t)(0x1UL << MXC_F_SKBD_CR1_CLEAR_POS)) /**< CR1_CLEAR Mask */ 126 127 #define MXC_F_SKBD_CR1_OUTNB_POS 8 /**< CR1_OUTNB Position */ 128 #define MXC_F_SKBD_CR1_OUTNB ((uint32_t)(0x7UL << MXC_F_SKBD_CR1_OUTNB_POS)) /**< CR1_OUTNB Mask */ 129 130 #define MXC_F_SKBD_CR1_DBTM_POS 13 /**< CR1_DBTM Position */ 131 #define MXC_F_SKBD_CR1_DBTM ((uint32_t)(0x7UL << MXC_F_SKBD_CR1_DBTM_POS)) /**< CR1_DBTM Mask */ 132 #define MXC_V_SKBD_CR1_DBTM_TIME4MS ((uint32_t)0x0UL) /**< CR1_DBTM_TIME4MS Value */ 133 #define MXC_S_SKBD_CR1_DBTM_TIME4MS (MXC_V_SKBD_CR1_DBTM_TIME4MS << MXC_F_SKBD_CR1_DBTM_POS) /**< CR1_DBTM_TIME4MS Setting */ 134 #define MXC_V_SKBD_CR1_DBTM_TIME5MS ((uint32_t)0x1UL) /**< CR1_DBTM_TIME5MS Value */ 135 #define MXC_S_SKBD_CR1_DBTM_TIME5MS (MXC_V_SKBD_CR1_DBTM_TIME5MS << MXC_F_SKBD_CR1_DBTM_POS) /**< CR1_DBTM_TIME5MS Setting */ 136 #define MXC_V_SKBD_CR1_DBTM_TIME6MS ((uint32_t)0x2UL) /**< CR1_DBTM_TIME6MS Value */ 137 #define MXC_S_SKBD_CR1_DBTM_TIME6MS (MXC_V_SKBD_CR1_DBTM_TIME6MS << MXC_F_SKBD_CR1_DBTM_POS) /**< CR1_DBTM_TIME6MS Setting */ 138 #define MXC_V_SKBD_CR1_DBTM_TIME7MS ((uint32_t)0x3UL) /**< CR1_DBTM_TIME7MS Value */ 139 #define MXC_S_SKBD_CR1_DBTM_TIME7MS (MXC_V_SKBD_CR1_DBTM_TIME7MS << MXC_F_SKBD_CR1_DBTM_POS) /**< CR1_DBTM_TIME7MS Setting */ 140 #define MXC_V_SKBD_CR1_DBTM_TIME8MS ((uint32_t)0x4UL) /**< CR1_DBTM_TIME8MS Value */ 141 #define MXC_S_SKBD_CR1_DBTM_TIME8MS (MXC_V_SKBD_CR1_DBTM_TIME8MS << MXC_F_SKBD_CR1_DBTM_POS) /**< CR1_DBTM_TIME8MS Setting */ 142 #define MXC_V_SKBD_CR1_DBTM_TIME10MS ((uint32_t)0x5UL) /**< CR1_DBTM_TIME10MS Value */ 143 #define MXC_S_SKBD_CR1_DBTM_TIME10MS (MXC_V_SKBD_CR1_DBTM_TIME10MS << MXC_F_SKBD_CR1_DBTM_POS) /**< CR1_DBTM_TIME10MS Setting */ 144 #define MXC_V_SKBD_CR1_DBTM_TIME11MS ((uint32_t)0x6UL) /**< CR1_DBTM_TIME11MS Value */ 145 #define MXC_S_SKBD_CR1_DBTM_TIME11MS (MXC_V_SKBD_CR1_DBTM_TIME11MS << MXC_F_SKBD_CR1_DBTM_POS) /**< CR1_DBTM_TIME11MS Setting */ 146 #define MXC_V_SKBD_CR1_DBTM_TIME12MS ((uint32_t)0x7UL) /**< CR1_DBTM_TIME12MS Value */ 147 #define MXC_S_SKBD_CR1_DBTM_TIME12MS (MXC_V_SKBD_CR1_DBTM_TIME12MS << MXC_F_SKBD_CR1_DBTM_POS) /**< CR1_DBTM_TIME12MS Setting */ 148 149 /**@} end of group SKBD_CR1_Register */ 150 151 /** 152 * @ingroup skbd_registers 153 * @defgroup SKBD_SR SKBD_SR 154 * @brief Status Register 155 * @{ 156 */ 157 #define MXC_F_SKBD_SR_BUSY_POS 0 /**< SR_BUSY Position */ 158 #define MXC_F_SKBD_SR_BUSY ((uint32_t)(0x1UL << MXC_F_SKBD_SR_BUSY_POS)) /**< SR_BUSY Mask */ 159 160 /**@} end of group SKBD_SR_Register */ 161 162 /** 163 * @ingroup skbd_registers 164 * @defgroup SKBD_IER SKBD_IER 165 * @brief Interrupt Enable Register 166 * @{ 167 */ 168 #define MXC_F_SKBD_IER_PUSHIE_POS 0 /**< IER_PUSHIE Position */ 169 #define MXC_F_SKBD_IER_PUSHIE ((uint32_t)(0x1UL << MXC_F_SKBD_IER_PUSHIE_POS)) /**< IER_PUSHIE Mask */ 170 171 #define MXC_F_SKBD_IER_RELEASEIE_POS 1 /**< IER_RELEASEIE Position */ 172 #define MXC_F_SKBD_IER_RELEASEIE ((uint32_t)(0x1UL << MXC_F_SKBD_IER_RELEASEIE_POS)) /**< IER_RELEASEIE Mask */ 173 174 #define MXC_F_SKBD_IER_OVERIE_POS 2 /**< IER_OVERIE Position */ 175 #define MXC_F_SKBD_IER_OVERIE ((uint32_t)(0x1UL << MXC_F_SKBD_IER_OVERIE_POS)) /**< IER_OVERIE Mask */ 176 177 /**@} end of group SKBD_IER_Register */ 178 179 /** 180 * @ingroup skbd_registers 181 * @defgroup SKBD_ISR SKBD_ISR 182 * @brief Interrupt Status Register 183 * @{ 184 */ 185 #define MXC_F_SKBD_ISR_PUSHIS_POS 0 /**< ISR_PUSHIS Position */ 186 #define MXC_F_SKBD_ISR_PUSHIS ((uint32_t)(0x1UL << MXC_F_SKBD_ISR_PUSHIS_POS)) /**< ISR_PUSHIS Mask */ 187 188 #define MXC_F_SKBD_ISR_RELEASEIS_POS 1 /**< ISR_RELEASEIS Position */ 189 #define MXC_F_SKBD_ISR_RELEASEIS ((uint32_t)(0x1UL << MXC_F_SKBD_ISR_RELEASEIS_POS)) /**< ISR_RELEASEIS Mask */ 190 191 #define MXC_F_SKBD_ISR_OVERIS_POS 2 /**< ISR_OVERIS Position */ 192 #define MXC_F_SKBD_ISR_OVERIS ((uint32_t)(0x1UL << MXC_F_SKBD_ISR_OVERIS_POS)) /**< ISR_OVERIS Mask */ 193 194 /**@} end of group SKBD_ISR_Register */ 195 196 /** 197 * @ingroup skbd_registers 198 * @defgroup SKBD_EVENT SKBD_EVENT 199 * @brief Key Register 200 * @{ 201 */ 202 #define MXC_F_SKBD_EVENT_IOIN_POS 0 /**< EVENT_IOIN Position */ 203 #define MXC_F_SKBD_EVENT_IOIN ((uint32_t)(0x7UL << MXC_F_SKBD_EVENT_IOIN_POS)) /**< EVENT_IOIN Mask */ 204 205 #define MXC_F_SKBD_EVENT_IOOUT_POS 5 /**< EVENT_IOOUT Position */ 206 #define MXC_F_SKBD_EVENT_IOOUT ((uint32_t)(0x7UL << MXC_F_SKBD_EVENT_IOOUT_POS)) /**< EVENT_IOOUT Mask */ 207 208 #define MXC_F_SKBD_EVENT_PUSH_POS 10 /**< EVENT_PUSH Position */ 209 #define MXC_F_SKBD_EVENT_PUSH ((uint32_t)(0x1UL << MXC_F_SKBD_EVENT_PUSH_POS)) /**< EVENT_PUSH Mask */ 210 211 #define MXC_F_SKBD_EVENT_READ_POS 11 /**< EVENT_READ Position */ 212 #define MXC_F_SKBD_EVENT_READ ((uint32_t)(0x1UL << MXC_F_SKBD_EVENT_READ_POS)) /**< EVENT_READ Mask */ 213 214 #define MXC_F_SKBD_EVENT_NEXT_POS 12 /**< EVENT_NEXT Position */ 215 #define MXC_F_SKBD_EVENT_NEXT ((uint32_t)(0x1UL << MXC_F_SKBD_EVENT_NEXT_POS)) /**< EVENT_NEXT Mask */ 216 217 /**@} end of group SKBD_EVENT_Register */ 218 219 #ifdef __cplusplus 220 } 221 #endif 222 223 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SKBD_REGS_H_ 224
