1 /** 2 * @file sir_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SIR_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SIR_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup sir 66 * @defgroup sir_registers SIR_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. 68 * @details System Initialization Registers. 69 */ 70 71 /** 72 * @ingroup sir_registers 73 * Structure type to access the SIR Registers. 74 */ 75 typedef struct { 76 __I uint32_t sistat; /**< <tt>\b 0x00:</tt> SIR SISTAT Register */ 77 __I uint32_t erraddr; /**< <tt>\b 0x04:</tt> SIR ERRADDR Register */ 78 __R uint32_t rsv_0x8_0xff[62]; 79 __I uint32_t fstat; /**< <tt>\b 0x100:</tt> SIR FSTAT Register */ 80 __I uint32_t sfstat; /**< <tt>\b 0x104:</tt> SIR SFSTAT Register */ 81 } mxc_sir_regs_t; 82 83 /* Register offsets for module SIR */ 84 /** 85 * @ingroup sir_registers 86 * @defgroup SIR_Register_Offsets Register Offsets 87 * @brief SIR Peripheral Register Offsets from the SIR Base Peripheral Address. 88 * @{ 89 */ 90 #define MXC_R_SIR_SISTAT ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: <tt> 0x0000</tt> */ 91 #define MXC_R_SIR_ERRADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: <tt> 0x0004</tt> */ 92 #define MXC_R_SIR_FSTAT ((uint32_t)0x00000100UL) /**< Offset from SIR Base Address: <tt> 0x0100</tt> */ 93 #define MXC_R_SIR_SFSTAT ((uint32_t)0x00000104UL) /**< Offset from SIR Base Address: <tt> 0x0104</tt> */ 94 /**@} end of group sir_registers */ 95 96 /** 97 * @ingroup sir_registers 98 * @defgroup SIR_SISTAT SIR_SISTAT 99 * @brief System Initialization Status Register. 100 * @{ 101 */ 102 #define MXC_F_SIR_SISTAT_MAGIC_POS 0 /**< SISTAT_MAGIC Position */ 103 #define MXC_F_SIR_SISTAT_MAGIC ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_MAGIC_POS)) /**< SISTAT_MAGIC Mask */ 104 105 #define MXC_F_SIR_SISTAT_CRCERR_POS 1 /**< SISTAT_CRCERR Position */ 106 #define MXC_F_SIR_SISTAT_CRCERR ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_CRCERR_POS)) /**< SISTAT_CRCERR Mask */ 107 108 /**@} end of group SIR_SISTAT_Register */ 109 110 /** 111 * @ingroup sir_registers 112 * @defgroup SIR_ERRADDR SIR_ERRADDR 113 * @brief Read-only field set by the SIB block if a CRC error occurs during the read of 114 * the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 115 * 1). 116 * @{ 117 */ 118 #define MXC_F_SIR_ERRADDR_ERRADDR_POS 0 /**< ERRADDR_ERRADDR Position */ 119 #define MXC_F_SIR_ERRADDR_ERRADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_ERRADDR_ERRADDR_POS)) /**< ERRADDR_ERRADDR Mask */ 120 121 /**@} end of group SIR_ERRADDR_Register */ 122 123 /** 124 * @ingroup sir_registers 125 * @defgroup SIR_FSTAT SIR_FSTAT 126 * @brief funcstat register. 127 * @{ 128 */ 129 #define MXC_F_SIR_FSTAT_FPU_POS 0 /**< FSTAT_FPU Position */ 130 #define MXC_F_SIR_FSTAT_FPU ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_FPU_POS)) /**< FSTAT_FPU Mask */ 131 132 #define MXC_F_SIR_FSTAT_USB_POS 1 /**< FSTAT_USB Position */ 133 #define MXC_F_SIR_FSTAT_USB ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_USB_POS)) /**< FSTAT_USB Mask */ 134 135 #define MXC_F_SIR_FSTAT_ADC_POS 2 /**< FSTAT_ADC Position */ 136 #define MXC_F_SIR_FSTAT_ADC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_ADC_POS)) /**< FSTAT_ADC Mask */ 137 138 #define MXC_F_SIR_FSTAT_XIP_POS 3 /**< FSTAT_XIP Position */ 139 #define MXC_F_SIR_FSTAT_XIP ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_XIP_POS)) /**< FSTAT_XIP Mask */ 140 141 #define MXC_F_SIR_FSTAT_SDHC_POS 6 /**< FSTAT_SDHC Position */ 142 #define MXC_F_SIR_FSTAT_SDHC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SDHC_POS)) /**< FSTAT_SDHC Mask */ 143 144 #define MXC_F_SIR_FSTAT_SMPHR_POS 7 /**< FSTAT_SMPHR Position */ 145 #define MXC_F_SIR_FSTAT_SMPHR ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SMPHR_POS)) /**< FSTAT_SMPHR Mask */ 146 147 #define MXC_F_SIR_FSTAT_SRCC_POS 8 /**< FSTAT_SRCC Position */ 148 #define MXC_F_SIR_FSTAT_SRCC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SRCC_POS)) /**< FSTAT_SRCC Mask */ 149 150 #define MXC_F_SIR_FSTAT_ADC9_POS 9 /**< FSTAT_ADC9 Position */ 151 #define MXC_F_SIR_FSTAT_ADC9 ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_ADC9_POS)) /**< FSTAT_ADC9 Mask */ 152 153 #define MXC_F_SIR_FSTAT_SC_POS 10 /**< FSTAT_SC Position */ 154 #define MXC_F_SIR_FSTAT_SC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SC_POS)) /**< FSTAT_SC Mask */ 155 156 #define MXC_F_SIR_FSTAT_NMI_POS 12 /**< FSTAT_NMI Position */ 157 #define MXC_F_SIR_FSTAT_NMI ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_NMI_POS)) /**< FSTAT_NMI Mask */ 158 159 /**@} end of group SIR_FSTAT_Register */ 160 161 /** 162 * @ingroup sir_registers 163 * @defgroup SIR_SFSTAT SIR_SFSTAT 164 * @brief secfuncstat register. 165 * @{ 166 */ 167 #define MXC_F_SIR_SFSTAT_SBD_POS 0 /**< SFSTAT_SBD Position */ 168 #define MXC_F_SIR_SFSTAT_SBD ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SBD_POS)) /**< SFSTAT_SBD Mask */ 169 170 #define MXC_F_SIR_SFSTAT_SLD_POS 1 /**< SFSTAT_SLD Position */ 171 #define MXC_F_SIR_SFSTAT_SLD ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SLD_POS)) /**< SFSTAT_SLD Mask */ 172 173 #define MXC_F_SIR_SFSTAT_TRNGD_POS 2 /**< SFSTAT_TRNGD Position */ 174 #define MXC_F_SIR_SFSTAT_TRNGD ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_TRNGD_POS)) /**< SFSTAT_TRNGD Mask */ 175 176 #define MXC_F_SIR_SFSTAT_AESD_POS 3 /**< SFSTAT_AESD Position */ 177 #define MXC_F_SIR_SFSTAT_AESD ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_AESD_POS)) /**< SFSTAT_AESD Mask */ 178 179 #define MXC_F_SIR_SFSTAT_SHAD_POS 4 /**< SFSTAT_SHAD Position */ 180 #define MXC_F_SIR_SFSTAT_SHAD ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SHAD_POS)) /**< SFSTAT_SHAD Mask */ 181 182 #define MXC_F_SIR_SFSTAT_SMD_POS 7 /**< SFSTAT_SMD Position */ 183 #define MXC_F_SIR_SFSTAT_SMD ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SMD_POS)) /**< SFSTAT_SMD Mask */ 184 185 /**@} end of group SIR_SFSTAT_Register */ 186 187 #ifdef __cplusplus 188 } 189 #endif 190 191 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SIR_REGS_H_ 192
