1 /** 2 * @file sdhc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SDHC Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SDHC_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SDHC_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup sdhc 66 * @defgroup sdhc_registers SDHC_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the SDHC Peripheral Module. 68 * @details SDHC/SDIO Controller 69 */ 70 71 /** 72 * @ingroup sdhc_registers 73 * Structure type to access the SDHC Registers. 74 */ 75 typedef struct { 76 __IO uint32_t sdma; /**< <tt>\b 0x00:</tt> SDHC SDMA Register */ 77 __IO uint16_t blk_size; /**< <tt>\b 0x04:</tt> SDHC BLK_SIZE Register */ 78 __IO uint16_t blk_cnt; /**< <tt>\b 0x06:</tt> SDHC BLK_CNT Register */ 79 __IO uint32_t arg_1; /**< <tt>\b 0x08:</tt> SDHC ARG_1 Register */ 80 __IO uint16_t trans; /**< <tt>\b 0x0C:</tt> SDHC TRANS Register */ 81 __IO uint16_t cmd; /**< <tt>\b 0x0E:</tt> SDHC CMD Register */ 82 __IO uint32_t resp[4]; /**< <tt>\b 0x010:</tt> SDHC RESP Register */ 83 __IO uint32_t buffer; /**< <tt>\b 0x20:</tt> SDHC BUFFER Register */ 84 __I uint32_t present; /**< <tt>\b 0x024:</tt> SDHC PRESENT Register */ 85 __IO uint8_t host_cn_1; /**< <tt>\b 0x028:</tt> SDHC HOST_CN_1 Register */ 86 __IO uint8_t pwr; /**< <tt>\b 0x029:</tt> SDHC PWR Register */ 87 __IO uint8_t blk_gap; /**< <tt>\b 0x02A:</tt> SDHC BLK_GAP Register */ 88 __IO uint8_t wakeup; /**< <tt>\b 0x02B:</tt> SDHC WAKEUP Register */ 89 __IO uint16_t clk_cn; /**< <tt>\b 0x02C:</tt> SDHC CLK_CN Register */ 90 __IO uint8_t to; /**< <tt>\b 0x02E:</tt> SDHC TO Register */ 91 __IO uint8_t sw_reset; /**< <tt>\b 0x02F:</tt> SDHC SW_RESET Register */ 92 __IO uint16_t int_stat; /**< <tt>\b 0x030:</tt> SDHC INT_STAT Register */ 93 __IO uint16_t er_int_stat; /**< <tt>\b 0x032:</tt> SDHC ER_INT_STAT Register */ 94 __IO uint16_t int_en; /**< <tt>\b 0x034:</tt> SDHC INT_EN Register */ 95 __IO uint16_t er_int_en; /**< <tt>\b 0x36:</tt> SDHC ER_INT_EN Register */ 96 __IO uint16_t int_signal; /**< <tt>\b 0x038:</tt> SDHC INT_SIGNAL Register */ 97 __IO uint16_t er_int_signal; /**< <tt>\b 0x03A:</tt> SDHC ER_INT_SIGNAL Register */ 98 __IO uint16_t auto_cmd_er; /**< <tt>\b 0x03C:</tt> SDHC AUTO_CMD_ER Register */ 99 __IO uint16_t host_cn_2; /**< <tt>\b 0x03E:</tt> SDHC HOST_CN_2 Register */ 100 __I uint32_t cfg_0; /**< <tt>\b 0x040:</tt> SDHC CFG_0 Register */ 101 __I uint32_t cfg_1; /**< <tt>\b 0x044:</tt> SDHC CFG_1 Register */ 102 __I uint32_t max_curr_cfg; /**< <tt>\b 0x048:</tt> SDHC MAX_CURR_CFG Register */ 103 __R uint32_t rsv_0x4c; 104 __O uint16_t force_cmd; /**< <tt>\b 0x050:</tt> SDHC FORCE_CMD Register */ 105 __IO uint16_t force_event_int_stat; /**< <tt>\b 0x052:</tt> SDHC FORCE_EVENT_INT_STAT Register */ 106 __IO uint8_t adma_er; /**< <tt>\b 0x054:</tt> SDHC ADMA_ER Register */ 107 __R uint8_t rsv_0x55_0x57[3]; 108 __IO uint32_t adma_addr_0; /**< <tt>\b 0x058:</tt> SDHC ADMA_ADDR_0 Register */ 109 __IO uint32_t adma_addr_1; /**< <tt>\b 0x05C:</tt> SDHC ADMA_ADDR_1 Register */ 110 __I uint16_t preset_0; /**< <tt>\b 0x060:</tt> SDHC PRESET_0 Register */ 111 __I uint16_t preset_1; /**< <tt>\b 0x062:</tt> SDHC PRESET_1 Register */ 112 __I uint16_t preset_2; /**< <tt>\b 0x064:</tt> SDHC PRESET_2 Register */ 113 __I uint16_t preset_3; /**< <tt>\b 0x066:</tt> SDHC PRESET_3 Register */ 114 __I uint16_t preset_4; /**< <tt>\b 0x068:</tt> SDHC PRESET_4 Register */ 115 __I uint16_t preset_5; /**< <tt>\b 0x06A:</tt> SDHC PRESET_5 Register */ 116 __I uint16_t preset_6; /**< <tt>\b 0x06C:</tt> SDHC PRESET_6 Register */ 117 __I uint16_t preset_7; /**< <tt>\b 0x06E:</tt> SDHC PRESET_7 Register */ 118 __R uint32_t rsv_0x70_0xfb[35]; 119 __I uint16_t slot_int; /**< <tt>\b 0x0FC:</tt> SDHC SLOT_INT Register */ 120 __IO uint16_t host_cn_ver; /**< <tt>\b 0x0FE:</tt> SDHC HOST_CN_VER Register */ 121 } mxc_sdhc_regs_t; 122 123 /* Register offsets for module SDHC */ 124 /** 125 * @ingroup sdhc_registers 126 * @defgroup SDHC_Register_Offsets Register Offsets 127 * @brief SDHC Peripheral Register Offsets from the SDHC Base Peripheral Address. 128 * @{ 129 */ 130 #define MXC_R_SDHC_SDMA ((uint32_t)0x00000000UL) /**< Offset from SDHC Base Address: <tt> 0x0000</tt> */ 131 #define MXC_R_SDHC_BLK_SIZE ((uint32_t)0x00000004UL) /**< Offset from SDHC Base Address: <tt> 0x0004</tt> */ 132 #define MXC_R_SDHC_BLK_CNT ((uint32_t)0x00000006UL) /**< Offset from SDHC Base Address: <tt> 0x0006</tt> */ 133 #define MXC_R_SDHC_ARG_1 ((uint32_t)0x00000008UL) /**< Offset from SDHC Base Address: <tt> 0x0008</tt> */ 134 #define MXC_R_SDHC_TRANS ((uint32_t)0x0000000CUL) /**< Offset from SDHC Base Address: <tt> 0x000C</tt> */ 135 #define MXC_R_SDHC_CMD ((uint32_t)0x0000000EUL) /**< Offset from SDHC Base Address: <tt> 0x000E</tt> */ 136 #define MXC_R_SDHC_RESP ((uint32_t)0x00000010UL) /**< Offset from SDHC Base Address: <tt> 0x0010</tt> */ 137 #define MXC_R_SDHC_BUFFER ((uint32_t)0x00000020UL) /**< Offset from SDHC Base Address: <tt> 0x0020</tt> */ 138 #define MXC_R_SDHC_PRESENT ((uint32_t)0x00000024UL) /**< Offset from SDHC Base Address: <tt> 0x0024</tt> */ 139 #define MXC_R_SDHC_HOST_CN_1 ((uint32_t)0x00000028UL) /**< Offset from SDHC Base Address: <tt> 0x0028</tt> */ 140 #define MXC_R_SDHC_PWR ((uint32_t)0x00000029UL) /**< Offset from SDHC Base Address: <tt> 0x0029</tt> */ 141 #define MXC_R_SDHC_BLK_GAP ((uint32_t)0x0000002AUL) /**< Offset from SDHC Base Address: <tt> 0x002A</tt> */ 142 #define MXC_R_SDHC_WAKEUP ((uint32_t)0x0000002BUL) /**< Offset from SDHC Base Address: <tt> 0x002B</tt> */ 143 #define MXC_R_SDHC_CLK_CN ((uint32_t)0x0000002CUL) /**< Offset from SDHC Base Address: <tt> 0x002C</tt> */ 144 #define MXC_R_SDHC_TO ((uint32_t)0x0000002EUL) /**< Offset from SDHC Base Address: <tt> 0x002E</tt> */ 145 #define MXC_R_SDHC_SW_RESET ((uint32_t)0x0000002FUL) /**< Offset from SDHC Base Address: <tt> 0x002F</tt> */ 146 #define MXC_R_SDHC_INT_STAT ((uint32_t)0x00000030UL) /**< Offset from SDHC Base Address: <tt> 0x0030</tt> */ 147 #define MXC_R_SDHC_ER_INT_STAT ((uint32_t)0x00000032UL) /**< Offset from SDHC Base Address: <tt> 0x0032</tt> */ 148 #define MXC_R_SDHC_INT_EN ((uint32_t)0x00000034UL) /**< Offset from SDHC Base Address: <tt> 0x0034</tt> */ 149 #define MXC_R_SDHC_ER_INT_EN ((uint32_t)0x00000036UL) /**< Offset from SDHC Base Address: <tt> 0x0036</tt> */ 150 #define MXC_R_SDHC_INT_SIGNAL ((uint32_t)0x00000038UL) /**< Offset from SDHC Base Address: <tt> 0x0038</tt> */ 151 #define MXC_R_SDHC_ER_INT_SIGNAL ((uint32_t)0x0000003AUL) /**< Offset from SDHC Base Address: <tt> 0x003A</tt> */ 152 #define MXC_R_SDHC_AUTO_CMD_ER ((uint32_t)0x0000003CUL) /**< Offset from SDHC Base Address: <tt> 0x003C</tt> */ 153 #define MXC_R_SDHC_HOST_CN_2 ((uint32_t)0x0000003EUL) /**< Offset from SDHC Base Address: <tt> 0x003E</tt> */ 154 #define MXC_R_SDHC_CFG_0 ((uint32_t)0x00000040UL) /**< Offset from SDHC Base Address: <tt> 0x0040</tt> */ 155 #define MXC_R_SDHC_CFG_1 ((uint32_t)0x00000044UL) /**< Offset from SDHC Base Address: <tt> 0x0044</tt> */ 156 #define MXC_R_SDHC_MAX_CURR_CFG ((uint32_t)0x00000048UL) /**< Offset from SDHC Base Address: <tt> 0x0048</tt> */ 157 #define MXC_R_SDHC_FORCE_CMD ((uint32_t)0x00000050UL) /**< Offset from SDHC Base Address: <tt> 0x0050</tt> */ 158 #define MXC_R_SDHC_FORCE_EVENT_INT_STAT ((uint32_t)0x00000052UL) /**< Offset from SDHC Base Address: <tt> 0x0052</tt> */ 159 #define MXC_R_SDHC_ADMA_ER ((uint32_t)0x00000054UL) /**< Offset from SDHC Base Address: <tt> 0x0054</tt> */ 160 #define MXC_R_SDHC_ADMA_ADDR_0 ((uint32_t)0x00000058UL) /**< Offset from SDHC Base Address: <tt> 0x0058</tt> */ 161 #define MXC_R_SDHC_ADMA_ADDR_1 ((uint32_t)0x0000005CUL) /**< Offset from SDHC Base Address: <tt> 0x005C</tt> */ 162 #define MXC_R_SDHC_PRESET_0 ((uint32_t)0x00000060UL) /**< Offset from SDHC Base Address: <tt> 0x0060</tt> */ 163 #define MXC_R_SDHC_PRESET_1 ((uint32_t)0x00000062UL) /**< Offset from SDHC Base Address: <tt> 0x0062</tt> */ 164 #define MXC_R_SDHC_PRESET_2 ((uint32_t)0x00000064UL) /**< Offset from SDHC Base Address: <tt> 0x0064</tt> */ 165 #define MXC_R_SDHC_PRESET_3 ((uint32_t)0x00000066UL) /**< Offset from SDHC Base Address: <tt> 0x0066</tt> */ 166 #define MXC_R_SDHC_PRESET_4 ((uint32_t)0x00000068UL) /**< Offset from SDHC Base Address: <tt> 0x0068</tt> */ 167 #define MXC_R_SDHC_PRESET_5 ((uint32_t)0x0000006AUL) /**< Offset from SDHC Base Address: <tt> 0x006A</tt> */ 168 #define MXC_R_SDHC_PRESET_6 ((uint32_t)0x0000006CUL) /**< Offset from SDHC Base Address: <tt> 0x006C</tt> */ 169 #define MXC_R_SDHC_PRESET_7 ((uint32_t)0x0000006EUL) /**< Offset from SDHC Base Address: <tt> 0x006E</tt> */ 170 #define MXC_R_SDHC_SLOT_INT ((uint32_t)0x000000FCUL) /**< Offset from SDHC Base Address: <tt> 0x00FC</tt> */ 171 #define MXC_R_SDHC_HOST_CN_VER ((uint32_t)0x000000FEUL) /**< Offset from SDHC Base Address: <tt> 0x00FE</tt> */ 172 /**@} end of group sdhc_registers */ 173 174 /** 175 * @ingroup sdhc_registers 176 * @defgroup SDHC_SDMA SDHC_SDMA 177 * @brief SDMA System Address / Argument 2. 178 * @{ 179 */ 180 #define MXC_F_SDHC_SDMA_ADDR_POS 0 /**< SDMA_ADDR Position */ 181 #define MXC_F_SDHC_SDMA_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_SDMA_ADDR_POS)) /**< SDMA_ADDR Mask */ 182 183 /**@} end of group SDHC_SDMA_Register */ 184 185 /** 186 * @ingroup sdhc_registers 187 * @defgroup SDHC_BLK_SIZE SDHC_BLK_SIZE 188 * @brief Block Size. 189 * @{ 190 */ 191 #define MXC_F_SDHC_BLK_SIZE_TRANS_POS 0 /**< BLK_SIZE_TRANS Position */ 192 #define MXC_F_SDHC_BLK_SIZE_TRANS ((uint16_t)(0xFFFUL << MXC_F_SDHC_BLK_SIZE_TRANS_POS)) /**< BLK_SIZE_TRANS Mask */ 193 194 #define MXC_F_SDHC_BLK_SIZE_HOST_BUFF_POS 12 /**< BLK_SIZE_HOST_BUFF Position */ 195 #define MXC_F_SDHC_BLK_SIZE_HOST_BUFF ((uint16_t)(0x7UL << MXC_F_SDHC_BLK_SIZE_HOST_BUFF_POS)) /**< BLK_SIZE_HOST_BUFF Mask */ 196 197 /**@} end of group SDHC_BLK_SIZE_Register */ 198 199 /** 200 * @ingroup sdhc_registers 201 * @defgroup SDHC_BLK_CNT SDHC_BLK_CNT 202 * @brief Block Count. 203 * @{ 204 */ 205 #define MXC_F_SDHC_BLK_CNT_TRANS_POS 0 /**< BLK_CNT_TRANS Position */ 206 #define MXC_F_SDHC_BLK_CNT_TRANS ((uint16_t)(0xFFFFUL << MXC_F_SDHC_BLK_CNT_TRANS_POS)) /**< BLK_CNT_TRANS Mask */ 207 208 /**@} end of group SDHC_BLK_CNT_Register */ 209 210 /** 211 * @ingroup sdhc_registers 212 * @defgroup SDHC_ARG_1 SDHC_ARG_1 213 * @brief Argument 1. 214 * @{ 215 */ 216 #define MXC_F_SDHC_ARG_1_CMD_POS 0 /**< ARG_1_CMD Position */ 217 #define MXC_F_SDHC_ARG_1_CMD ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_ARG_1_CMD_POS)) /**< ARG_1_CMD Mask */ 218 219 /**@} end of group SDHC_ARG_1_Register */ 220 221 /** 222 * @ingroup sdhc_registers 223 * @defgroup SDHC_TRANS SDHC_TRANS 224 * @brief Transfer Mode. 225 * @{ 226 */ 227 #define MXC_F_SDHC_TRANS_DMA_EN_POS 0 /**< TRANS_DMA_EN Position */ 228 #define MXC_F_SDHC_TRANS_DMA_EN ((uint16_t)(0x1UL << MXC_F_SDHC_TRANS_DMA_EN_POS)) /**< TRANS_DMA_EN Mask */ 229 230 #define MXC_F_SDHC_TRANS_BLK_CNT_EN_POS 1 /**< TRANS_BLK_CNT_EN Position */ 231 #define MXC_F_SDHC_TRANS_BLK_CNT_EN ((uint16_t)(0x1UL << MXC_F_SDHC_TRANS_BLK_CNT_EN_POS)) /**< TRANS_BLK_CNT_EN Mask */ 232 233 #define MXC_F_SDHC_TRANS_AUTO_CMD_EN_POS 2 /**< TRANS_AUTO_CMD_EN Position */ 234 #define MXC_F_SDHC_TRANS_AUTO_CMD_EN ((uint16_t)(0x3UL << MXC_F_SDHC_TRANS_AUTO_CMD_EN_POS)) /**< TRANS_AUTO_CMD_EN Mask */ 235 #define MXC_V_SDHC_TRANS_AUTO_CMD_EN_DISABLE ((uint16_t)0x0UL) /**< TRANS_AUTO_CMD_EN_DISABLE Value */ 236 #define MXC_S_SDHC_TRANS_AUTO_CMD_EN_DISABLE (MXC_V_SDHC_TRANS_AUTO_CMD_EN_DISABLE << MXC_F_SDHC_TRANS_AUTO_CMD_EN_POS) /**< TRANS_AUTO_CMD_EN_DISABLE Setting */ 237 #define MXC_V_SDHC_TRANS_AUTO_CMD_EN_CMD12 ((uint16_t)0x1UL) /**< TRANS_AUTO_CMD_EN_CMD12 Value */ 238 #define MXC_S_SDHC_TRANS_AUTO_CMD_EN_CMD12 (MXC_V_SDHC_TRANS_AUTO_CMD_EN_CMD12 << MXC_F_SDHC_TRANS_AUTO_CMD_EN_POS) /**< TRANS_AUTO_CMD_EN_CMD12 Setting */ 239 #define MXC_V_SDHC_TRANS_AUTO_CMD_EN_CMD23 ((uint16_t)0x2UL) /**< TRANS_AUTO_CMD_EN_CMD23 Value */ 240 #define MXC_S_SDHC_TRANS_AUTO_CMD_EN_CMD23 (MXC_V_SDHC_TRANS_AUTO_CMD_EN_CMD23 << MXC_F_SDHC_TRANS_AUTO_CMD_EN_POS) /**< TRANS_AUTO_CMD_EN_CMD23 Setting */ 241 242 #define MXC_F_SDHC_TRANS_READ_WRITE_POS 4 /**< TRANS_READ_WRITE Position */ 243 #define MXC_F_SDHC_TRANS_READ_WRITE ((uint16_t)(0x1UL << MXC_F_SDHC_TRANS_READ_WRITE_POS)) /**< TRANS_READ_WRITE Mask */ 244 245 #define MXC_F_SDHC_TRANS_MULTI_POS 5 /**< TRANS_MULTI Position */ 246 #define MXC_F_SDHC_TRANS_MULTI ((uint16_t)(0x1UL << MXC_F_SDHC_TRANS_MULTI_POS)) /**< TRANS_MULTI Mask */ 247 248 /**@} end of group SDHC_TRANS_Register */ 249 250 /** 251 * @ingroup sdhc_registers 252 * @defgroup SDHC_CMD SDHC_CMD 253 * @brief Command. 254 * @{ 255 */ 256 #define MXC_F_SDHC_CMD_RESP_TYPE_POS 0 /**< CMD_RESP_TYPE Position */ 257 #define MXC_F_SDHC_CMD_RESP_TYPE ((uint16_t)(0x3UL << MXC_F_SDHC_CMD_RESP_TYPE_POS)) /**< CMD_RESP_TYPE Mask */ 258 259 #define MXC_F_SDHC_CMD_CRC_CHK_EN_POS 3 /**< CMD_CRC_CHK_EN Position */ 260 #define MXC_F_SDHC_CMD_CRC_CHK_EN ((uint16_t)(0x1UL << MXC_F_SDHC_CMD_CRC_CHK_EN_POS)) /**< CMD_CRC_CHK_EN Mask */ 261 262 #define MXC_F_SDHC_CMD_IDX_CHK_EN_POS 4 /**< CMD_IDX_CHK_EN Position */ 263 #define MXC_F_SDHC_CMD_IDX_CHK_EN ((uint16_t)(0x1UL << MXC_F_SDHC_CMD_IDX_CHK_EN_POS)) /**< CMD_IDX_CHK_EN Mask */ 264 265 #define MXC_F_SDHC_CMD_DATA_PRES_SEL_POS 5 /**< CMD_DATA_PRES_SEL Position */ 266 #define MXC_F_SDHC_CMD_DATA_PRES_SEL ((uint16_t)(0x1UL << MXC_F_SDHC_CMD_DATA_PRES_SEL_POS)) /**< CMD_DATA_PRES_SEL Mask */ 267 268 #define MXC_F_SDHC_CMD_TYPE_POS 6 /**< CMD_TYPE Position */ 269 #define MXC_F_SDHC_CMD_TYPE ((uint16_t)(0x3UL << MXC_F_SDHC_CMD_TYPE_POS)) /**< CMD_TYPE Mask */ 270 271 #define MXC_F_SDHC_CMD_IDX_POS 8 /**< CMD_IDX Position */ 272 #define MXC_F_SDHC_CMD_IDX ((uint16_t)(0x3FUL << MXC_F_SDHC_CMD_IDX_POS)) /**< CMD_IDX Mask */ 273 274 /**@} end of group SDHC_CMD_Register */ 275 276 /** 277 * @ingroup sdhc_registers 278 * @defgroup SDHC_RESP SDHC_RESP 279 * @brief Response 0 Register 0-7. 280 * @{ 281 */ 282 #define MXC_F_SDHC_RESP_CMD_RESP_POS 0 /**< RESP_CMD_RESP Position */ 283 #define MXC_F_SDHC_RESP_CMD_RESP ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_RESP_CMD_RESP_POS)) /**< RESP_CMD_RESP Mask */ 284 285 /**@} end of group SDHC_RESP_Register */ 286 287 /** 288 * @ingroup sdhc_registers 289 * @defgroup SDHC_BUFFER SDHC_BUFFER 290 * @brief Buffer Data Port. 291 * @{ 292 */ 293 #define MXC_F_SDHC_BUFFER_DATA_POS 0 /**< BUFFER_DATA Position */ 294 #define MXC_F_SDHC_BUFFER_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_BUFFER_DATA_POS)) /**< BUFFER_DATA Mask */ 295 296 /**@} end of group SDHC_BUFFER_Register */ 297 298 /** 299 * @ingroup sdhc_registers 300 * @defgroup SDHC_PRESENT SDHC_PRESENT 301 * @brief Present State. 302 * @{ 303 */ 304 #define MXC_F_SDHC_PRESENT_CMD_POS 0 /**< PRESENT_CMD Position */ 305 #define MXC_F_SDHC_PRESENT_CMD ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_CMD_POS)) /**< PRESENT_CMD Mask */ 306 307 #define MXC_F_SDHC_PRESENT_DAT_POS 1 /**< PRESENT_DAT Position */ 308 #define MXC_F_SDHC_PRESENT_DAT ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_DAT_POS)) /**< PRESENT_DAT Mask */ 309 310 #define MXC_F_SDHC_PRESENT_DAT_LINE_ACTIVE_POS 2 /**< PRESENT_DAT_LINE_ACTIVE Position */ 311 #define MXC_F_SDHC_PRESENT_DAT_LINE_ACTIVE ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_DAT_LINE_ACTIVE_POS)) /**< PRESENT_DAT_LINE_ACTIVE Mask */ 312 313 #define MXC_F_SDHC_PRESENT_RETUNING_POS 3 /**< PRESENT_RETUNING Position */ 314 #define MXC_F_SDHC_PRESENT_RETUNING ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_RETUNING_POS)) /**< PRESENT_RETUNING Mask */ 315 316 #define MXC_F_SDHC_PRESENT_WRITE_TRANSFER_POS 8 /**< PRESENT_WRITE_TRANSFER Position */ 317 #define MXC_F_SDHC_PRESENT_WRITE_TRANSFER ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_WRITE_TRANSFER_POS)) /**< PRESENT_WRITE_TRANSFER Mask */ 318 319 #define MXC_F_SDHC_PRESENT_READ_TRANSFER_POS 9 /**< PRESENT_READ_TRANSFER Position */ 320 #define MXC_F_SDHC_PRESENT_READ_TRANSFER ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_READ_TRANSFER_POS)) /**< PRESENT_READ_TRANSFER Mask */ 321 322 #define MXC_F_SDHC_PRESENT_BUFFER_WRITE_POS 10 /**< PRESENT_BUFFER_WRITE Position */ 323 #define MXC_F_SDHC_PRESENT_BUFFER_WRITE ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_BUFFER_WRITE_POS)) /**< PRESENT_BUFFER_WRITE Mask */ 324 325 #define MXC_F_SDHC_PRESENT_BUFFER_READ_POS 11 /**< PRESENT_BUFFER_READ Position */ 326 #define MXC_F_SDHC_PRESENT_BUFFER_READ ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_BUFFER_READ_POS)) /**< PRESENT_BUFFER_READ Mask */ 327 328 #define MXC_F_SDHC_PRESENT_CARD_INSERTED_POS 16 /**< PRESENT_CARD_INSERTED Position */ 329 #define MXC_F_SDHC_PRESENT_CARD_INSERTED ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_CARD_INSERTED_POS)) /**< PRESENT_CARD_INSERTED Mask */ 330 331 #define MXC_F_SDHC_PRESENT_CARD_STATE_POS 17 /**< PRESENT_CARD_STATE Position */ 332 #define MXC_F_SDHC_PRESENT_CARD_STATE ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_CARD_STATE_POS)) /**< PRESENT_CARD_STATE Mask */ 333 334 #define MXC_F_SDHC_PRESENT_CARD_DETECT_POS 18 /**< PRESENT_CARD_DETECT Position */ 335 #define MXC_F_SDHC_PRESENT_CARD_DETECT ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_CARD_DETECT_POS)) /**< PRESENT_CARD_DETECT Mask */ 336 337 #define MXC_F_SDHC_PRESENT_WP_POS 19 /**< PRESENT_WP Position */ 338 #define MXC_F_SDHC_PRESENT_WP ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_WP_POS)) /**< PRESENT_WP Mask */ 339 340 #define MXC_F_SDHC_PRESENT_DAT_SIGNAL_LEVEL_POS 20 /**< PRESENT_DAT_SIGNAL_LEVEL Position */ 341 #define MXC_F_SDHC_PRESENT_DAT_SIGNAL_LEVEL ((uint32_t)(0xFUL << MXC_F_SDHC_PRESENT_DAT_SIGNAL_LEVEL_POS)) /**< PRESENT_DAT_SIGNAL_LEVEL Mask */ 342 343 #define MXC_F_SDHC_PRESENT_CMD_SIGNAL_LEVEL_POS 24 /**< PRESENT_CMD_SIGNAL_LEVEL Position */ 344 #define MXC_F_SDHC_PRESENT_CMD_SIGNAL_LEVEL ((uint32_t)(0x1UL << MXC_F_SDHC_PRESENT_CMD_SIGNAL_LEVEL_POS)) /**< PRESENT_CMD_SIGNAL_LEVEL Mask */ 345 346 /**@} end of group SDHC_PRESENT_Register */ 347 348 /** 349 * @ingroup sdhc_registers 350 * @defgroup SDHC_HOST_CN_1 SDHC_HOST_CN_1 351 * @brief Host Control 1. 352 * @{ 353 */ 354 #define MXC_F_SDHC_HOST_CN_1_LED_CN_POS 0 /**< HOST_CN_1_LED_CN Position */ 355 #define MXC_F_SDHC_HOST_CN_1_LED_CN ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_LED_CN_POS)) /**< HOST_CN_1_LED_CN Mask */ 356 357 #define MXC_F_SDHC_HOST_CN_1_DATA_TRANSFER_WIDTH_POS 1 /**< HOST_CN_1_DATA_TRANSFER_WIDTH Position */ 358 #define MXC_F_SDHC_HOST_CN_1_DATA_TRANSFER_WIDTH ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_DATA_TRANSFER_WIDTH_POS)) /**< HOST_CN_1_DATA_TRANSFER_WIDTH Mask */ 359 360 #define MXC_F_SDHC_HOST_CN_1_HS_EN_POS 2 /**< HOST_CN_1_HS_EN Position */ 361 #define MXC_F_SDHC_HOST_CN_1_HS_EN ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_HS_EN_POS)) /**< HOST_CN_1_HS_EN Mask */ 362 363 #define MXC_F_SDHC_HOST_CN_1_DMA_SELECT_POS 3 /**< HOST_CN_1_DMA_SELECT Position */ 364 #define MXC_F_SDHC_HOST_CN_1_DMA_SELECT ((uint8_t)(0x3UL << MXC_F_SDHC_HOST_CN_1_DMA_SELECT_POS)) /**< HOST_CN_1_DMA_SELECT Mask */ 365 366 #define MXC_F_SDHC_HOST_CN_1_EXT_DATA_TRANSFER_WIDTH_POS 5 /**< HOST_CN_1_EXT_DATA_TRANSFER_WIDTH Position */ 367 #define MXC_F_SDHC_HOST_CN_1_EXT_DATA_TRANSFER_WIDTH ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_EXT_DATA_TRANSFER_WIDTH_POS)) /**< HOST_CN_1_EXT_DATA_TRANSFER_WIDTH Mask */ 368 369 #define MXC_F_SDHC_HOST_CN_1_CARD_DETECT_TEST_POS 6 /**< HOST_CN_1_CARD_DETECT_TEST Position */ 370 #define MXC_F_SDHC_HOST_CN_1_CARD_DETECT_TEST ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_CARD_DETECT_TEST_POS)) /**< HOST_CN_1_CARD_DETECT_TEST Mask */ 371 372 #define MXC_F_SDHC_HOST_CN_1_CARD_DETECT_SIGNAL_POS 7 /**< HOST_CN_1_CARD_DETECT_SIGNAL Position */ 373 #define MXC_F_SDHC_HOST_CN_1_CARD_DETECT_SIGNAL ((uint8_t)(0x1UL << MXC_F_SDHC_HOST_CN_1_CARD_DETECT_SIGNAL_POS)) /**< HOST_CN_1_CARD_DETECT_SIGNAL Mask */ 374 375 /**@} end of group SDHC_HOST_CN_1_Register */ 376 377 /** 378 * @ingroup sdhc_registers 379 * @defgroup SDHC_PWR SDHC_PWR 380 * @brief Power Control. 381 * @{ 382 */ 383 #define MXC_F_SDHC_PWR_BUS_POWER_POS 0 /**< PWR_BUS_POWER Position */ 384 #define MXC_F_SDHC_PWR_BUS_POWER ((uint8_t)(0x1UL << MXC_F_SDHC_PWR_BUS_POWER_POS)) /**< PWR_BUS_POWER Mask */ 385 386 #define MXC_F_SDHC_PWR_BUS_VOLT_SEL_POS 1 /**< PWR_BUS_VOLT_SEL Position */ 387 #define MXC_F_SDHC_PWR_BUS_VOLT_SEL ((uint8_t)(0x7UL << MXC_F_SDHC_PWR_BUS_VOLT_SEL_POS)) /**< PWR_BUS_VOLT_SEL Mask */ 388 389 /**@} end of group SDHC_PWR_Register */ 390 391 /** 392 * @ingroup sdhc_registers 393 * @defgroup SDHC_BLK_GAP SDHC_BLK_GAP 394 * @brief Block Gap Control. 395 * @{ 396 */ 397 #define MXC_F_SDHC_BLK_GAP_STOP_POS 0 /**< BLK_GAP_STOP Position */ 398 #define MXC_F_SDHC_BLK_GAP_STOP ((uint8_t)(0x1UL << MXC_F_SDHC_BLK_GAP_STOP_POS)) /**< BLK_GAP_STOP Mask */ 399 400 #define MXC_F_SDHC_BLK_GAP_CONT_POS 1 /**< BLK_GAP_CONT Position */ 401 #define MXC_F_SDHC_BLK_GAP_CONT ((uint8_t)(0x1UL << MXC_F_SDHC_BLK_GAP_CONT_POS)) /**< BLK_GAP_CONT Mask */ 402 403 #define MXC_F_SDHC_BLK_GAP_READ_WAIT_POS 2 /**< BLK_GAP_READ_WAIT Position */ 404 #define MXC_F_SDHC_BLK_GAP_READ_WAIT ((uint8_t)(0x1UL << MXC_F_SDHC_BLK_GAP_READ_WAIT_POS)) /**< BLK_GAP_READ_WAIT Mask */ 405 406 #define MXC_F_SDHC_BLK_GAP_INTR_POS 3 /**< BLK_GAP_INTR Position */ 407 #define MXC_F_SDHC_BLK_GAP_INTR ((uint8_t)(0x1UL << MXC_F_SDHC_BLK_GAP_INTR_POS)) /**< BLK_GAP_INTR Mask */ 408 409 /**@} end of group SDHC_BLK_GAP_Register */ 410 411 /** 412 * @ingroup sdhc_registers 413 * @defgroup SDHC_WAKEUP SDHC_WAKEUP 414 * @brief Wakeup Control. 415 * @{ 416 */ 417 #define MXC_F_SDHC_WAKEUP_CARD_INT_POS 0 /**< WAKEUP_CARD_INT Position */ 418 #define MXC_F_SDHC_WAKEUP_CARD_INT ((uint8_t)(0x1UL << MXC_F_SDHC_WAKEUP_CARD_INT_POS)) /**< WAKEUP_CARD_INT Mask */ 419 420 #define MXC_F_SDHC_WAKEUP_CARD_INS_POS 1 /**< WAKEUP_CARD_INS Position */ 421 #define MXC_F_SDHC_WAKEUP_CARD_INS ((uint8_t)(0x1UL << MXC_F_SDHC_WAKEUP_CARD_INS_POS)) /**< WAKEUP_CARD_INS Mask */ 422 423 #define MXC_F_SDHC_WAKEUP_CARD_REM_POS 2 /**< WAKEUP_CARD_REM Position */ 424 #define MXC_F_SDHC_WAKEUP_CARD_REM ((uint8_t)(0x1UL << MXC_F_SDHC_WAKEUP_CARD_REM_POS)) /**< WAKEUP_CARD_REM Mask */ 425 426 /**@} end of group SDHC_WAKEUP_Register */ 427 428 /** 429 * @ingroup sdhc_registers 430 * @defgroup SDHC_CLK_CN SDHC_CLK_CN 431 * @brief Clock Control. 432 * @{ 433 */ 434 #define MXC_F_SDHC_CLK_CN_INTERNAL_CLK_EN_POS 0 /**< CLK_CN_INTERNAL_CLK_EN Position */ 435 #define MXC_F_SDHC_CLK_CN_INTERNAL_CLK_EN ((uint16_t)(0x1UL << MXC_F_SDHC_CLK_CN_INTERNAL_CLK_EN_POS)) /**< CLK_CN_INTERNAL_CLK_EN Mask */ 436 437 #define MXC_F_SDHC_CLK_CN_INTERNAL_CLK_STABLE_POS 1 /**< CLK_CN_INTERNAL_CLK_STABLE Position */ 438 #define MXC_F_SDHC_CLK_CN_INTERNAL_CLK_STABLE ((uint16_t)(0x1UL << MXC_F_SDHC_CLK_CN_INTERNAL_CLK_STABLE_POS)) /**< CLK_CN_INTERNAL_CLK_STABLE Mask */ 439 440 #define MXC_F_SDHC_CLK_CN_SD_CLK_EN_POS 2 /**< CLK_CN_SD_CLK_EN Position */ 441 #define MXC_F_SDHC_CLK_CN_SD_CLK_EN ((uint16_t)(0x1UL << MXC_F_SDHC_CLK_CN_SD_CLK_EN_POS)) /**< CLK_CN_SD_CLK_EN Mask */ 442 443 #define MXC_F_SDHC_CLK_CN_CLK_GEN_SEL_POS 5 /**< CLK_CN_CLK_GEN_SEL Position */ 444 #define MXC_F_SDHC_CLK_CN_CLK_GEN_SEL ((uint16_t)(0x1UL << MXC_F_SDHC_CLK_CN_CLK_GEN_SEL_POS)) /**< CLK_CN_CLK_GEN_SEL Mask */ 445 446 #define MXC_F_SDHC_CLK_CN_UPPER_SDCLK_FREQ_SEL_POS 6 /**< CLK_CN_UPPER_SDCLK_FREQ_SEL Position */ 447 #define MXC_F_SDHC_CLK_CN_UPPER_SDCLK_FREQ_SEL ((uint16_t)(0x3UL << MXC_F_SDHC_CLK_CN_UPPER_SDCLK_FREQ_SEL_POS)) /**< CLK_CN_UPPER_SDCLK_FREQ_SEL Mask */ 448 449 #define MXC_F_SDHC_CLK_CN_SDCLK_FREQ_SEL_POS 8 /**< CLK_CN_SDCLK_FREQ_SEL Position */ 450 #define MXC_F_SDHC_CLK_CN_SDCLK_FREQ_SEL ((uint16_t)(0xFFUL << MXC_F_SDHC_CLK_CN_SDCLK_FREQ_SEL_POS)) /**< CLK_CN_SDCLK_FREQ_SEL Mask */ 451 452 /**@} end of group SDHC_CLK_CN_Register */ 453 454 /** 455 * @ingroup sdhc_registers 456 * @defgroup SDHC_TO SDHC_TO 457 * @brief Timeout Control. 458 * @{ 459 */ 460 #define MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS 0 /**< TO_DATA_COUNT_VALUE Position */ 461 #define MXC_F_SDHC_TO_DATA_COUNT_VALUE ((uint8_t)(0x7UL << MXC_F_SDHC_TO_DATA_COUNT_VALUE_POS)) /**< TO_DATA_COUNT_VALUE Mask */ 462 463 /**@} end of group SDHC_TO_Register */ 464 465 /** 466 * @ingroup sdhc_registers 467 * @defgroup SDHC_SW_RESET SDHC_SW_RESET 468 * @brief Software Reset. 469 * @{ 470 */ 471 #define MXC_F_SDHC_SW_RESET_RESET_ALL_POS 0 /**< SW_RESET_RESET_ALL Position */ 472 #define MXC_F_SDHC_SW_RESET_RESET_ALL ((uint8_t)(0x1UL << MXC_F_SDHC_SW_RESET_RESET_ALL_POS)) /**< SW_RESET_RESET_ALL Mask */ 473 474 #define MXC_F_SDHC_SW_RESET_RESET_CMD_POS 1 /**< SW_RESET_RESET_CMD Position */ 475 #define MXC_F_SDHC_SW_RESET_RESET_CMD ((uint8_t)(0x1UL << MXC_F_SDHC_SW_RESET_RESET_CMD_POS)) /**< SW_RESET_RESET_CMD Mask */ 476 477 #define MXC_F_SDHC_SW_RESET_RESET_DAT_POS 2 /**< SW_RESET_RESET_DAT Position */ 478 #define MXC_F_SDHC_SW_RESET_RESET_DAT ((uint8_t)(0x1UL << MXC_F_SDHC_SW_RESET_RESET_DAT_POS)) /**< SW_RESET_RESET_DAT Mask */ 479 480 /**@} end of group SDHC_SW_RESET_Register */ 481 482 /** 483 * @ingroup sdhc_registers 484 * @defgroup SDHC_INT_STAT SDHC_INT_STAT 485 * @brief Normal Interrupt Status. 486 * @{ 487 */ 488 #define MXC_F_SDHC_INT_STAT_CMD_COMP_POS 0 /**< INT_STAT_CMD_COMP Position */ 489 #define MXC_F_SDHC_INT_STAT_CMD_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_CMD_COMP_POS)) /**< INT_STAT_CMD_COMP Mask */ 490 491 #define MXC_F_SDHC_INT_STAT_TRANS_COMP_POS 1 /**< INT_STAT_TRANS_COMP Position */ 492 #define MXC_F_SDHC_INT_STAT_TRANS_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_TRANS_COMP_POS)) /**< INT_STAT_TRANS_COMP Mask */ 493 494 #define MXC_F_SDHC_INT_STAT_BLK_GAP_EVENT_POS 2 /**< INT_STAT_BLK_GAP_EVENT Position */ 495 #define MXC_F_SDHC_INT_STAT_BLK_GAP_EVENT ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_BLK_GAP_EVENT_POS)) /**< INT_STAT_BLK_GAP_EVENT Mask */ 496 497 #define MXC_F_SDHC_INT_STAT_DMA_POS 3 /**< INT_STAT_DMA Position */ 498 #define MXC_F_SDHC_INT_STAT_DMA ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_DMA_POS)) /**< INT_STAT_DMA Mask */ 499 500 #define MXC_F_SDHC_INT_STAT_BUFF_WR_READY_POS 4 /**< INT_STAT_BUFF_WR_READY Position */ 501 #define MXC_F_SDHC_INT_STAT_BUFF_WR_READY ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_BUFF_WR_READY_POS)) /**< INT_STAT_BUFF_WR_READY Mask */ 502 503 #define MXC_F_SDHC_INT_STAT_BUFF_RD_READY_POS 5 /**< INT_STAT_BUFF_RD_READY Position */ 504 #define MXC_F_SDHC_INT_STAT_BUFF_RD_READY ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_BUFF_RD_READY_POS)) /**< INT_STAT_BUFF_RD_READY Mask */ 505 506 #define MXC_F_SDHC_INT_STAT_CARD_INSERTION_POS 6 /**< INT_STAT_CARD_INSERTION Position */ 507 #define MXC_F_SDHC_INT_STAT_CARD_INSERTION ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_CARD_INSERTION_POS)) /**< INT_STAT_CARD_INSERTION Mask */ 508 509 #define MXC_F_SDHC_INT_STAT_CARD_REMOVAL_POS 7 /**< INT_STAT_CARD_REMOVAL Position */ 510 #define MXC_F_SDHC_INT_STAT_CARD_REMOVAL ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_CARD_REMOVAL_POS)) /**< INT_STAT_CARD_REMOVAL Mask */ 511 512 #define MXC_F_SDHC_INT_STAT_CARD_INTR_POS 8 /**< INT_STAT_CARD_INTR Position */ 513 #define MXC_F_SDHC_INT_STAT_CARD_INTR ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_CARD_INTR_POS)) /**< INT_STAT_CARD_INTR Mask */ 514 515 #define MXC_F_SDHC_INT_STAT_RETUNING_POS 12 /**< INT_STAT_RETUNING Position */ 516 #define MXC_F_SDHC_INT_STAT_RETUNING ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_RETUNING_POS)) /**< INT_STAT_RETUNING Mask */ 517 518 #define MXC_F_SDHC_INT_STAT_ERR_INTR_POS 15 /**< INT_STAT_ERR_INTR Position */ 519 #define MXC_F_SDHC_INT_STAT_ERR_INTR ((uint16_t)(0x1UL << MXC_F_SDHC_INT_STAT_ERR_INTR_POS)) /**< INT_STAT_ERR_INTR Mask */ 520 521 /**@} end of group SDHC_INT_STAT_Register */ 522 523 /** 524 * @ingroup sdhc_registers 525 * @defgroup SDHC_ER_INT_STAT SDHC_ER_INT_STAT 526 * @brief Error Interrupt Status. 527 * @{ 528 */ 529 #define MXC_F_SDHC_ER_INT_STAT_CMD_TO_POS 0 /**< ER_INT_STAT_CMD_TO Position */ 530 #define MXC_F_SDHC_ER_INT_STAT_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_CMD_TO_POS)) /**< ER_INT_STAT_CMD_TO Mask */ 531 532 #define MXC_F_SDHC_ER_INT_STAT_CMD_CRC_POS 1 /**< ER_INT_STAT_CMD_CRC Position */ 533 #define MXC_F_SDHC_ER_INT_STAT_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_CMD_CRC_POS)) /**< ER_INT_STAT_CMD_CRC Mask */ 534 535 #define MXC_F_SDHC_ER_INT_STAT_CMD_END_BIT_POS 2 /**< ER_INT_STAT_CMD_END_BIT Position */ 536 #define MXC_F_SDHC_ER_INT_STAT_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_CMD_END_BIT_POS)) /**< ER_INT_STAT_CMD_END_BIT Mask */ 537 538 #define MXC_F_SDHC_ER_INT_STAT_CMD_IDX_POS 3 /**< ER_INT_STAT_CMD_IDX Position */ 539 #define MXC_F_SDHC_ER_INT_STAT_CMD_IDX ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_CMD_IDX_POS)) /**< ER_INT_STAT_CMD_IDX Mask */ 540 541 #define MXC_F_SDHC_ER_INT_STAT_DATA_TO_POS 4 /**< ER_INT_STAT_DATA_TO Position */ 542 #define MXC_F_SDHC_ER_INT_STAT_DATA_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_DATA_TO_POS)) /**< ER_INT_STAT_DATA_TO Mask */ 543 544 #define MXC_F_SDHC_ER_INT_STAT_DATA_CRC_POS 5 /**< ER_INT_STAT_DATA_CRC Position */ 545 #define MXC_F_SDHC_ER_INT_STAT_DATA_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_DATA_CRC_POS)) /**< ER_INT_STAT_DATA_CRC Mask */ 546 547 #define MXC_F_SDHC_ER_INT_STAT_DATA_END_BIT_POS 6 /**< ER_INT_STAT_DATA_END_BIT Position */ 548 #define MXC_F_SDHC_ER_INT_STAT_DATA_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_DATA_END_BIT_POS)) /**< ER_INT_STAT_DATA_END_BIT Mask */ 549 550 #define MXC_F_SDHC_ER_INT_STAT_CURRENT_LIMIT_POS 7 /**< ER_INT_STAT_CURRENT_LIMIT Position */ 551 #define MXC_F_SDHC_ER_INT_STAT_CURRENT_LIMIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_CURRENT_LIMIT_POS)) /**< ER_INT_STAT_CURRENT_LIMIT Mask */ 552 553 #define MXC_F_SDHC_ER_INT_STAT_AUTO_CMD_12_POS 8 /**< ER_INT_STAT_AUTO_CMD_12 Position */ 554 #define MXC_F_SDHC_ER_INT_STAT_AUTO_CMD_12 ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_AUTO_CMD_12_POS)) /**< ER_INT_STAT_AUTO_CMD_12 Mask */ 555 556 #define MXC_F_SDHC_ER_INT_STAT_ADMA_POS 9 /**< ER_INT_STAT_ADMA Position */ 557 #define MXC_F_SDHC_ER_INT_STAT_ADMA ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_ADMA_POS)) /**< ER_INT_STAT_ADMA Mask */ 558 559 #define MXC_F_SDHC_ER_INT_STAT_DMA_POS 12 /**< ER_INT_STAT_DMA Position */ 560 #define MXC_F_SDHC_ER_INT_STAT_DMA ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_STAT_DMA_POS)) /**< ER_INT_STAT_DMA Mask */ 561 562 /**@} end of group SDHC_ER_INT_STAT_Register */ 563 564 /** 565 * @ingroup sdhc_registers 566 * @defgroup SDHC_INT_EN SDHC_INT_EN 567 * @brief Normal Interrupt Status Enable. 568 * @{ 569 */ 570 #define MXC_F_SDHC_INT_EN_CMD_COMP_POS 0 /**< INT_EN_CMD_COMP Position */ 571 #define MXC_F_SDHC_INT_EN_CMD_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_CMD_COMP_POS)) /**< INT_EN_CMD_COMP Mask */ 572 573 #define MXC_F_SDHC_INT_EN_TRANS_COMP_POS 1 /**< INT_EN_TRANS_COMP Position */ 574 #define MXC_F_SDHC_INT_EN_TRANS_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_TRANS_COMP_POS)) /**< INT_EN_TRANS_COMP Mask */ 575 576 #define MXC_F_SDHC_INT_EN_BLK_GAP_POS 2 /**< INT_EN_BLK_GAP Position */ 577 #define MXC_F_SDHC_INT_EN_BLK_GAP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_BLK_GAP_POS)) /**< INT_EN_BLK_GAP Mask */ 578 579 #define MXC_F_SDHC_INT_EN_DMA_POS 3 /**< INT_EN_DMA Position */ 580 #define MXC_F_SDHC_INT_EN_DMA ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_DMA_POS)) /**< INT_EN_DMA Mask */ 581 582 #define MXC_F_SDHC_INT_EN_BUFFER_WR_POS 4 /**< INT_EN_BUFFER_WR Position */ 583 #define MXC_F_SDHC_INT_EN_BUFFER_WR ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_BUFFER_WR_POS)) /**< INT_EN_BUFFER_WR Mask */ 584 585 #define MXC_F_SDHC_INT_EN_BUFFER_RD_POS 5 /**< INT_EN_BUFFER_RD Position */ 586 #define MXC_F_SDHC_INT_EN_BUFFER_RD ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_BUFFER_RD_POS)) /**< INT_EN_BUFFER_RD Mask */ 587 588 #define MXC_F_SDHC_INT_EN_CARD_INSERT_POS 6 /**< INT_EN_CARD_INSERT Position */ 589 #define MXC_F_SDHC_INT_EN_CARD_INSERT ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_CARD_INSERT_POS)) /**< INT_EN_CARD_INSERT Mask */ 590 591 #define MXC_F_SDHC_INT_EN_CARD_REMOVAL_POS 7 /**< INT_EN_CARD_REMOVAL Position */ 592 #define MXC_F_SDHC_INT_EN_CARD_REMOVAL ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_CARD_REMOVAL_POS)) /**< INT_EN_CARD_REMOVAL Mask */ 593 594 #define MXC_F_SDHC_INT_EN_CARD_INT_POS 8 /**< INT_EN_CARD_INT Position */ 595 #define MXC_F_SDHC_INT_EN_CARD_INT ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_CARD_INT_POS)) /**< INT_EN_CARD_INT Mask */ 596 597 #define MXC_F_SDHC_INT_EN_RETUNING_POS 12 /**< INT_EN_RETUNING Position */ 598 #define MXC_F_SDHC_INT_EN_RETUNING ((uint16_t)(0x1UL << MXC_F_SDHC_INT_EN_RETUNING_POS)) /**< INT_EN_RETUNING Mask */ 599 600 /**@} end of group SDHC_INT_EN_Register */ 601 602 /** 603 * @ingroup sdhc_registers 604 * @defgroup SDHC_ER_INT_EN SDHC_ER_INT_EN 605 * @brief Error Interrupt Status Enable. 606 * @{ 607 */ 608 #define MXC_F_SDHC_ER_INT_EN_CMD_TO_POS 0 /**< ER_INT_EN_CMD_TO Position */ 609 #define MXC_F_SDHC_ER_INT_EN_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_CMD_TO_POS)) /**< ER_INT_EN_CMD_TO Mask */ 610 611 #define MXC_F_SDHC_ER_INT_EN_CMD_CRC_POS 1 /**< ER_INT_EN_CMD_CRC Position */ 612 #define MXC_F_SDHC_ER_INT_EN_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_CMD_CRC_POS)) /**< ER_INT_EN_CMD_CRC Mask */ 613 614 #define MXC_F_SDHC_ER_INT_EN_CMD_END_BIT_POS 2 /**< ER_INT_EN_CMD_END_BIT Position */ 615 #define MXC_F_SDHC_ER_INT_EN_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_CMD_END_BIT_POS)) /**< ER_INT_EN_CMD_END_BIT Mask */ 616 617 #define MXC_F_SDHC_ER_INT_EN_CMD_IDX_POS 3 /**< ER_INT_EN_CMD_IDX Position */ 618 #define MXC_F_SDHC_ER_INT_EN_CMD_IDX ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_CMD_IDX_POS)) /**< ER_INT_EN_CMD_IDX Mask */ 619 620 #define MXC_F_SDHC_ER_INT_EN_DATA_TO_POS 4 /**< ER_INT_EN_DATA_TO Position */ 621 #define MXC_F_SDHC_ER_INT_EN_DATA_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_DATA_TO_POS)) /**< ER_INT_EN_DATA_TO Mask */ 622 623 #define MXC_F_SDHC_ER_INT_EN_DATA_CRC_POS 5 /**< ER_INT_EN_DATA_CRC Position */ 624 #define MXC_F_SDHC_ER_INT_EN_DATA_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_DATA_CRC_POS)) /**< ER_INT_EN_DATA_CRC Mask */ 625 626 #define MXC_F_SDHC_ER_INT_EN_DATA_END_BIT_POS 6 /**< ER_INT_EN_DATA_END_BIT Position */ 627 #define MXC_F_SDHC_ER_INT_EN_DATA_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_DATA_END_BIT_POS)) /**< ER_INT_EN_DATA_END_BIT Mask */ 628 629 #define MXC_F_SDHC_ER_INT_EN_AUTO_CMD_POS 8 /**< ER_INT_EN_AUTO_CMD Position */ 630 #define MXC_F_SDHC_ER_INT_EN_AUTO_CMD ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_AUTO_CMD_POS)) /**< ER_INT_EN_AUTO_CMD Mask */ 631 632 #define MXC_F_SDHC_ER_INT_EN_ADMA_POS 9 /**< ER_INT_EN_ADMA Position */ 633 #define MXC_F_SDHC_ER_INT_EN_ADMA ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_ADMA_POS)) /**< ER_INT_EN_ADMA Mask */ 634 635 #define MXC_F_SDHC_ER_INT_EN_TUNING_POS 10 /**< ER_INT_EN_TUNING Position */ 636 #define MXC_F_SDHC_ER_INT_EN_TUNING ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_TUNING_POS)) /**< ER_INT_EN_TUNING Mask */ 637 638 #define MXC_F_SDHC_ER_INT_EN_VENDOR_POS 12 /**< ER_INT_EN_VENDOR Position */ 639 #define MXC_F_SDHC_ER_INT_EN_VENDOR ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_EN_VENDOR_POS)) /**< ER_INT_EN_VENDOR Mask */ 640 641 /**@} end of group SDHC_ER_INT_EN_Register */ 642 643 /** 644 * @ingroup sdhc_registers 645 * @defgroup SDHC_INT_SIGNAL SDHC_INT_SIGNAL 646 * @brief Normal Interrupt Signal Enable. 647 * @{ 648 */ 649 #define MXC_F_SDHC_INT_SIGNAL_CMD_COMP_POS 0 /**< INT_SIGNAL_CMD_COMP Position */ 650 #define MXC_F_SDHC_INT_SIGNAL_CMD_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_CMD_COMP_POS)) /**< INT_SIGNAL_CMD_COMP Mask */ 651 652 #define MXC_F_SDHC_INT_SIGNAL_TRANS_COMP_POS 1 /**< INT_SIGNAL_TRANS_COMP Position */ 653 #define MXC_F_SDHC_INT_SIGNAL_TRANS_COMP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_TRANS_COMP_POS)) /**< INT_SIGNAL_TRANS_COMP Mask */ 654 655 #define MXC_F_SDHC_INT_SIGNAL_BLK_GAP_POS 2 /**< INT_SIGNAL_BLK_GAP Position */ 656 #define MXC_F_SDHC_INT_SIGNAL_BLK_GAP ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_BLK_GAP_POS)) /**< INT_SIGNAL_BLK_GAP Mask */ 657 658 #define MXC_F_SDHC_INT_SIGNAL_DMA_POS 3 /**< INT_SIGNAL_DMA Position */ 659 #define MXC_F_SDHC_INT_SIGNAL_DMA ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_DMA_POS)) /**< INT_SIGNAL_DMA Mask */ 660 661 #define MXC_F_SDHC_INT_SIGNAL_BUFFER_WR_POS 4 /**< INT_SIGNAL_BUFFER_WR Position */ 662 #define MXC_F_SDHC_INT_SIGNAL_BUFFER_WR ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_BUFFER_WR_POS)) /**< INT_SIGNAL_BUFFER_WR Mask */ 663 664 #define MXC_F_SDHC_INT_SIGNAL_BUFFER_RD_POS 5 /**< INT_SIGNAL_BUFFER_RD Position */ 665 #define MXC_F_SDHC_INT_SIGNAL_BUFFER_RD ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_BUFFER_RD_POS)) /**< INT_SIGNAL_BUFFER_RD Mask */ 666 667 #define MXC_F_SDHC_INT_SIGNAL_CARD_INSERT_POS 6 /**< INT_SIGNAL_CARD_INSERT Position */ 668 #define MXC_F_SDHC_INT_SIGNAL_CARD_INSERT ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_CARD_INSERT_POS)) /**< INT_SIGNAL_CARD_INSERT Mask */ 669 670 #define MXC_F_SDHC_INT_SIGNAL_CARD_REMOVAL_POS 7 /**< INT_SIGNAL_CARD_REMOVAL Position */ 671 #define MXC_F_SDHC_INT_SIGNAL_CARD_REMOVAL ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_CARD_REMOVAL_POS)) /**< INT_SIGNAL_CARD_REMOVAL Mask */ 672 673 #define MXC_F_SDHC_INT_SIGNAL_CARD_INT_POS 8 /**< INT_SIGNAL_CARD_INT Position */ 674 #define MXC_F_SDHC_INT_SIGNAL_CARD_INT ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_CARD_INT_POS)) /**< INT_SIGNAL_CARD_INT Mask */ 675 676 #define MXC_F_SDHC_INT_SIGNAL_RETUNING_POS 12 /**< INT_SIGNAL_RETUNING Position */ 677 #define MXC_F_SDHC_INT_SIGNAL_RETUNING ((uint16_t)(0x1UL << MXC_F_SDHC_INT_SIGNAL_RETUNING_POS)) /**< INT_SIGNAL_RETUNING Mask */ 678 679 /**@} end of group SDHC_INT_SIGNAL_Register */ 680 681 /** 682 * @ingroup sdhc_registers 683 * @defgroup SDHC_ER_INT_SIGNAL SDHC_ER_INT_SIGNAL 684 * @brief Error Interrupt Signal Enable. 685 * @{ 686 */ 687 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_TO_POS 0 /**< ER_INT_SIGNAL_CMD_TO Position */ 688 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_CMD_TO_POS)) /**< ER_INT_SIGNAL_CMD_TO Mask */ 689 690 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_CRC_POS 1 /**< ER_INT_SIGNAL_CMD_CRC Position */ 691 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_CMD_CRC_POS)) /**< ER_INT_SIGNAL_CMD_CRC Mask */ 692 693 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_END_BIT_POS 2 /**< ER_INT_SIGNAL_CMD_END_BIT Position */ 694 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_CMD_END_BIT_POS)) /**< ER_INT_SIGNAL_CMD_END_BIT Mask */ 695 696 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_IDX_POS 3 /**< ER_INT_SIGNAL_CMD_IDX Position */ 697 #define MXC_F_SDHC_ER_INT_SIGNAL_CMD_IDX ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_CMD_IDX_POS)) /**< ER_INT_SIGNAL_CMD_IDX Mask */ 698 699 #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_TO_POS 4 /**< ER_INT_SIGNAL_DATA_TO Position */ 700 #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_TO ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_DATA_TO_POS)) /**< ER_INT_SIGNAL_DATA_TO Mask */ 701 702 #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_CRC_POS 5 /**< ER_INT_SIGNAL_DATA_CRC Position */ 703 #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_DATA_CRC_POS)) /**< ER_INT_SIGNAL_DATA_CRC Mask */ 704 705 #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_END_BIT_POS 6 /**< ER_INT_SIGNAL_DATA_END_BIT Position */ 706 #define MXC_F_SDHC_ER_INT_SIGNAL_DATA_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_DATA_END_BIT_POS)) /**< ER_INT_SIGNAL_DATA_END_BIT Mask */ 707 708 #define MXC_F_SDHC_ER_INT_SIGNAL_CURR_LIM_POS 7 /**< ER_INT_SIGNAL_CURR_LIM Position */ 709 #define MXC_F_SDHC_ER_INT_SIGNAL_CURR_LIM ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_CURR_LIM_POS)) /**< ER_INT_SIGNAL_CURR_LIM Mask */ 710 711 #define MXC_F_SDHC_ER_INT_SIGNAL_AUTO_CMD_POS 8 /**< ER_INT_SIGNAL_AUTO_CMD Position */ 712 #define MXC_F_SDHC_ER_INT_SIGNAL_AUTO_CMD ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_AUTO_CMD_POS)) /**< ER_INT_SIGNAL_AUTO_CMD Mask */ 713 714 #define MXC_F_SDHC_ER_INT_SIGNAL_ADMA_POS 9 /**< ER_INT_SIGNAL_ADMA Position */ 715 #define MXC_F_SDHC_ER_INT_SIGNAL_ADMA ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_ADMA_POS)) /**< ER_INT_SIGNAL_ADMA Mask */ 716 717 #define MXC_F_SDHC_ER_INT_SIGNAL_TUNING_POS 10 /**< ER_INT_SIGNAL_TUNING Position */ 718 #define MXC_F_SDHC_ER_INT_SIGNAL_TUNING ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_TUNING_POS)) /**< ER_INT_SIGNAL_TUNING Mask */ 719 720 #define MXC_F_SDHC_ER_INT_SIGNAL_TAR_RESP_POS 12 /**< ER_INT_SIGNAL_TAR_RESP Position */ 721 #define MXC_F_SDHC_ER_INT_SIGNAL_TAR_RESP ((uint16_t)(0x1UL << MXC_F_SDHC_ER_INT_SIGNAL_TAR_RESP_POS)) /**< ER_INT_SIGNAL_TAR_RESP Mask */ 722 723 /**@} end of group SDHC_ER_INT_SIGNAL_Register */ 724 725 /** 726 * @ingroup sdhc_registers 727 * @defgroup SDHC_AUTO_CMD_ER SDHC_AUTO_CMD_ER 728 * @brief Auto CMD Error Status. 729 * @{ 730 */ 731 #define MXC_F_SDHC_AUTO_CMD_ER_NOT_EXCUTED_POS 0 /**< AUTO_CMD_ER_NOT_EXCUTED Position */ 732 #define MXC_F_SDHC_AUTO_CMD_ER_NOT_EXCUTED ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_NOT_EXCUTED_POS)) /**< AUTO_CMD_ER_NOT_EXCUTED Mask */ 733 734 #define MXC_F_SDHC_AUTO_CMD_ER_TO_POS 1 /**< AUTO_CMD_ER_TO Position */ 735 #define MXC_F_SDHC_AUTO_CMD_ER_TO ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_TO_POS)) /**< AUTO_CMD_ER_TO Mask */ 736 737 #define MXC_F_SDHC_AUTO_CMD_ER_CRC_POS 2 /**< AUTO_CMD_ER_CRC Position */ 738 #define MXC_F_SDHC_AUTO_CMD_ER_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_CRC_POS)) /**< AUTO_CMD_ER_CRC Mask */ 739 740 #define MXC_F_SDHC_AUTO_CMD_ER_END_BIT_POS 3 /**< AUTO_CMD_ER_END_BIT Position */ 741 #define MXC_F_SDHC_AUTO_CMD_ER_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_END_BIT_POS)) /**< AUTO_CMD_ER_END_BIT Mask */ 742 743 #define MXC_F_SDHC_AUTO_CMD_ER_INDEX_POS 4 /**< AUTO_CMD_ER_INDEX Position */ 744 #define MXC_F_SDHC_AUTO_CMD_ER_INDEX ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_INDEX_POS)) /**< AUTO_CMD_ER_INDEX Mask */ 745 746 #define MXC_F_SDHC_AUTO_CMD_ER_NOT_ISSUED_POS 7 /**< AUTO_CMD_ER_NOT_ISSUED Position */ 747 #define MXC_F_SDHC_AUTO_CMD_ER_NOT_ISSUED ((uint16_t)(0x1UL << MXC_F_SDHC_AUTO_CMD_ER_NOT_ISSUED_POS)) /**< AUTO_CMD_ER_NOT_ISSUED Mask */ 748 749 /**@} end of group SDHC_AUTO_CMD_ER_Register */ 750 751 /** 752 * @ingroup sdhc_registers 753 * @defgroup SDHC_HOST_CN_2 SDHC_HOST_CN_2 754 * @brief Host Control 2. 755 * @{ 756 */ 757 #define MXC_F_SDHC_HOST_CN_2_UHS_POS 0 /**< HOST_CN_2_UHS Position */ 758 #define MXC_F_SDHC_HOST_CN_2_UHS ((uint16_t)(0x3UL << MXC_F_SDHC_HOST_CN_2_UHS_POS)) /**< HOST_CN_2_UHS Mask */ 759 760 #define MXC_F_SDHC_HOST_CN_2_SIGNAL_V1_8_POS 3 /**< HOST_CN_2_SIGNAL_V1_8 Position */ 761 #define MXC_F_SDHC_HOST_CN_2_SIGNAL_V1_8 ((uint16_t)(0x1UL << MXC_F_SDHC_HOST_CN_2_SIGNAL_V1_8_POS)) /**< HOST_CN_2_SIGNAL_V1_8 Mask */ 762 763 #define MXC_F_SDHC_HOST_CN_2_DRIVER_STRENGTH_POS 4 /**< HOST_CN_2_DRIVER_STRENGTH Position */ 764 #define MXC_F_SDHC_HOST_CN_2_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_HOST_CN_2_DRIVER_STRENGTH_POS)) /**< HOST_CN_2_DRIVER_STRENGTH Mask */ 765 766 #define MXC_F_SDHC_HOST_CN_2_EXCUTE_POS 6 /**< HOST_CN_2_EXCUTE Position */ 767 #define MXC_F_SDHC_HOST_CN_2_EXCUTE ((uint16_t)(0x1UL << MXC_F_SDHC_HOST_CN_2_EXCUTE_POS)) /**< HOST_CN_2_EXCUTE Mask */ 768 769 #define MXC_F_SDHC_HOST_CN_2_SAMPLING_CLK_POS 7 /**< HOST_CN_2_SAMPLING_CLK Position */ 770 #define MXC_F_SDHC_HOST_CN_2_SAMPLING_CLK ((uint16_t)(0x1UL << MXC_F_SDHC_HOST_CN_2_SAMPLING_CLK_POS)) /**< HOST_CN_2_SAMPLING_CLK Mask */ 771 772 #define MXC_F_SDHC_HOST_CN_2_ASYNCH_INT_POS 14 /**< HOST_CN_2_ASYNCH_INT Position */ 773 #define MXC_F_SDHC_HOST_CN_2_ASYNCH_INT ((uint16_t)(0x1UL << MXC_F_SDHC_HOST_CN_2_ASYNCH_INT_POS)) /**< HOST_CN_2_ASYNCH_INT Mask */ 774 775 #define MXC_F_SDHC_HOST_CN_2_PRESET_VAL_EN_POS 15 /**< HOST_CN_2_PRESET_VAL_EN Position */ 776 #define MXC_F_SDHC_HOST_CN_2_PRESET_VAL_EN ((uint16_t)(0x1UL << MXC_F_SDHC_HOST_CN_2_PRESET_VAL_EN_POS)) /**< HOST_CN_2_PRESET_VAL_EN Mask */ 777 778 /**@} end of group SDHC_HOST_CN_2_Register */ 779 780 /** 781 * @ingroup sdhc_registers 782 * @defgroup SDHC_CFG_0 SDHC_CFG_0 783 * @brief Capabilities 0-31. 784 * @{ 785 */ 786 #define MXC_F_SDHC_CFG_0_TO_CLK_FREQ_POS 0 /**< CFG_0_TO_CLK_FREQ Position */ 787 #define MXC_F_SDHC_CFG_0_TO_CLK_FREQ ((uint32_t)(0x3FUL << MXC_F_SDHC_CFG_0_TO_CLK_FREQ_POS)) /**< CFG_0_TO_CLK_FREQ Mask */ 788 789 #define MXC_F_SDHC_CFG_0_TO_CLK_UNIT_POS 7 /**< CFG_0_TO_CLK_UNIT Position */ 790 #define MXC_F_SDHC_CFG_0_TO_CLK_UNIT ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_TO_CLK_UNIT_POS)) /**< CFG_0_TO_CLK_UNIT Mask */ 791 792 #define MXC_F_SDHC_CFG_0_CLK_FREQ_POS 8 /**< CFG_0_CLK_FREQ Position */ 793 #define MXC_F_SDHC_CFG_0_CLK_FREQ ((uint32_t)(0xFFUL << MXC_F_SDHC_CFG_0_CLK_FREQ_POS)) /**< CFG_0_CLK_FREQ Mask */ 794 795 #define MXC_F_SDHC_CFG_0_MAX_BLK_LEN_POS 16 /**< CFG_0_MAX_BLK_LEN Position */ 796 #define MXC_F_SDHC_CFG_0_MAX_BLK_LEN ((uint32_t)(0x3UL << MXC_F_SDHC_CFG_0_MAX_BLK_LEN_POS)) /**< CFG_0_MAX_BLK_LEN Mask */ 797 798 #define MXC_F_SDHC_CFG_0_BIT_8_POS 18 /**< CFG_0_BIT_8 Position */ 799 #define MXC_F_SDHC_CFG_0_BIT_8 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_BIT_8_POS)) /**< CFG_0_BIT_8 Mask */ 800 801 #define MXC_F_SDHC_CFG_0_ADMA2_POS 19 /**< CFG_0_ADMA2 Position */ 802 #define MXC_F_SDHC_CFG_0_ADMA2 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_ADMA2_POS)) /**< CFG_0_ADMA2 Mask */ 803 804 #define MXC_F_SDHC_CFG_0_HS_POS 21 /**< CFG_0_HS Position */ 805 #define MXC_F_SDHC_CFG_0_HS ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_HS_POS)) /**< CFG_0_HS Mask */ 806 807 #define MXC_F_SDHC_CFG_0_SDMA_POS 22 /**< CFG_0_SDMA Position */ 808 #define MXC_F_SDHC_CFG_0_SDMA ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_SDMA_POS)) /**< CFG_0_SDMA Mask */ 809 810 #define MXC_F_SDHC_CFG_0_SUSPEND_POS 23 /**< CFG_0_SUSPEND Position */ 811 #define MXC_F_SDHC_CFG_0_SUSPEND ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_SUSPEND_POS)) /**< CFG_0_SUSPEND Mask */ 812 813 #define MXC_F_SDHC_CFG_0_V3_3_POS 24 /**< CFG_0_V3_3 Position */ 814 #define MXC_F_SDHC_CFG_0_V3_3 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_V3_3_POS)) /**< CFG_0_V3_3 Mask */ 815 816 #define MXC_F_SDHC_CFG_0_V3_0_POS 25 /**< CFG_0_V3_0 Position */ 817 #define MXC_F_SDHC_CFG_0_V3_0 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_V3_0_POS)) /**< CFG_0_V3_0 Mask */ 818 819 #define MXC_F_SDHC_CFG_0_V1_8_POS 26 /**< CFG_0_V1_8 Position */ 820 #define MXC_F_SDHC_CFG_0_V1_8 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_V1_8_POS)) /**< CFG_0_V1_8 Mask */ 821 822 #define MXC_F_SDHC_CFG_0_BIT_64_SYS_BUS_POS 28 /**< CFG_0_BIT_64_SYS_BUS Position */ 823 #define MXC_F_SDHC_CFG_0_BIT_64_SYS_BUS ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_BIT_64_SYS_BUS_POS)) /**< CFG_0_BIT_64_SYS_BUS Mask */ 824 825 #define MXC_F_SDHC_CFG_0_ASYNC_INT_POS 29 /**< CFG_0_ASYNC_INT Position */ 826 #define MXC_F_SDHC_CFG_0_ASYNC_INT ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_ASYNC_INT_POS)) /**< CFG_0_ASYNC_INT Mask */ 827 828 #define MXC_F_SDHC_CFG_0_SLOT_TYPE_POS 30 /**< CFG_0_SLOT_TYPE Position */ 829 #define MXC_F_SDHC_CFG_0_SLOT_TYPE ((uint32_t)(0x3UL << MXC_F_SDHC_CFG_0_SLOT_TYPE_POS)) /**< CFG_0_SLOT_TYPE Mask */ 830 831 /**@} end of group SDHC_CFG_0_Register */ 832 833 /** 834 * @ingroup sdhc_registers 835 * @defgroup SDHC_CFG_1 SDHC_CFG_1 836 * @brief Capabilities 32-63. 837 * @{ 838 */ 839 #define MXC_F_SDHC_CFG_1_SDR50_POS 0 /**< CFG_1_SDR50 Position */ 840 #define MXC_F_SDHC_CFG_1_SDR50 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_SDR50_POS)) /**< CFG_1_SDR50 Mask */ 841 842 #define MXC_F_SDHC_CFG_1_SDR104_POS 1 /**< CFG_1_SDR104 Position */ 843 #define MXC_F_SDHC_CFG_1_SDR104 ((uint32_t)(0x0UL << MXC_F_SDHC_CFG_1_SDR104_POS)) /**< CFG_1_SDR104 Mask */ 844 845 #define MXC_F_SDHC_CFG_1_DDR50_POS 2 /**< CFG_1_DDR50 Position */ 846 #define MXC_F_SDHC_CFG_1_DDR50 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DDR50_POS)) /**< CFG_1_DDR50 Mask */ 847 848 #define MXC_F_SDHC_CFG_1_DRIVER_A_POS 4 /**< CFG_1_DRIVER_A Position */ 849 #define MXC_F_SDHC_CFG_1_DRIVER_A ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_A_POS)) /**< CFG_1_DRIVER_A Mask */ 850 851 #define MXC_F_SDHC_CFG_1_DRIVER_C_POS 5 /**< CFG_1_DRIVER_C Position */ 852 #define MXC_F_SDHC_CFG_1_DRIVER_C ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_C_POS)) /**< CFG_1_DRIVER_C Mask */ 853 854 #define MXC_F_SDHC_CFG_1_DRIVER_D_POS 6 /**< CFG_1_DRIVER_D Position */ 855 #define MXC_F_SDHC_CFG_1_DRIVER_D ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_D_POS)) /**< CFG_1_DRIVER_D Mask */ 856 857 #define MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS 8 /**< CFG_1_TIMER_CNT_TUNING Position */ 858 #define MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING ((uint32_t)(0xFUL << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)) /**< CFG_1_TIMER_CNT_TUNING Mask */ 859 860 #define MXC_F_SDHC_CFG_1_TUNING_SDR50_POS 13 /**< CFG_1_TUNING_SDR50 Position */ 861 #define MXC_F_SDHC_CFG_1_TUNING_SDR50 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_TUNING_SDR50_POS)) /**< CFG_1_TUNING_SDR50 Mask */ 862 863 #define MXC_F_SDHC_CFG_1_RETUNING_POS 14 /**< CFG_1_RETUNING Position */ 864 #define MXC_F_SDHC_CFG_1_RETUNING ((uint32_t)(0x3UL << MXC_F_SDHC_CFG_1_RETUNING_POS)) /**< CFG_1_RETUNING Mask */ 865 866 #define MXC_F_SDHC_CFG_1_CLK_MULTI_POS 16 /**< CFG_1_CLK_MULTI Position */ 867 #define MXC_F_SDHC_CFG_1_CLK_MULTI ((uint32_t)(0xFFUL << MXC_F_SDHC_CFG_1_CLK_MULTI_POS)) /**< CFG_1_CLK_MULTI Mask */ 868 869 /**@} end of group SDHC_CFG_1_Register */ 870 871 /** 872 * @ingroup sdhc_registers 873 * @defgroup SDHC_MAX_CURR_CFG SDHC_MAX_CURR_CFG 874 * @brief Maximum Current Capabilities. 875 * @{ 876 */ 877 #define MXC_F_SDHC_MAX_CURR_CFG_V3_3_POS 0 /**< MAX_CURR_CFG_V3_3 Position */ 878 #define MXC_F_SDHC_MAX_CURR_CFG_V3_3 ((uint32_t)(0xFFUL << MXC_F_SDHC_MAX_CURR_CFG_V3_3_POS)) /**< MAX_CURR_CFG_V3_3 Mask */ 879 880 #define MXC_F_SDHC_MAX_CURR_CFG_V3_0_POS 8 /**< MAX_CURR_CFG_V3_0 Position */ 881 #define MXC_F_SDHC_MAX_CURR_CFG_V3_0 ((uint32_t)(0xFFUL << MXC_F_SDHC_MAX_CURR_CFG_V3_0_POS)) /**< MAX_CURR_CFG_V3_0 Mask */ 882 883 #define MXC_F_SDHC_MAX_CURR_CFG_V1_8_POS 16 /**< MAX_CURR_CFG_V1_8 Position */ 884 #define MXC_F_SDHC_MAX_CURR_CFG_V1_8 ((uint32_t)(0xFFUL << MXC_F_SDHC_MAX_CURR_CFG_V1_8_POS)) /**< MAX_CURR_CFG_V1_8 Mask */ 885 886 /**@} end of group SDHC_MAX_CURR_CFG_Register */ 887 888 /** 889 * @ingroup sdhc_registers 890 * @defgroup SDHC_FORCE_CMD SDHC_FORCE_CMD 891 * @brief Force Event for Auto CMD Error Status. 892 * @{ 893 */ 894 #define MXC_F_SDHC_FORCE_CMD_NOT_EXCU_POS 0 /**< FORCE_CMD_NOT_EXCU Position */ 895 #define MXC_F_SDHC_FORCE_CMD_NOT_EXCU ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_NOT_EXCU_POS)) /**< FORCE_CMD_NOT_EXCU Mask */ 896 897 #define MXC_F_SDHC_FORCE_CMD_TO_POS 1 /**< FORCE_CMD_TO Position */ 898 #define MXC_F_SDHC_FORCE_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_TO_POS)) /**< FORCE_CMD_TO Mask */ 899 900 #define MXC_F_SDHC_FORCE_CMD_CRC_POS 2 /**< FORCE_CMD_CRC Position */ 901 #define MXC_F_SDHC_FORCE_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_CRC_POS)) /**< FORCE_CMD_CRC Mask */ 902 903 #define MXC_F_SDHC_FORCE_CMD_END_BIT_POS 3 /**< FORCE_CMD_END_BIT Position */ 904 #define MXC_F_SDHC_FORCE_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_END_BIT_POS)) /**< FORCE_CMD_END_BIT Mask */ 905 906 #define MXC_F_SDHC_FORCE_CMD_INDEX_POS 4 /**< FORCE_CMD_INDEX Position */ 907 #define MXC_F_SDHC_FORCE_CMD_INDEX ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_INDEX_POS)) /**< FORCE_CMD_INDEX Mask */ 908 909 #define MXC_F_SDHC_FORCE_CMD_NOT_ISSUED_POS 7 /**< FORCE_CMD_NOT_ISSUED Position */ 910 #define MXC_F_SDHC_FORCE_CMD_NOT_ISSUED ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_CMD_NOT_ISSUED_POS)) /**< FORCE_CMD_NOT_ISSUED Mask */ 911 912 /**@} end of group SDHC_FORCE_CMD_Register */ 913 914 /** 915 * @ingroup sdhc_registers 916 * @defgroup SDHC_FORCE_EVENT_INT_STAT SDHC_FORCE_EVENT_INT_STAT 917 * @brief Force Event for Error Interrupt Status. 918 * @{ 919 */ 920 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_TO_POS 0 /**< FORCE_EVENT_INT_STAT_CMD_TO Position */ 921 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_TO ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_TO_POS)) /**< FORCE_EVENT_INT_STAT_CMD_TO Mask */ 922 923 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_CRC_POS 1 /**< FORCE_EVENT_INT_STAT_CMD_CRC Position */ 924 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_CRC_POS)) /**< FORCE_EVENT_INT_STAT_CMD_CRC Mask */ 925 926 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_END_BIT_POS 2 /**< FORCE_EVENT_INT_STAT_CMD_END_BIT Position */ 927 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_END_BIT_POS)) /**< FORCE_EVENT_INT_STAT_CMD_END_BIT Mask */ 928 929 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_INDEX_POS 3 /**< FORCE_EVENT_INT_STAT_CMD_INDEX Position */ 930 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_INDEX ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_CMD_INDEX_POS)) /**< FORCE_EVENT_INT_STAT_CMD_INDEX Mask */ 931 932 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_TO_POS 4 /**< FORCE_EVENT_INT_STAT_DATA_TO Position */ 933 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_TO ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_TO_POS)) /**< FORCE_EVENT_INT_STAT_DATA_TO Mask */ 934 935 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_CRC_POS 5 /**< FORCE_EVENT_INT_STAT_DATA_CRC Position */ 936 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_CRC ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_CRC_POS)) /**< FORCE_EVENT_INT_STAT_DATA_CRC Mask */ 937 938 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_END_BIT_POS 6 /**< FORCE_EVENT_INT_STAT_DATA_END_BIT Position */ 939 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_END_BIT ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_DATA_END_BIT_POS)) /**< FORCE_EVENT_INT_STAT_DATA_END_BIT Mask */ 940 941 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CURR_LIMIT_POS 7 /**< FORCE_EVENT_INT_STAT_CURR_LIMIT Position */ 942 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_CURR_LIMIT ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_CURR_LIMIT_POS)) /**< FORCE_EVENT_INT_STAT_CURR_LIMIT Mask */ 943 944 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_AUTO_CMD_POS 8 /**< FORCE_EVENT_INT_STAT_AUTO_CMD Position */ 945 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_AUTO_CMD ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_AUTO_CMD_POS)) /**< FORCE_EVENT_INT_STAT_AUTO_CMD Mask */ 946 947 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_ADMA_POS 9 /**< FORCE_EVENT_INT_STAT_ADMA Position */ 948 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_ADMA ((uint16_t)(0x1UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_ADMA_POS)) /**< FORCE_EVENT_INT_STAT_ADMA Mask */ 949 950 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_VENDOR_POS 12 /**< FORCE_EVENT_INT_STAT_VENDOR Position */ 951 #define MXC_F_SDHC_FORCE_EVENT_INT_STAT_VENDOR ((uint16_t)(0x7UL << MXC_F_SDHC_FORCE_EVENT_INT_STAT_VENDOR_POS)) /**< FORCE_EVENT_INT_STAT_VENDOR Mask */ 952 953 /**@} end of group SDHC_FORCE_EVENT_INT_STAT_Register */ 954 955 /** 956 * @ingroup sdhc_registers 957 * @defgroup SDHC_ADMA_ER SDHC_ADMA_ER 958 * @brief ADMA Error Status. 959 * @{ 960 */ 961 #define MXC_F_SDHC_ADMA_ER_STATE_POS 0 /**< ADMA_ER_STATE Position */ 962 #define MXC_F_SDHC_ADMA_ER_STATE ((uint8_t)(0x3UL << MXC_F_SDHC_ADMA_ER_STATE_POS)) /**< ADMA_ER_STATE Mask */ 963 964 #define MXC_F_SDHC_ADMA_ER_LEN_MISMATCH_POS 2 /**< ADMA_ER_LEN_MISMATCH Position */ 965 #define MXC_F_SDHC_ADMA_ER_LEN_MISMATCH ((uint8_t)(0x1UL << MXC_F_SDHC_ADMA_ER_LEN_MISMATCH_POS)) /**< ADMA_ER_LEN_MISMATCH Mask */ 966 967 /**@} end of group SDHC_ADMA_ER_Register */ 968 969 /** 970 * @ingroup sdhc_registers 971 * @defgroup SDHC_ADMA_ADDR_0 SDHC_ADMA_ADDR_0 972 * @brief ADMA System Address 0-31. 973 * @{ 974 */ 975 #define MXC_F_SDHC_ADMA_ADDR_0_ADDR_POS 0 /**< ADMA_ADDR_0_ADDR Position */ 976 #define MXC_F_SDHC_ADMA_ADDR_0_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_ADMA_ADDR_0_ADDR_POS)) /**< ADMA_ADDR_0_ADDR Mask */ 977 978 /**@} end of group SDHC_ADMA_ADDR_0_Register */ 979 980 /** 981 * @ingroup sdhc_registers 982 * @defgroup SDHC_ADMA_ADDR_1 SDHC_ADMA_ADDR_1 983 * @brief ADMA System Address 32-63. 984 * @{ 985 */ 986 #define MXC_F_SDHC_ADMA_ADDR_1_ADDR_POS 0 /**< ADMA_ADDR_1_ADDR Position */ 987 #define MXC_F_SDHC_ADMA_ADDR_1_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDHC_ADMA_ADDR_1_ADDR_POS)) /**< ADMA_ADDR_1_ADDR Mask */ 988 989 /**@} end of group SDHC_ADMA_ADDR_1_Register */ 990 991 /** 992 * @ingroup sdhc_registers 993 * @defgroup SDHC_PRESET_0 SDHC_PRESET_0 994 * @brief Preset Value for Initialization. 995 * @{ 996 */ 997 #define MXC_F_SDHC_PRESET_0_SDCLK_FREQ_POS 0 /**< PRESET_0_SDCLK_FREQ Position */ 998 #define MXC_F_SDHC_PRESET_0_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_0_SDCLK_FREQ_POS)) /**< PRESET_0_SDCLK_FREQ Mask */ 999 1000 #define MXC_F_SDHC_PRESET_0_CLK_GEN_POS 10 /**< PRESET_0_CLK_GEN Position */ 1001 #define MXC_F_SDHC_PRESET_0_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_0_CLK_GEN_POS)) /**< PRESET_0_CLK_GEN Mask */ 1002 1003 #define MXC_F_SDHC_PRESET_0_DRIVER_STRENGTH_POS 14 /**< PRESET_0_DRIVER_STRENGTH Position */ 1004 #define MXC_F_SDHC_PRESET_0_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_0_DRIVER_STRENGTH_POS)) /**< PRESET_0_DRIVER_STRENGTH Mask */ 1005 1006 /**@} end of group SDHC_PRESET_0_Register */ 1007 1008 /** 1009 * @ingroup sdhc_registers 1010 * @defgroup SDHC_PRESET_1 SDHC_PRESET_1 1011 * @brief Preset Value for Default Speed. 1012 * @{ 1013 */ 1014 #define MXC_F_SDHC_PRESET_1_SDCLK_FREQ_POS 0 /**< PRESET_1_SDCLK_FREQ Position */ 1015 #define MXC_F_SDHC_PRESET_1_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_1_SDCLK_FREQ_POS)) /**< PRESET_1_SDCLK_FREQ Mask */ 1016 1017 #define MXC_F_SDHC_PRESET_1_CLK_GEN_POS 10 /**< PRESET_1_CLK_GEN Position */ 1018 #define MXC_F_SDHC_PRESET_1_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_1_CLK_GEN_POS)) /**< PRESET_1_CLK_GEN Mask */ 1019 1020 #define MXC_F_SDHC_PRESET_1_DRIVER_STRENGTH_POS 14 /**< PRESET_1_DRIVER_STRENGTH Position */ 1021 #define MXC_F_SDHC_PRESET_1_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_1_DRIVER_STRENGTH_POS)) /**< PRESET_1_DRIVER_STRENGTH Mask */ 1022 1023 /**@} end of group SDHC_PRESET_1_Register */ 1024 1025 /** 1026 * @ingroup sdhc_registers 1027 * @defgroup SDHC_PRESET_2 SDHC_PRESET_2 1028 * @brief Preset Value for High Speed. 1029 * @{ 1030 */ 1031 #define MXC_F_SDHC_PRESET_2_SDCLK_FREQ_POS 0 /**< PRESET_2_SDCLK_FREQ Position */ 1032 #define MXC_F_SDHC_PRESET_2_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_2_SDCLK_FREQ_POS)) /**< PRESET_2_SDCLK_FREQ Mask */ 1033 1034 #define MXC_F_SDHC_PRESET_2_CLK_GEN_POS 10 /**< PRESET_2_CLK_GEN Position */ 1035 #define MXC_F_SDHC_PRESET_2_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_2_CLK_GEN_POS)) /**< PRESET_2_CLK_GEN Mask */ 1036 1037 #define MXC_F_SDHC_PRESET_2_DRIVER_STRENGTH_POS 14 /**< PRESET_2_DRIVER_STRENGTH Position */ 1038 #define MXC_F_SDHC_PRESET_2_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_2_DRIVER_STRENGTH_POS)) /**< PRESET_2_DRIVER_STRENGTH Mask */ 1039 1040 /**@} end of group SDHC_PRESET_2_Register */ 1041 1042 /** 1043 * @ingroup sdhc_registers 1044 * @defgroup SDHC_PRESET_3 SDHC_PRESET_3 1045 * @brief Preset Value for SDR12. 1046 * @{ 1047 */ 1048 #define MXC_F_SDHC_PRESET_3_SDCLK_FREQ_POS 0 /**< PRESET_3_SDCLK_FREQ Position */ 1049 #define MXC_F_SDHC_PRESET_3_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_3_SDCLK_FREQ_POS)) /**< PRESET_3_SDCLK_FREQ Mask */ 1050 1051 #define MXC_F_SDHC_PRESET_3_CLK_GEN_POS 10 /**< PRESET_3_CLK_GEN Position */ 1052 #define MXC_F_SDHC_PRESET_3_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_3_CLK_GEN_POS)) /**< PRESET_3_CLK_GEN Mask */ 1053 1054 #define MXC_F_SDHC_PRESET_3_DRIVER_STRENGTH_POS 14 /**< PRESET_3_DRIVER_STRENGTH Position */ 1055 #define MXC_F_SDHC_PRESET_3_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_3_DRIVER_STRENGTH_POS)) /**< PRESET_3_DRIVER_STRENGTH Mask */ 1056 1057 /**@} end of group SDHC_PRESET_3_Register */ 1058 1059 /** 1060 * @ingroup sdhc_registers 1061 * @defgroup SDHC_PRESET_4 SDHC_PRESET_4 1062 * @brief Preset Value for SDR25. 1063 * @{ 1064 */ 1065 #define MXC_F_SDHC_PRESET_4_SDCLK_FREQ_POS 0 /**< PRESET_4_SDCLK_FREQ Position */ 1066 #define MXC_F_SDHC_PRESET_4_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_4_SDCLK_FREQ_POS)) /**< PRESET_4_SDCLK_FREQ Mask */ 1067 1068 #define MXC_F_SDHC_PRESET_4_CLK_GEN_POS 10 /**< PRESET_4_CLK_GEN Position */ 1069 #define MXC_F_SDHC_PRESET_4_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_4_CLK_GEN_POS)) /**< PRESET_4_CLK_GEN Mask */ 1070 1071 #define MXC_F_SDHC_PRESET_4_DRIVER_STRENGTH_POS 14 /**< PRESET_4_DRIVER_STRENGTH Position */ 1072 #define MXC_F_SDHC_PRESET_4_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_4_DRIVER_STRENGTH_POS)) /**< PRESET_4_DRIVER_STRENGTH Mask */ 1073 1074 /**@} end of group SDHC_PRESET_4_Register */ 1075 1076 /** 1077 * @ingroup sdhc_registers 1078 * @defgroup SDHC_PRESET_5 SDHC_PRESET_5 1079 * @brief Preset Value for SDR50. 1080 * @{ 1081 */ 1082 #define MXC_F_SDHC_PRESET_5_SDCLK_FREQ_POS 0 /**< PRESET_5_SDCLK_FREQ Position */ 1083 #define MXC_F_SDHC_PRESET_5_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_5_SDCLK_FREQ_POS)) /**< PRESET_5_SDCLK_FREQ Mask */ 1084 1085 #define MXC_F_SDHC_PRESET_5_CLK_GEN_POS 10 /**< PRESET_5_CLK_GEN Position */ 1086 #define MXC_F_SDHC_PRESET_5_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_5_CLK_GEN_POS)) /**< PRESET_5_CLK_GEN Mask */ 1087 1088 #define MXC_F_SDHC_PRESET_5_DRIVER_STRENGTH_POS 14 /**< PRESET_5_DRIVER_STRENGTH Position */ 1089 #define MXC_F_SDHC_PRESET_5_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_5_DRIVER_STRENGTH_POS)) /**< PRESET_5_DRIVER_STRENGTH Mask */ 1090 1091 /**@} end of group SDHC_PRESET_5_Register */ 1092 1093 /** 1094 * @ingroup sdhc_registers 1095 * @defgroup SDHC_PRESET_6 SDHC_PRESET_6 1096 * @brief Preset Value for SDR104. 1097 * @{ 1098 */ 1099 #define MXC_F_SDHC_PRESET_6_SDCLK_FREQ_POS 0 /**< PRESET_6_SDCLK_FREQ Position */ 1100 #define MXC_F_SDHC_PRESET_6_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_6_SDCLK_FREQ_POS)) /**< PRESET_6_SDCLK_FREQ Mask */ 1101 1102 #define MXC_F_SDHC_PRESET_6_CLK_GEN_POS 10 /**< PRESET_6_CLK_GEN Position */ 1103 #define MXC_F_SDHC_PRESET_6_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_6_CLK_GEN_POS)) /**< PRESET_6_CLK_GEN Mask */ 1104 1105 #define MXC_F_SDHC_PRESET_6_DRIVER_STRENGTH_POS 14 /**< PRESET_6_DRIVER_STRENGTH Position */ 1106 #define MXC_F_SDHC_PRESET_6_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_6_DRIVER_STRENGTH_POS)) /**< PRESET_6_DRIVER_STRENGTH Mask */ 1107 1108 /**@} end of group SDHC_PRESET_6_Register */ 1109 1110 /** 1111 * @ingroup sdhc_registers 1112 * @defgroup SDHC_PRESET_7 SDHC_PRESET_7 1113 * @brief Preset Value for DDR50. 1114 * @{ 1115 */ 1116 #define MXC_F_SDHC_PRESET_7_SDCLK_FREQ_POS 0 /**< PRESET_7_SDCLK_FREQ Position */ 1117 #define MXC_F_SDHC_PRESET_7_SDCLK_FREQ ((uint16_t)(0x3FFUL << MXC_F_SDHC_PRESET_7_SDCLK_FREQ_POS)) /**< PRESET_7_SDCLK_FREQ Mask */ 1118 1119 #define MXC_F_SDHC_PRESET_7_CLK_GEN_POS 10 /**< PRESET_7_CLK_GEN Position */ 1120 #define MXC_F_SDHC_PRESET_7_CLK_GEN ((uint16_t)(0x1UL << MXC_F_SDHC_PRESET_7_CLK_GEN_POS)) /**< PRESET_7_CLK_GEN Mask */ 1121 1122 #define MXC_F_SDHC_PRESET_7_DRIVER_STRENGTH_POS 14 /**< PRESET_7_DRIVER_STRENGTH Position */ 1123 #define MXC_F_SDHC_PRESET_7_DRIVER_STRENGTH ((uint16_t)(0x3UL << MXC_F_SDHC_PRESET_7_DRIVER_STRENGTH_POS)) /**< PRESET_7_DRIVER_STRENGTH Mask */ 1124 1125 /**@} end of group SDHC_PRESET_7_Register */ 1126 1127 /** 1128 * @ingroup sdhc_registers 1129 * @defgroup SDHC_SLOT_INT SDHC_SLOT_INT 1130 * @brief Slot Interrupt Status. 1131 * @{ 1132 */ 1133 #define MXC_F_SDHC_SLOT_INT_INT_SIGNALS_POS 0 /**< SLOT_INT_INT_SIGNALS Position */ 1134 #define MXC_F_SDHC_SLOT_INT_INT_SIGNALS ((uint16_t)(0x1UL << MXC_F_SDHC_SLOT_INT_INT_SIGNALS_POS)) /**< SLOT_INT_INT_SIGNALS Mask */ 1135 1136 /**@} end of group SDHC_SLOT_INT_Register */ 1137 1138 /** 1139 * @ingroup sdhc_registers 1140 * @defgroup SDHC_HOST_CN_VER SDHC_HOST_CN_VER 1141 * @brief Host Controller Version. 1142 * @{ 1143 */ 1144 #define MXC_F_SDHC_HOST_CN_VER_SPEC_VER_POS 0 /**< HOST_CN_VER_SPEC_VER Position */ 1145 #define MXC_F_SDHC_HOST_CN_VER_SPEC_VER ((uint16_t)(0xFFUL << MXC_F_SDHC_HOST_CN_VER_SPEC_VER_POS)) /**< HOST_CN_VER_SPEC_VER Mask */ 1146 1147 #define MXC_F_SDHC_HOST_CN_VER_VEND_VER_POS 8 /**< HOST_CN_VER_VEND_VER Position */ 1148 #define MXC_F_SDHC_HOST_CN_VER_VEND_VER ((uint16_t)(0xFFUL << MXC_F_SDHC_HOST_CN_VER_VEND_VER_POS)) /**< HOST_CN_VER_VEND_VER Mask */ 1149 1150 /**@} end of group SDHC_HOST_CN_VER_Register */ 1151 1152 #ifdef __cplusplus 1153 } 1154 #endif 1155 1156 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SDHC_REGS_H_ 1157
